DETAILED ACTION
Claims 1-20 are presented for examination.
This office action is in response to submission of application on 19-DEC-2022.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10-FEB-2023, 1-JUNE-2023, 23-OCT-2023 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Objections
Claims 10 objected to because of the following informalities:
In claim 10, line 1, “wherein allocate” should read “wherein to allocate”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation "the region of the memory tier" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5-9, 11, 13, 14, 16, 17 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by
Erickson et al., U.S. Pub. No. 20220179799 (hereinafter “Erickson”).
Regarding claim 1: Erickson teaches An apparatus comprising:
a memory controller, when connected to at least one memory device in a multi-tiered memory system comprising a near memory and far memory, is to allocate a region of the near memory to a requester based on receipt of a request, wherein ([0017-0018], Erickson teaches a set of memory control components that are connected to memory devices, and contains an access/allocation engine which coordinates memory pages allocated to processes, and receives memory allocation requests. The memory control components also teach a far memory, in the form of an auxiliary remote, MV-attached memory 116, that is separate to a local memory subsystem 115.).
circuitry to transmit at least one memory read command and address information to the multi-tiered memory system to read data from the multi-tiered memory system and circuitry to transmit at least one memory write command and address information to the multi-tiered memory system to write data to the multi-tiered memory system, wherein ([0018], Erickson teaches that the access/allocation engine also responds to loads/stores directed to MV-attached memory by issuing corresponding signals to an auxiliary memory, including a fabric interface which transmits memory load/store instructions. Furthermore, in [0022], Erickson teaches that a process issues load/stores to a virtual address. Therefore, the circuitry to transmit at least one memory read (load) command and address information to read data from the system, and to transmit at least one memory write (store) command and address information to the memory system to write data is taught.)
the near memory comprises at least one memory connected to the memory controller via a memory interface and the far memory comprises at least one memory connected to the memory controller via a network. ([0016], Erickson teaches that memory access requests are routed to local or remote memory, the remote memory including operating memory on servers other than the requesting server. Furthermore, [0017], Erickson teaches a memory subsystem coupled to a memory control unit via traces, within a server, which corresponds to the local memory and is interpreted to be the near memory comprising memory connected to the memory controller via a memory interface. While not explicit, in light of [0017], where Erickson teaches a network interface card that enables connection to a communication network, to enable data transport, the remote memory belonging on other servers and having a network of servers where access is allowed to be transmitted across teaches the far memory connected to the memory controller via a network.)
Regarding claim 5: Erickson teaches all limitations of claim 1, from which claim 5 depends.
Erickson further teaches the request comprises one or more of: requester identifier, amount of memory to reserve, tier of memory in which to reserve memory, level of priority of the requester, and/or latency sensitivity of the requester. ([0023], Erickson teaches that to fulfill memory allocation requests from local CPUs, a parametrized request specifying memory location, and that during fulfillment, the process identifier for the process that triggered the allocation is stored.)
Regarding claim 6: Erickson teaches all limitations of claim 1, from which claim 6 depends.
Erickson further teaches the multi-tiered memory system comprises one or more of: a volatile memory device and/or a non-volatile memory device. ([0017], Erickson teaches that the memory subsystem used in an example embodiment may be dynamic random access memory (DRAM), which is known in the art to be a type of volatile memory.)
Regarding claim 7: Erickson teaches all limitations of claim 1, from which claim 7 depends.
Erickson further teaches a server comprising at least one processor communicatively coupled to the memory controller, wherein the at least one processor is to execute an operating system (OS) to configure the memory controller to provide access to the region of the near memory to the requester. ([0017], Erickson teaches that each example server contains a CPU which performs the memory management. Further, in [0019], Erickson teaches that an allocation scheme invokes a local operating system’s page-fault handler to map addresses, and that the LPAs are issued by the CPU’s memory management unit and directed to a local memory controller, in which the LPA may decode to a page of local memory. The CPU directing LPAs, which are part of an overall allocation scheme involving the execution of an operating system, to a local memory controller, which decodes to local memory, is interpreted to be the claimed processor coupled to the memory controller, wherein an operating system configures a memory controller to provide access to the region of the near memory to the requester.)
Regarding claim 8: Erickson teaches At least one non-transitory computer-readable medium comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to: ([0041-0042], Erickson teaches one or more computer readable media with instructions that can be processed by a processing entity to perform the invention.)
Erickson further teaches execute an operating system (OS) to configure a memory controller, when connected to at least one memory device in a multi-tiered memory system, to allocate a region of a near memory tier to a requester based on a request from the OS. ([0019], Erickson teaches that an allocation scheme invokes a local operating system’s page-fault handler to map addresses, and that the LPAs (which define a region) are issued by the CPU’s memory management unit and directed to a local memory controller, in which the LPA may decode to a page of local memory. Further, in [0017], Erickson teaches that the system includes a local operating memory and an auxiliary memory, interpreted to be the multi-tiered memory system. The CPU directing LPAs, which are part of an overall allocation scheme involving the execution of an operating system, to a local memory controller, which decodes to local memory, is interpreted to be the claimed execute an operating system (OS) to configure a memory controller, when connected to at least one memory device in a multi-tiered memory system, to allocate a region of a near memory tier to a requester based on a request from the OS)
Regarding claim 9: Erickson teaches all limitations of claim 8, from which claim 9 depends.
Erickson further teaches circuitry to transmit at least one memory read command and address information to the multi-tiered memory system to read data from the multi-tiered memory system and circuitry to transmit at least one memory write command and address information to the multi-tiered memory system to write data to the multi-tiered memory system. ([0018], Erickson teaches an access/allocation engine that responds to loads/stores directed to MV-attached memory by issuing corresponding signals to an auxiliary memory, including a fabric interface which transmits memory load/store instructions. Furthermore, in [0022], Erickson teaches that a process issues load/stores to a virtual address. Therefore, the circuitry to transmit at least one memory read (load) command and address information to read data from the system, and to transmit at least one memory write (store) command and address information to the memory system to write data is taught.)
Regarding claim 11: Erickson teaches all limitations of claim 8, from which claim 11 depends.
Erickson further teaches the multi-tiered memory system comprises the near memory tier and a far memory tier and wherein the near memory tier is to provide a lower latency of data retrieval and/or higher bandwidth of data retrieval than that of the far memory tier. ([0019], Erickson teaches that memory-pooling servers can include hierarchically accessed storage devices, where the local (near memory tier) memory implements high bandwidth, low latency operating memory, and where the auxiliary (far memory tier) memory has a higher latency than the local memory.)
Regarding claim 13: Erickson teaches all limitations of claim 8, from which claim 13 depends.
Erickson further teaches the request comprises one or more of: requester identifier, amount of memory to reserve, tier of memory in which to reserve memory, level of priority of the requester, and/or latency sensitivity of the requester. ([0023], Erickson teaches that to fulfill memory allocation requests from local CPUs, a parametrized request specifying memory location, and that during fulfillment, the process identifier for the process that triggered the allocation is stored.)
Regarding claim 14: Erickson teaches A method comprising:
in a data center comprising at least one processor, a memory controller, and a multi-tiered memory system: the memory controller allocating a region of a near memory tier of the multi-tiered memory system to a requester based on receipt of a request, ([0017-0018], Erickson teaches a data center with servers, which each contain a set of memory control components that are connected to memory devices, and contains an access/allocation engine which coordinates memory pages allocated to processes, and receives memory allocation requests. The memory control components also teach a far memory, in the form of an auxiliary remote, MV-attached memory 116, that is separate to a local memory subsystem 115.).
circuitry to transmit at least one memory read command and address information to the multi-tiered memory system to read data from the multi-tiered memory system and circuitry to transmit at least one memory write command and address information to the multi-tiered memory system to write data to the multi-tiered memory system, wherein ([0018], Erickson teaches that the access/allocation engine also responds to loads/stores directed to MV-attached memory by issuing corresponding signals to an auxiliary memory, including a fabric interface which transmits memory load/store instructions. Furthermore, in [0022], Erickson teaches that a process issues load/stores to a virtual address. Therefore, the circuitry to transmit at least one memory read (load) command and address information to read data from the system, and to transmit at least one memory write (store) command and address information to the memory system to write data is taught.)
the near memory tier comprises at least one memory connected to the memory controller via a memory interface. (Furthermore, [0017], Erickson teaches a memory subsystem coupled to a memory control unit via traces, within a server, which corresponds to the local memory and is interpreted to be the near memory comprising memory connected to the memory controller via a memory interface.)
Regarding claim 16: Erickson teaches all limitations of claim 14, from which claim 16 depends.
Erickson further teaches the multi-tiered memory system comprises the near memory tier and a far memory tier and wherein the near memory tier is to provide a lower latency of data retrieval and/or higher bandwidth of data retrieval than that of the far memory tier. ([0019], Erickson teaches that memory-pooling servers can include hierarchically accessed storage devices, where the local (near memory tier) memory implements high bandwidth, low latency operating memory, and where the auxiliary (far memory tier) memory has a higher latency than the local memory.)
Regarding claim 17: Erickson teaches all limitations of claim 16, from which claim 17 depends.
Erickson further teaches the region of the memory tier comprises a region of the near memory tier. ([0022], Erickson teaches that a set of LPAs (defining a region) issued as part of a memory allocation request is directed to a local memory controller, such that the LPAs decode to pages of local memory, which is interpreted to be the claimed region of the (allocation-requested) memory tier comprising a region of the near memory tier.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4, 10, 12, 15, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over
Erickson et al., U.S. Pub. No. 20220179799 (hereinafter “Erickson”) in view of
HERDRICH et al., U.S. Pub. No. 20190340123 (hereinafter “Herdrich”)
Regarding claim 2: Erickson teaches all limitations of claim 1, from which claim 2 depends.
While Erickson teaches allocation of near memory, Erickson does not appear to explicitly disclose the memory controller is to allocate a region of the near memory to the requester based on priority of the request.
However, Herdrich teaches the memory controller is to allocate a region of the near memory to the requester based on priority of the request. ([0065-0068], Herdrich teaches that an application can request locking (corresponding to allocating) of a cache region including a lowest level cache (corresponding to the near memory), and that the request can be granted or denied, with an embodiment being that the locking can be provided based on the priority of an application that requests cache locking.).
Erickson and Herdrich are analogous art because they are from the same field of endeavor, memory management systems.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Erickson and Herdrich to achieve the combined result of the apparatus of claim 1, which allocates a region of the near memory to the requester based on priority of the request.
One of ordinary skill in the art would have been motivated to make this modification in order to allow commonly shared resources such as a last level cache (near memory) to be favored for workloads, such as when there is a service level objective that guarantees an upper bound for latency as discussed in Herdrich [0002].
Regarding claim 3: Erickson teaches all limitations of claim 1, from which claim 3 depends.
Erickson further teaches to allocate a region of the near memory to the requester, a processor-executed operating system (OS) is to configure the memory controller to provide access to the region of the memory tier ([0019], Erickson teaches that an allocation scheme invokes a local operating system’s page-fault handler to map addresses, and that the LPAs are issued by the CPU’s memory management unit and directed to a local memory controller, in which the LPA may decode to a page of local memory. The overall allocation scheme involving the execution of an operating system, to a local memory controller, which decodes to local memory, is interpreted to be the claimed processor-executed operating system configuring a memory controller to provide access to the region of the near memory to the requester.)
Erickson does not appear to explicitly disclose provide access to the region of the memory tier to the requester and no other service.
However, Herdrich teaches provide access to the region of the memory tier to the requester and no other service ([0042] and Table 2, Herdrich teaches that for a cache allocation, a set of fields in an input can be used. One of the fields includes an Access/Level field which sets an allocation to be private or public, wherein when it is private, there will be a protection fault upon illegal access by other threads in the group. The illegal access causing a protection fault from other threads is interpreted to be the providing access to no other service.).
Erickson and Herdrich are analogous art because they are from the same field of endeavor, memory management systems.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Erickson and Herdrich to achieve the combined result of the apparatus of claim 1, which allocates a region of the near memory with an operating system that configures a memory controller, to provide access to a region of memory to only the requester, and no others.
One of ordinary skill in the art would have been motivated to make this modification in order to allow commonly shared resources such as a last level cache (near memory) to be favored for workloads, such as when there is a service level objective that guarantees an upper bound for latency as discussed in Herdrich [0002].
Regarding claim 4: Erickson teaches all limitations of claim 1, from which claim 4 depends.
Erickson does not appear to explicitly disclose the memory controller is to selectively deny the request based on a portion of the region of the memory tier being reserved for another requester.
However, Herdrich teaches the memory controller is to selectively deny the request based on a portion of the region of the memory tier being reserved for another requester ([0057], Herdrich teaches that, as part of a process to permit or deny cache locking (reserving), the controller declines a request from an application if part of the region is not available. Furthermore, in [0029], Herdrich teaches a table that tracks which portions of a cache system are occupied and what is available for locking or occupation. While not explicit, since the occupied portions are described separately to the portions that are available, and the controller declines requests for a region that is not available, and that the portions that are occupied are obviously not available, Herdrich teaches the selectively denying the request based on the portion of the memory tier being reserved for another requester.).
Erickson and Herdrich are analogous art because they are from the same field of endeavor, memory management systems.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Erickson and Herdrich to achieve the combined result of the apparatus of claim 1, which denies requests to allocate a region when a portion of the region is reserved for another requester.
One of ordinary skill in the art would have been motivated to make this modification in order to allow commonly shared resources such as a last level cache (near memory) to be favored for workloads, such as when there is a service level objective that guarantees an upper bound for latency as discussed in Herdrich [0002].
Regarding claim 10: Erickson teaches all limitations of claim 8, from which claim 10 depends.
Erickson further teaches allocate a region of a near memory tier to a requester based on a request from the OS, a processor-executed operating system (OS) is to configure the memory controller to provide access to the region of the memory tier to the requester ([0019], Erickson teaches that an allocation scheme invokes a local operating system’s page-fault handler to map addresses, and that the LPAs are issued by the CPU’s memory management unit and directed to a local memory controller, in which the LPA may decode to a page of local memory. The overall allocation scheme involving the execution of an operating system, to a local memory controller, which decodes to local memory, is interpreted to be the claimed processor-executed operating system configuring a memory controller to provide access to the region of the near memory to the requester.)
Erickson does not appear to explicitly disclose provide access to the region of the memory tier to the requester and no other service.
However, Herdrich teaches provide access to the region of the memory tier to the requester and no other service ([0042] and Table 2, Herdrich teaches that for a cache allocation, a set of fields in an input can be used. One of the fields includes an Access/Level field which sets an allocation to be private or public, wherein when it is private, there will be a protection fault upon illegal access by other threads in the group. The illegal access causing a protection fault from other threads is interpreted to be the providing access to no other service.).
Erickson and Herdrich are analogous art because they are from the same field of endeavor, memory management systems.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Erickson and Herdrich to achieve the combined result of claim 8, which further includes allocating a region of the near memory with an operating system that configures a memory controller, to provide access to a region of memory to only the requester, and no others.
One of ordinary skill in the art would have been motivated to make this modification in order to allow commonly shared resources such as a last level cache (near memory) to be favored for workloads, such as when there is a service level objective that guarantees an upper bound for latency as discussed in Herdrich [0002].
Regarding claim 12: Erickson teaches all limitations of claim 8, from which claim 12 depends.
Erickson does not appear to explicitly disclose the memory controller is to selectively deny the request based on a portion of the region of the memory tier being reserved for another requester.
However, Herdrich teaches the memory controller is to selectively deny the request based on a portion of the region of the memory tier being reserved for another requester. ([0057], Herdrich teaches that, as part of a process to permit or deny cache locking (reserving), the controller declines a request from an application if part of the region is not available. Furthermore, in [0029], Herdrich teaches a table that tracks which portions of a cache system are occupied and what is available for locking or occupation. While not explicit, since the occupied portions are described separately to the portions that are available, and the controller declines requests for a region that is not available, and that the portions that are occupied are obviously not available, Herdrich teaches the selectively denying the request based on the portion of the memory tier being reserved for another requester.).
Erickson and Herdrich are analogous art because they are from the same field of endeavor, memory management systems.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Erickson and Herdrich to achieve the combined result of claim 8, which further denies requests to allocate a region when a portion of the region is reserved for another requester.
One of ordinary skill in the art would have been motivated to make this modification in order to allow commonly shared resources such as a last level cache (near memory) to be favored for workloads, such as when there is a service level objective that guarantees an upper bound for latency as discussed in Herdrich [0002].
Regarding claim 15: Erickson teaches all limitations of claim 14, from which claim 15 depends.
While Erickson teaches allocation of near memory, Erickson does not appear to explicitly disclose the memory controller allocating a region of a near memory tier of the multi-tiered memory system to a requester based on receipt of a request is based on a priority level of the request.
However, Herdrich teaches the memory controller allocating a region of a near memory tier of the multi-tiered memory system to a requester based on receipt of a request is based on a priority level of the request. ([0065-0068], Herdrich teaches that an application can request locking (corresponding to allocating) of a cache region including a lowest level cache (corresponding to the near memory), and that the request can be granted or denied, with an embodiment being that the locking can be provided based on the priority of an application that requests cache locking.).
Erickson and Herdrich are analogous art because they are from the same field of endeavor, memory management systems.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Erickson and Herdrich to achieve the combined result of claim 14, further including which allocating a region of the near memory to the requester based on priority of the request.
One of ordinary skill in the art would have been motivated to make this modification in order to allow commonly shared resources such as a last level cache (near memory) to be favored for workloads, such as when there is a service level objective that guarantees an upper bound for latency as discussed in Herdrich [0002].
Regarding claim 18: The combination of Erickson and Herdrich teaches all limitations of claim 15, from which claim 18 depends.
Erickson/Herdrich further teaches the memory controller selectively denying the request based on a portion of the region of the memory tier being reserved for another requester. ([0057], Herdrich teaches that, as part of a process to permit or deny cache locking (reserving), the controller declines a request from an application if part of the region is not available. Furthermore, in [0029], Herdrich teaches a table that tracks which portions of a cache system are occupied and what is available for locking or occupation. While not explicit, since the occupied portions are described separately to the portions that are available, and the controller declines requests for a region that is not available, and that the portions that are occupied are obviously not available, Herdrich teaches the selectively denying the request based on the portion of the memory tier being reserved for another requester.)
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as in claim 15.
Regarding claim 19: The combination of Erickson and Herdrich teaches all limitations of claim 15, from which claim 19 depends.
Erickson/Herdrich further teaches based on a portion of the region of the memory tier being reserved for another requester, the memory controller accepting the request based at least on the request being associated with a higher priority level than a priority level of the another requester. ([0067], Herdrich teaches an embodiment where the cache controller can provide cache locking based on the priority of an application that requests cache locking, which may cause the eviction of locked content of another application, with an example of a request from a higher priorty application can cause the eviction of content from a lower priority application. The cache controller providing the cache locking in this scenario is interpreted to be the claimed memory controller accepting the request.)
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as in claim 15.
Regarding claim 20: The combination of Erickson and Herdrich teaches all limitations of claim 15, from which claim 20 depends.
Erickson/Herdrich further teaches the request comprises one or more of: requester identifier, amount of memory to reserve, tier of memory in which to reserve memory, level of priority of the requester, and/or latency sensitivity of the requester. ([0023], Erickson teaches that to fulfill memory allocation requests from local CPUs, a parametrized request specifying memory location, and that during fulfillment, the process identifier for the process that triggered the allocation is stored.)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Klein, U.S. Pub. No. 20190045009, teaches a system which defines a reserved, local, and remote area, where host clients use farther memory when the target memory has no available space.
Haywood et al., U.S. Pub. No. 20210132999, teaches an allocation scheme which can allocate memory with parameters that specifies an average latency limit.
Herdrich et al., U.S. Pub. No. 20210042228, teaches a cache locking system that uses priority levels to determine whether to grant or deny requests, which also teaches isolation including permitted access of a region of memory by a particular application, but not another.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAITLYN HUNG PHAM whose telephone number is (571)272-6333. The examiner can normally be reached Mon-Thurs 8:00-6:00 EST.
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/K.H.P./Examiner, Art Unit 2133
/KHOA D DOAN/Primary Examiner, Art Unit 2133