DETAILED ACTION
Claims 1 – 20 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/19/2022 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 6-10, 13-15, 18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ould-Ahmed-Vall (US 2020/0409770).
As per claims 1, 10 and 15:
Taking claim 1 as exemplary, Ould-Ahmed-Vall discloses a processor core comprising fetch circuitry to fetch a first instruction comprising a first opcode which is to correspond to a first one or more components of the processor core (Ould-Ahmed-Vall: Paragraph [0207] – [0208], operands in the save offload instruction identify the components); a decoder circuit coupled to the fetch circuitry, the decoder to decode the first instruction to generate a first decoded instruction (Ould-Ahmed-Vall: Paragraph [0207], save offload instruction decoded in pipeline 2191); and an execution circuit coupled to receive the first decoded instruction, wherein the execution circuit is to execute the first decoded instruction to save a microarchitectural state of the first one or more components to a repository of the processor core (Ould-Ahmed-Vall: Paragraph [0208] – [0210], saving the state of the selected components in the save-restore region 2321, a designated region in memory).
As per claims 4, 13 and 18:
Taking claim 4 as exemplary, Ould-Ahmed-Vall discloses comprising a micro-operation cache, wherein the first one or more components is the micro-operation cache (Ould-Ahmed-Vall: Paragraph [0208], interpreting the data components stored with the save offload instruction as being taken from a micro-operations cache equivalent).
As per claims 6, 14 and 20:
Taking claim 6 as exemplary, Ould-Ahmed-Vall discloses the fetch circuitry is further to fetch a second instruction comprising a second opcode which is to correspond to the first one or more components (Ould-Ahmed-Vall: Paragraph [0207] – [0208], operands in the save offload instruction identify the components); the decoder is further to decode the second instruction to generate a second decoded instruction (Ould-Ahmed-Vall: Paragraph [0207], save offload instruction decoded in pipeline 2191); and the execution circuit is further to execute the second decoded instruction to restore the microarchitectural state from the repository to the first one or more components (Ould-Ahmed-Vall: Paragraph [0212] – [0213], the restore instruction to return components from the save-restore region of memory).
As per claim 7:
Ould-Ahmed-Vall discloses the microarchitectural state is a first microarchitectural state, and wherein: the fetch circuitry is further to fetch a third instruction comprising a third opcode which is to correspond to a second one or more components of the processor core (Ould-Ahmed-Vall: Paragraph [0207] – [0208], operands in the save offload instruction identify the components); the decoder is further to decode the third instruction to generate a third decoded instruction (Ould-Ahmed-Vall: Paragraph [0207], save offload instruction decoded in pipeline 2191); and the execution circuit is further to execute the third decoded instruction to save a second microarchitectural state of the second one or more components to the repository (Ould-Ahmed-Vall: Paragraph [0208] – [0210], saving the state of the selected components in the save-restore region 2321, a designated region in memory).
As per claim 8:
Ould-Ahmed-Vall discloses the fetch circuitry is further to fetch a fourth instruction comprising a fourth opcode which is to correspond to the second one or more components (Ould-Ahmed-Vall: Paragraph [0207] – [0208], operands in the save offload instruction identify the components); the decoder is further to decode the fourth instruction to generate a fourth decoded instruction (Ould-Ahmed-Vall: Paragraph [0207], save offload instruction decoded in pipeline 2191); and the execution circuit is further to execute the fourth decoded instruction to restore the second microarchitectural state from the repository to the second one or more components (Ould-Ahmed-Vall: Paragraph [0212] – [0213], the restore instruction to return components from the save-restore region of memory).
As per claim 9:
Ould-Ahmed-Vall discloses the microarchitectural state is a first microarchitectural state, and wherein: the fetch circuitry is further to fetch a second instruction comprising a second opcode which is to correspond to a second one or more components of the processor core (Ould-Ahmed-Vall: Paragraph [0207] – [0208], operands in the save offload instruction identify the components); the decoder is further to decode the second instruction to generate a second decoded instruction (Ould-Ahmed-Vall: Paragraph [0207], save offload instruction decoded in pipeline 2191); and the execution circuit is further to execute the second decoded instruction to save a second microarchitectural state of the second one or more components to the repository (Ould-Ahmed-Vall: Paragraph [0208] – [0210], saving the state of the selected components in the save-restore region 2321, a designated region in memory).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3, 5, 11-12, 16-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Ould-Ahmed-Vall as applied to claims 1, 10 and 15 above, and further in view of Reid (GB2574042A).
As per claims 2, 11 and 16:
Ould-Ahmed-Vall does not specifically teach that the first one or more components is a branch prediction unit.
However, Reid teaches the saving of the branch prediction state in a memory separate from the branch predictor (Reid: Page 17 lines 17-27) as a way to prevent an attacker from being able to corrupt the branch prediction state (Reid: Page 17 line 17 – Page 18 line 14).
It would have been obvious to one of ordinary skill in the art at the time of filing for Ould-Ahmed-Vall to implement its techniques of saving component data to the branch predictor as taught by Reid in order to prevent an attacker from being able to corrupt the branch prediction state (Reid: Page 17 line 17 – Page 18 line 14).
As per claims 3, 12 and 17:
Ould-Ahmed-Vall does not specifically teach that the first one or more components is a branch target buffer.
However, Reid teaches the saving of the branch prediction state in a memory separate from the branch target buffer (Reid: Page 18 lines 1 - 7) as a way to prevent an attacker from being able to corrupt the branch target buffer state (Reid: Page 18 lines 1 - 14).
It would have been obvious to one of ordinary skill in the art at the time of filing for Ould-Ahmed-Vall to implement its techniques of saving component data to the branch target buffer as taught by Reid in order to prevent an attacker from being able to corrupt the branch target buffer state (Reid: Page 18 lines 1 - 14).
As per claims 5 and 19:
Ould-Ahmed-Vall discloses a micro operation cache where the first one or more components comprises two or more components (Ould-Ahmed-Vall: Paragraph [0208], interpreting the data components stored with the save offload instruction as being taken from a micro-operations cache equivalents).
Ould-Ahmed-Vall does not specifically disclose that the components include a branch prediction unit and a branch target buffer.
However, Reid teaches the saving of the branch prediction state and a branch target buffer in a memory separate from the branch predictor (Reid: Page 17 lines 17-27 and Page 18 lines 1 - 7) as a way to prevent an attacker from being able to corrupt the branch prediction state (Reid: Page 17 line 17 – Page 18 line 14).
It would have been obvious to one of ordinary skill in the art at the time of filing for Ould-Ahmed-Vall to implement its techniques of saving state data to the branch predictor and the branch target buffer as taught by Reid in order to prevent an attacker from being able to corrupt the branch prediction state (Reid: Page 17 line 17 – Page 18 line 14).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Moshe et al (US 2024/0153572) teaches restore commands to load snapshot data into buffers registers and caches. Al Sheikh et al (US 2021/0064378) teaches swapping and restoring context specific branch predictor states in a processor. Grewal et al (US 2019/0138720) teaches side channel attack prevention by maintaining architectural state consistency.
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/ZACHARY K HUSON/Primary Examiner, Art Unit 2181