Notice of Pre-AIA or AIA Status 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 2. NO restrictions warranted at initial time of filing for patent. Information Disclosure Statement 3 . The information disclosure statement (IDS) submitted on 12/19/2022 , the submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Oath/Declaration 4 . Applicant’s Oath was filed on 12/19/2022 . Drawings 5 . Applicant’s drawings filed on 12/19/2022 has been inspected and is in compliance with MPEP 608.01. Specification 6 . Applicant’s specification filed on 12/19/2022 has been inspected and is in compliance with MPEP 608.02. Claim Objections 7 . NO objections warranted at initial time of filing for patent. Remarks 8. Examiner request Applicant review relevant prior art under the conclusion of this office action. Allowable Subject Matter 9. Claim 5 , 8, 9, 14 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 10. Claim s 1-4, 6, 10-13, and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over U . S . Publication No. 20210203504 hereinafter Brandt U . S . Publication No. 20220066809 hereinafter Liu. As per claim 1, Brandt discloses: A processor core (Fig. 1, element 104 and Fig. 2, element 200) comprising: a decoder circuit (Fig. 2, element 206) to decode an instruction to enable a first hardware (HW) thread of a processor core ( para 0048 “ In certain embodiments, an encryption or decryption instruction is according to any of the disclosure herein. In one embodiment, e.g., in response to a request to perform an operation, the instruction (e.g., macro-instruction) is fetched from storage 202 and sent to decoder 206 . In the depicted embodiment, the decoder 206 (e.g., decoder circuit) decodes the instruction into a decoded instruction ( e.g., one or more micro-instructions or micro-operations). The decoded instruction is then sent for execution, e.g., via scheduler circuit 208 to schedule the decoded instruction for execution. ”) to access a trusted execution environment (TEE) ( para 0032 “ For example, limiting use of a handle to only an OS (e.g., ring 0) only, to encryption only, to decryption only, to being virtual machine (VM) specific (e.g., assuming a virtual machine monitor (VMM) does not set up guests to share handle space), to being process specific, to being (e.g., secure) trusted execution environment specific, or any combination thereof. In one embodiment, a trusted execution environment is a (e.g., secure) enclave. In one embodiment, a trusted execution environment is a trusted domain (TD), e.g., a TD that is being worked on where an entire VM (e.g., guest) is run in a way that it is protected against attack from a malicious VMM that is managing it. ”) , wherein the decoder circuit is to generate a decoded instruction (para 0048 “ In the depicted embodiment, the decoder 206 (e.g., decoder circuit) decodes the instruction into a decoded instruction (e.g., one or more micro-instructions or micro-operations) . ”) ; and an execution circuit to execute the decoded instruction with the processor core ( para 0048 “ The decoded instruction is then sent for execution, e.g., via scheduler circuit 208 to schedule the decoded instruction for execution. ” Para 0049 “T he scheduler circuit(s) may schedule one or more operations associated with decoded instructions, including one or more operations decoded from an encryption or decryption instruction, for execution on the execution circuit 212 .”) , comprising: the execution circuit to perform an evaluation to determine (para 0053 “ In one embodiment of a decryption instruction, execution circuit 212 (e.g., unit) is to determine an encryption key from the handle 216 (e.g., as discussed herein) and if no exception (e.g., fault from not matching the authentication tag), then is to use the encryption key to decrypt the encrypted data 220 into unencrypted (e.g., decrypted) data 218 . ”) Brandt does not discloses: whether, for each other HW thread of the processor core which is currently in an active state, the other HW thread is currently authorized to access the TEE; and the execution circuit to generate a signal, based on the evaluation, to indicate whether the first HW thread is authorized to access the TEE Liu discloses: whether, for each other HW thread of the processor core which is currently in an active state, the other HW thread is currently authorized to access the TEE; ( para 0025- 0026 “ [0025] FIG. 1 is a flowchart illustrating a secure scheduling method for synchronously entering a trusted execution environment in a hyper-threading scenario according to an example implementation. As shown in FIG. 1, the method can include the following steps. In response to that a logical processor running on a physical processor core generates a trusted execution environment entry event through an approach provided by a virtual machine monitor, label the logical processor with a state of expecting to enter a trusted execution environment . ” Fig. 2, para 0033 “ The hypervisor needs to perform other operations in addition to executing the ENCLS[EADD] instruction and the ENCLS[EINIT] instruction to create the enclave. For example, assuming that mapping relationship 1 in the extended page table shown in FIG. 2 corresponds to the enclave created above, the hypervisor can restrict the application program from entering the enclave directly through mapping relationship 1 . In this case, the hypervisor can configure mapping relationship 1 as having read and write permissions but not an execution permission, or the hypervisor can refuse to generate mapping relationship 1 in the extended page table . Certainly, an EPC memory range is usually predetermined and fixed. Therefore, mapping relationship 1 above can cover the entire EPC memory range and is set as having no execution permission, so that mapping relationship 1 is set to correspond to all enclaves, without having to temporarily set a corresponding mapping relationship in the extended page table after each enclave creation or setting the mapping relationship as having no execution permission. Accordingly, when the application program in the logical processor enters the enclave through the extended page table, a page table translation error will be caused as mapping relationship 1 is non-executable or does not exist, causing a VM exit. By locating a cause for the VM exit, the hypervisor can identify an intent of the application program on directly entering the enclave, and further determine that the application program may be an untrusted application . Such practice can avoid scheduling a logical processor running the untrusted application to enter the enclave and prevent the untrusted application from stealing privacy data. Therefore, a VM exit can be triggered when an extended page table translation error occurs and it is identified that an instruction for entering a trusted execution environment (for example, an ENCLS[EENTER] instruction in the SGX technology) is executed. By locating a cause for the VM exit, the hypervisor can detect a trusted execution environment entry event and determine that the trusted execution environment entry event is generated by any logical processor by directly accessing a trusted execution environment built on a physical processor core .” ). and the execution circuit to generate a signal, based on the evaluation, to indicate whether the first HW thread is authorized to access the TEE ( para 0034 “ In the present specification, the hypervisor provides multiple secure approaches used to enter the enclave. First approach: The present specification can provide a new hypercall used to initiate entry into a trusted execution environment, which can be implemented by executing a hypercall TEE entry instruction. The hypercall TEE entry instruction can trigger a VM exit. By locating a cause for the VM exit, the hypervisor can detect a trusted execution environment entry event, and determine that the trusted execution environment entry event is generated by any logical processor through the approach provided by the hypervisor, and further the hypervisor helps the logical processor enter the TEE. Second approach: As described above, since mapping relationship 1 cannot be used to enter the enclave, the hypervisor can add mapping relationship 2 shown in FIG. 2 to the extended page table. Mapping relationship 2 can be used to map to the springboard code at address “b,” and the springboard code can be executed by any logical processor to help the logical processor enter the TEE. Although the second approach does not trigger a VM exit, it can still be considered that the approach is provided by the hypervisor because the springboard code is provided by the hypervisor. Third approach: The first approach and the second approach are combined. The springboard code provided by the hypervisor can include the above-mentioned hypercall TEE entry instruction, so that after executing the springboard code, any logical processor can enter a TEE with the assistance of the springboard code and the hypervisor. ” Para 0036 “ As shown in FIG. 3, the second extended page table includes mapping relationship 1 having read, write, and execution permissions and the like, and includes mapping relationship 4 used to map springboard code .” Para 0038 “ If the hypervisor determines that the logical processor is allowed to enter the enclave, the hypervisor first switches a page table used by the logical processor from the first extended page table to the second extended page table; then, labels the logical processor with a state of expecting to enter the enclave; and finally, keeps waiting until all the logical processors on the CPU are labeled with the state of expecting to enter the enclave . In this case, it can be ensured that an untrusted application cannot use the CPU resources and sensitive data generated by the enclave will not be stolen. T he hypervisor can trigger a return to virtualization, so as to hand over the CPU control right to the guest machine . As such, each logical processor can enter the enclave by executing the TEE entry instruction. The TEE entry instruction is used to enter a TEE. For example, in the SGX technology, the TEE entry instruction can be ENCLS[EENTER] or ENCLS[ERESUME], which is used to enter or re-enter an enclave. ”) Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify the processor core of Brandt to include whether, for each other HW thread of the processor core which is currently in an active state, the other HW thread is currently authorized to access the TEE; and the execution circuit to generate a signal, based on the evaluation, to indicate whether the first HW thread is authorized to access the TEE, as taught by Liu. The motivation would have been to securely entering a trusted execution environment in a hyper-threading (Liu paragraph 0004). As per claim 2, Brandt in view of Liu discloses: The processor core of claim 1, wherein the execution circuit to perform the evaluation comprises the execution circuit to make a first determination as to whether, after an expiration of a threshold period of time, any active HW thread which is a sibling of the first HW thread is unable to access the TEE ( Brandt para 0034 “ In the depicted embodiment, a core of (e.g., each core of) hardware processor 100 includes a plurality of logical cores (e.g., logical processing elements or logical processors), for example, where M is any integer 1 or greater. In certain embodiments, each of physical core 104 ( 1 ) to physical core 104 (N) supports multithreading (e.g., executing two or more parallel sets of operations or threads on a first and second logical core) , and may do so in a variety of ways including time sliced multithreading , simultaneous multithreading (e.g., where a single physical core provides a respective logical core for each of the threads (e.g., hardware threads) that physical core is simultaneously multithreading), or a combination thereof (e.g., time sliced fetching and decoding and simultaneous multithreading thereafter). ”) . As per claim 3 , Brandt in view of Liu discloses: The processor core of claim 1, wherein the signal is to enable an entry of the first HW thread into the TEE using a respective hardware-reserved thread state (Brandt under para 0074, TABLES 1, 2, and 3, handling generation instruction with reserved fields) As per claim 4 , Brandt in view of Liu discloses: The processor core of claim 3, wherein the signal is a first signal, and wherein the execution circuit to execute the decoded instruction with the processor core further comprises the execution circuit to generate a second signal, based on the evaluation, to wake up another HW thread of the processor core, wherein the other HW thread is to enter into the TEE using a respective hardware- reserved thread state ( Brandt para 0034 and under para 0074, TABLES 1, 2, and 3, handling generation instruction with reserved fields ) and (Liu para 0033, 0034, and 0038, though Brandt discloses determining, Liu discloses a first signal and a second signal based on evaluation. The motivation would have been to securely entering a trusted execution environment in a hyper-threading (Liu paragraph 0004). ) As per claim 6 , Brandt in view of Liu discloses: The processor core of claim 1, wherein the execution circuit to execute the second decoded instruction further comprises the execution circuit to: make a first determination that one or more other HW threads of the processor core are active in the TEE; make a second determination that an execution by the first HW thread is expected to continue outside of the TEE; and based on the first determination and the second determination, generate a third signal to force the one or more other HW threads to exit the TEE (Liu para 0033, 0034, and 0038, though Brandt discloses determining, Liu discloses first, and second determination, and generate a third signal based on evaluation. The motivation would have been to securely entering a trusted execution environment in a hyper-threading (Liu paragraph 0004). ) As per claim 10, the implementation processor core of claim 1 will execute the method of claim 10. The claim is analyzed with respect to claim 1. As per claim 11, the claim is analyzed with respect to claim 2. As per claim 1 2 , the claim is analyzed with respect to claim 3 . As per claim 1 3 , the claim is analyzed with respect to claim 4 . As per claim 1 5 , the claim is analyzed with respect to claim 6 . As per claim 16, the implementation processor core of claim 1 will execute the system (Brandt Figs. 1-3) of claim 16. The claim is analyzed with respect to claim 1. As per claim 1 7 , the claim is analyzed with respect to claim 2. As per claim 1 8 , the claim is analyzed with respect to claim 3 . As per claim 1 9 , the claim is analyzed with respect to claim 4 . 11. Claim s 7 is rejected under 35 U.S.C. 103 a s being unpatentable over Brandt in view of Liu, and further in view of U.S. Publication No. 20220207187 hereinafter Constable. As per claim 6 , Brandt in view of Liu discloses: The processor core of claim 1, wherein the evaluation is a first evaluation, and wherein the signal is a first signal, (Liu para 0033, 0034, and 0038, though Brandt discloses determining, Liu discloses evaluation of a signal. The motivation would have been to securely entering a trusted execution environment in a hyper-threading (Liu paragraph 0004). ) Brandt in view of Liu does not disclose: the processor core further comprises circuitry to: detect a transition to an awake state by a second HW thread of the processor core, the transition while the first HW thread is in the TEE; based on the transition, perform a second evaluation to determine whether the second HW thread is to execute in the TEE; and based on the second evaluation, generate a second signal to exit the first HW thread from the TEE. Constable discloses: the processor core further comprises circuitry to: detect a transition to an awake state by a second HW thread of the processor core, the transition while the first HW thread is in the TEE; based on the transition, perform a second evaluation to determine whether the second HW thread is to execute in the TEE; and based on the second evaluation, generate a second signal to exit the first HW thread from the TEE ( para 0075 “ FIG. 6 illustrates a method of handling an asynchronous exit 610 (AEX) of the execution of code from an enclave 602 that utilizes an enclave resume instruction 622 (ERESUME) that invokes a handler 624 to handle an operating system signal caused by the asynchronous exit and then resumes execution of the code from the enclave according to embodiments of the disclosure. In certain embodiments, enclave 602 is a trusted (e.g., for security purposes) execution environment (e.g., an architecturally protected enclave) for user code, untrusted (e.g., for security purposes) run-time system 604 (uRTS) is untrusted user code, operating system (OS) 606 is untrusted, and ISA 608 (e.g., processor) is trusted. FIG. 6 illustrates how an ERESUME instruction according to this disclosure can be used to handle signals more efficiently, e.g., without requiring a nested ECALL as compared with FIG. 4). .” Para 0077 “ In one embodiment, immediately following ERESUME 622 , the enclave 602 is notified that an AEX 610 had occurred, and enclave 602 (e.g., via its handler 624 ) can respond by handling the signal (e.g., to take an action to remove the trigger of the interrupt/exception) . After the signal has been processed, the enclave 602 thread resumes execution where the AEX 610 had occurred in certain embodiments . Note that this approach uses only two enclave operations (i.e., AEX and ERESUME) in contrast to an enclave exception handling model that additionally requires entry into the enclave via EENTER to handle the exception followed by an EEXIT (see, e.g., FIG. 4). ” Para 0084 “ T urning again to FIGS. 1-2, embodiments of an ERESUME (with return-to-handler (RTH) functionality) instruction may be implemented by adding and/or modifying certain fields . While example below may be utilized with a certain ISA (e.g., SGX extension), it should be understood that embodiments herein can be applied similarly to other ISAs, e.g., implementing a TEE. ”) . Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify the processor core of Brandt to include the processor core further comprises circuitry to: detect a transition to an awake state by a second HW thread of the processor core, the transition while the first HW thread is in the TEE; based on the transition, perform a second evaluation to determine whether the second HW thread is to execute in the TEE; and based on the second evaluation, generate a second signal to exit the first HW thread from the TEE , as taught by Constable. The motivation would have been to securely to receive and handle software interrupts and (e.g., software and/or hardware) exceptions in order to mitigat e against attac ks. Conclusion 12. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. A. U . S . Publication No. 20220126210 discloses on paragraph 0122 “ FIG. 6 illustrates an additional execution unit 600 , according to an embodiment. The execution unit 600 may be a compute-optimized execution unit for use in, for example, a compute engine tile 340 A- 340 D as in FIG. 3C, but is not limited as such. Variants of the execution unit 600 may also be used in a graphics engine tile 310 A- 310 D as in FIG. 3B. In one embodiment, the execution unit 600 includes a thread control unit 601 , a thread state unit 602 , an instruction fetch/prefetch unit 603 , and an instruction decode unit 604 . The execution unit 600 additionally includes a register file 606 that stores registers that can be assigned to hardware threads within the execution unit. The execution unit 600 additionally includes a send unit 607 and a branch unit 608 . In one embodiment, the send unit 607 and branch unit 608 can operate similarly as the send unit 530 and a branch unit 532 of the graphics execution unit 508 of FIG. 5B. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT GARY S GRACIA whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-5192 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday-Friday 9am-6pm . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Philip Chea can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 5712723951 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GARY S GRACIA/ Primary Examiner, Art Unit 2499