CTNF 18/085,011 CTNF 82548 DETAILED ACTION 1. Claims 1-25 are pending in the application. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia 2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA 4. Claim (s) 1, 2, and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jia et al (hereafter Jia)(US Pub. 20230074229) in view of Badaroglu et al (hereafter Badaroglu) (US Pub. 20230025068) . 5. As to claim 1, Jia discloses a compute-in-memory (CiM) accelerator system ([0011] and [0014] CiM and Neural network accelerator) comprising: a plurality of in-memory tiles, an array of memory devices for storing a 2D weight-matrix representing at least a portion of a neural network model layer ([0201] tiled array, fig. 11, weights as matrix elements; [0262]-[0264] two dimensional and fig. 10 neural network layers); wherein at least one in-memory tile is configured to perform vector-matrix multiplications (VMM) from successive neural network layers mapped, and no in-memory tile is configured to represent vector-matrix multiplications of non-successive neural network layers ([0013], [0064], [0079] matrix vector multiplication, matrix elements mapped). Jia does not disclose each in-memory tile comprising more than one tier arranged in the Z dimension and the vector-matrix multiplication mapped into more than one tier. However, Badaroglu discloses each in-memory tile comprising more than one tier arranged in the Z dimension and the vector-matrix multiplication mapped into more than one tier ([0096] Every depth cycle, one slice at depth N.sub.i is read. For example, during the first depth cycle, a slice of depth N.sub.1 is read, during the second depth cycle, a second slice of depth N.sub.2 is read, and so on for each depth N.sub.i. Thus, teaching more than one tier (slice) arranged. When taken in combination with the vector-matrix multiplication as in Jia, the combination of Jia and Badaroglu teach the claimed limitations. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention, to modify the teachings of Jia, by incorporating the tiers as taught by Badaroglu, for the benefit of performing computation-in-memory with increased accuracy (Badaroglu [0005]). 6. As to claim 2, the combination of Jia and Badaroglu discloses wherein at least two in-memory tiles store a 2D weight-matrix representing at least a portion of the same neural network model layer (Jia, [0100]-[0105]). 7. As to claim 4, the combination of Jia and Badaroglu discloses wherein N neural network model layers are assigned to tiers of in-memory tiles (Badaroglu [0096]), said assignment of N neural network model layers to tiers of in-memory tiles being optimized for a sample batch-size (Badaroglu [0071] Batch size) . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 8. Claim s 8-25 are allowed. 12-151-08 AIA 07-43 12-51-08 Claim s 3 and 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: 9. Claim 3 recites at least wherein 2D weight matrices representing at least a portion of at least two successive neural network layers are mapped into the same tier of the same in-memory tile. Claim 5 recites at least wherein of said N neural network model layers, an amount Di of successive neural network model layers are assigned to a given in- memory tile i at tiers of that tile i, a usage of successive Di neural network model layers at the given in-memory tile i being collapsed into one continuous time-period. Claims 8 and 12 recite at least wherein a mapping of a sequence of at least Ntier1 neural network model layers to tiers of successive in- memory tiles is optimized for a finite input batch-size m of an incoming workflow, said mapping comprising at least an assignment of layers Nstart to Nstart + Ntier1- 1 of the neural network model to a first tier (tier 1) of successive in-memory tiles 1 to Ntiles, each first tier of the successive in-memory tiles 1 to Ntiles configured for storing data representing a 2D weight-matrix for processing at the corresponding neural network model layer; and an assignment of layer Nstart + Ntier1 of the neural network model to a second tier (tier 2) of in-memory tile 1, the second tier of in-memory tile 1 configured for storing data representing a 2D weight-matrix for processing at the corresponding neural network model layer, wherein said Ntiles is a minimum number of tiles chosen such that the first batch member completes processing in tier 1 of tile Nties no sooner than the mth batch member completes processing in tier 1 of in-memory tile 1; and a controller unit associated with each in-memory tile configured for controlling a 2D weight-matrix multiplication operation of at least a portion of a neural network model layer at a tier of said in-memory tile. Claims 15 and 22 recite at least mapping of a sequence of greater than N neural network model layers to tiers of successive in-memory tiles optimized for a large sample batch-size m of an incoming workflow, said mapping comprising at least an assignment of a pre-determined amount of successive neural network model layers to respective successive tiers of a single in-memory tile, each successive tier of the single in-memory tile configured for storing data representing a 2D weight-matrix for processing at the corresponding neural network model layer; and a hardware controller device configured for controlling a 2D weight-matrix multiplication operation at each said successive neural network model layer at each said successive tier of said given in-memory tile. The closest prior art of record US Pub. 20230074229 teaches a compute-in-memory (CiM) accelerator system as in claim 1. However, the prior art of record does not teach or suggest at least wherein 2D weight matrices representing at least a portion of at least two successive neural network layers are mapped into the same tier of the same in-memory tile as in claim 3; wherein of said N neural network model layers, an amount Di of successive neural network model layers are assigned to a given in- memory tile i at tiers of that tile i, a usage of successive Di neural network model layers at the given in-memory tile i being collapsed into one continuous time-period, as in claim 5; wherein a mapping of a sequence of at least Ntier1 neural network model layers to tiers of successive in- memory tiles is optimized for a finite input batch-size m of an incoming workflow, said mapping comprising at least an assignment of layers Nstart to Nstart + Ntier1- 1 of the neural network model to a first tier (tier 1) of successive in-memory tiles 1 to Ntiles, each first tier of the successive in-memory tiles 1 to Ntiles configured for storing data representing a 2D weight-matrix for processing at the corresponding neural network model layer; and an assignment of layer Nstart + Ntier1 of the neural network model to a second tier (tier 2) of in-memory tile 1, the second tier of in-memory tile 1 configured for storing data representing a 2D weight-matrix for processing at the corresponding neural network model layer, wherein said Ntiles is a minimum number of tiles chosen such that the first batch member completes processing in tier 1 of tile Nties no sooner than the mth batch member completes processing in tier 1 of in-memory tile 1; and a controller unit associated with each in-memory tile configured for controlling a 2D weight-matrix multiplication operation of at least a portion of a neural network model layer at a tier of said in-memory tile, as in claims 8 and 12; and mapping of a sequence of greater than N neural network model layers to tiers of successive in-memory tiles optimized for a large sample batch-size m of an incoming workflow, said mapping comprising at least an assignment of a pre-determined amount of successive neural network model layers to respective successive tiers of a single in-memory tile, each successive tier of the single in-memory tile configured for storing data representing a 2D weight-matrix for processing at the corresponding neural network model layer; and a hardware controller device configured for controlling a 2D weight-matrix multiplication operation at each said successive neural network model layer at each said successive tier of said given in-memory tile, as in claims 15 and 22. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL D YAARY whose telephone number is (571)270-1249. The examiner can normally be reached Mon-Fri 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571)272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL D. YAARY/ Primary Examiner, Art Unit 2151 Application/Control Number: 18/085,011 Page 2 Art Unit: 2151 Application/Control Number: 18/085,011 Page 3 Art Unit: 2151 Application/Control Number: 18/085,011 Page 4 Art Unit: 2151 Application/Control Number: 18/085,011 Page 5 Art Unit: 2151 Application/Control Number: 18/085,011 Page 6 Art Unit: 2151 Application/Control Number: 18/085,011 Page 7 Art Unit: 2151 Application/Control Number: 18/085,011 Page 8 Art Unit: 2151
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