CTNF 18/085,291 CTNF 99013 DETAILED ACTION This Office Action is in response to the Applicant Election filed on 03/25/2026. Currently, claims 1-20 are pending in the application. Currently, claims 11-14 and 16-20 are withdrawn. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of Group I, Species I in the reply filed on 03/25/2026 is acknowledged. Claims 11 and 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-selected invention, there being no allowable generic or linking claim. Further, claims 12-14 do not read on the elected Species (Figs. 2 & 4) and are withdrawn by the Examiner. (The Examiner notes that claim 12-14 reads on Species II, Fig. 3E) Claims 1-10 and 15 are examined in this Office action. Information Disclosure Statement The information disclosure statements (IDS) submitted on 10/17/2025 and 02/27/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the Examiner. Claim Objections Claim 5 is objected to because of the following informality: In claim 5, “a bottom surface” should read “the bottom surface”. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-6 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by MA et al. (US Pub. No. 2016/0322290) . Regarding independent claim 1, Ma teaches an electronic device (Fig. 1F) comprising: at least one layer (Fig. 1F, 157b, ¶ [0033]) formed from glass; a plurality of through glass vias (Fig. 1F, 165 corresponding to 157b, ¶ [0035]) formed within the at least one layer; wherein each of the through glass vias has a perimeter (Fig. 1F, portion of the perimeter of 160 in contact with 158a, ¶ [0033]) corresponding to a first opening (Fig. 1F, opening in 157b below 158a) on a first surface (Fig. 1F, top surface of 157b) of the glass layer and an edge (Fig. 1F, sidewall edges of 160 in contact with 158b, ¶ [0033]) corresponding to a second opening (Fig. 1F, opening in 157b above 158b) on a second (Fig. 1F, bottom surface of 157b) , opposing, surface of the glass layer; and a metallic conductor plug (Fig. 1F, 165, ¶ [0035]) filling an interior of the plurality of through glass vias, the metallic conductor plug including an exposed surface (Fig. 1F, portion of 165 above 157b and exposed to 158a) , the exposed surface including; a central region (Fig. 1F, portion of 165 above 157b and horizontally overlapping with 158a) ; and an edge region (Fig. 1F, portion of 165 at a same level as top surface of 157b and in contact with a bottom surface of 158a) , wherein the edge is substantially coplanar with at least one of a top surface (Fig. 1F, top surface of 157b) or a bottom surface (Fig. 1F, bottom surface of 157b) of the at least one layer (Fig. 1F) . Regarding claim 2, Ma teaches the electronic device of claim 1, and Ma teaches a buffer layer (Fig. 1F, 158a, ¶ [0041]) coupled to at least one of the first surface (Fig. 1F, 158a is over the top surface of 157b) and the second, opposing, surface (Ma teaches at least one option required by this claim) ; wherein the buffer layer extends beyond the perimeter of the through glass via (Fig. 1F, 158a horizontally extends beyond the perimeter sidewall portions of 160 in contact with 158a) ; a through hole (Fig. 1F, 165 corresponding to 158a and 157b, ¶ [0035]) extending through the buffer layer from the first surface towards the second surface (Fig. 1F, bottom surface of 157b) . Regarding claim 3, Ma teaches the electronic device of claim 2, and Ma teaches that an angle formed between a wall of the through glass via (Fig. 1F, 165 corresponding to 157b, ¶ [0035]) and the buffer layer (Fig. 1F, 158a, ¶ [0041]) extending is approximately perpendicular (Fig. 1F, the angle between the sidewall of 165 directly above the top surface of 157b and 158a appears to be approximately perpendicular) . Regarding claim 4, Ma teaches the electronic device of claim 1, and Ma teaches that the metallic conductor plug (Fig. 1F, 165, ¶ [0035]) abuts a buffer layer (Fig. 1F, 158a, ¶ [0041]) at the edge region (Fig. 1F, portion of 165 at a same level as top surface of 157b and in contact with a bottom surface of 158a) . Regarding claim 5, Ma teaches the electronic device of claim 1, and Ma teaches a buffer layer (Fig. 1F, 158a + 158b, ¶ [0041]) coupled with the top surface (Fig. 1F, top surface of 157b) of the at least one layer and a bottom surface (Fig. 1F, top surface of 157b) of the at least one layer. Regarding claim 6, Ma teaches the electronic device of claim 5, and Ma teaches that the buffer layer (Fig. 1F, 158a + 158b, ¶ [0041]) extends over the edge region (Fig. 1F, portion of 165 at a same level as top surface of 157b and in contact with a bottom surface of 158a) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 8 and 15 are rejected under 35 U.S.C. 103 as being obvious over MA et al. (US Pub. No. 2016/0322290). Regarding independent claim 8, Ma teaches an electronic system (Fig. 1F) comprising: a die (Fig. 1A, 110, ¶ [0037]) ; a substrate (Fig. 1F, 100, ¶ [0037]) coupled to the die comprising: a prepatterned glass layer (Fig. 1F, 157b, ¶ [0033]) , the prepatterned glass layer comprising: a first exposed surface (Fig. 1F, top surface of 157b exposed to 158a) and a second exposed surface (Fig. 1F, bottom surface of 157b exposed to 158b) ; a plurality of through holes (Fig. 1F, 165, ¶ [0035]) formed within the prepatterned glass layer, each of the plurality of through holes has a first end (Fig. 1F, top surface of 165) and a second end (Fig. 1F, bottom surface of 165) ; and a layer of copper plating (Fig. 1F, 160, ¶ [0036] teaches that 160 can be a metal such as copper, tin, silver, or other metals. It would be obvious to select copper 160 for the material in order to reduce manufacturing costs. Further, it has been held that choosing from a finite number of identified, predictable solutions with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).) extending within each through hole of the plurality of through holes, the copper plating including a first copper plating surface (Fig. 1F, outer perimeter of the top half of 160 at least partially corresponds to the top end of 165) corresponding with the first end and a second copper plating surface (Fig. 1F, outer perimeter of the bottom half of 160 at least partially corresponds to the bottom end of 165) corresponding with the second end; wherein the first copper plating surface includes a ring flush with the first exposed surface (Fig. 1F, portion of the outer perimeter of the top half of 160 at a same level as the top surface of 157b and under 158a) and circumnavigating an interior of each of the plurality of through holes (Fig. 1A, left and right portions of the perimeter of 165 that is flush with the top surface of 157b) ; wherein the second copper plating surface includes a ring (Fig. 1F, portion of the outer perimeter of the bottom half of 160 at a same level as the bottom surface of 157b and above 158b) flush with the second exposed surface and circumnavigating the interior of each of the plurality of through holes (Fig. 1A, left and right portions of the perimeter of 165 that is flush with the bottom surface of of 157b) . Regarding claim 15, Ma teaches the electronic system of claim 8, and Ma teaches a buffer layer (Fig. 1F, 133a, ¶ [0042] teaches a dielectric material that is vertically above the portion of the outer perimeter of the top half of 160 at a same level as the top surface of 157b and under 158a) extends over the ring of the first copper plating surface (Fig. 1F, portion of the outer perimeter of the top half of 160 at a same level as the top surface of 157b and under 158a) ; and a buffer layer Fig. 1F, 143a, ¶ [0044] teaches a dielectric material that is vertically below the portion of the outer perimeter of the top half of 160 at a same level as the top surface of 157b and under 158a) extends over the ring of the second copper plating surface. Claims 7, 9, and 10 are rejected under 35 U.S.C. 103 as being obvious over MA et al. (US Pub. No. 2016/0322290) in view of ECTON et al. (US Pub. No. 2023/0093522). Regarding claim 7, Ma teaches the electronic device of claim 1, and Ma teaches a buffer layer (Fig. 1F, 158a, ¶ [0041]) . However, Ma does not explicitly teach an adhesion promoter deposited on the top surface of the at least one layer; and a buffer layer deposited on top of the adhesion promoter. However, Ecton is a pertinent art that teaches an adhesion promoter (Fig. 1, 108, ¶ [0023]) deposited on the top surface of the at least one layer (Fig. 1, top surface of 102b, ¶ [0023]) ; and a buffer layer (Fig. 1, 106, ¶ [0023]) deposited on top of the adhesion promoter. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ma’s device to further comprise an adhesion promoter layer in-between their glass layer and their buffer layer according to the teaching of Ecton (Fig. 1) in order to increase the strength of the stacked layers (Ecton ¶ [0023]). Regarding claim 9, Ma teaches the electronic system of claim 8, and Ma teaches a buffer layer (Fig. 1F, 158a + 158b, ¶ [0033]) . However, Ma does not explicitly teach an adhesion promotor coupled with the first exposed surface and the second exposed surface; and a buffer layer coupled with an exposed surface of the adhesion promotor. However, Ecton is a pertinent art that teaches an adhesion promotor (Fig. 1, 108, ¶ [0023]) coupled with the first exposed surface (Fig. 1, top surface of 102b, ¶ [0023]), and the second exposed surface (Ma’s layer 157b is coupled to additional glass layers above and below it. Ecton ¶ [0023] teaches that glass layers can be stacked almost indefinitely using their two layer bonding structure. Therefore, Ma modified to have Ecton’s two layer bonding structure would be on the top and bottom surface of Ma’s layer 157b.) ; and a buffer layer (Fig. 1, 106, ¶ [0023]) coupled with an exposed surface of the adhesion promotor. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ma’s device to further comprise an adhesion promoter layer in-between their glass layer and their buffer layer according to the teaching of Ecton (Fig. 1) in order to increase the strength of the stacked layers (Ecton ¶ [0023]). Regarding claim 10, Ma modified by Ecton teaches the electronic system of claim 9, and Ma teaches that the buffer layer (Fig. 1F, 158a + 158b, ¶ [0033] teaches that 158a and 158b can be an acrylic or epoxy resin, which are dielectric materials) is a dielectric material . Cited Prior Art The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub No. 2018/0294214 by Aoki et al discloses a via structure . 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub No. 2005/0012217 by Mori et al discloses a via structure . Any inquiry concerning this communication or earlier communications from the examiner should be directed to RHYS P. SHEKER whose telephone number is (703)756-1348. The examiner can normally be reached Monday - Friday 7:30 am to 5 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached on 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /R.P.S./ Examiner, Art Unit 2813 /STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813 Application/Control Number: 18/085,291 Page 2 Art Unit: 2813 Application/Control Number: 18/085,291 Page 3 Art Unit: 2813 Application/Control Number: 18/085,291 Page 4 Art Unit: 2813 Application/Control Number: 18/085,291 Page 5 Art Unit: 2813 Application/Control Number: 18/085,291 Page 6 Art Unit: 2813 Application/Control Number: 18/085,291 Page 7 Art Unit: 2813 Application/Control Number: 18/085,291 Page 8 Art Unit: 2813 Application/Control Number: 18/085,291 Page 9 Art Unit: 2813 Application/Control Number: 18/085,291 Page 10 Art Unit: 2813 Application/Control Number: 18/085,291 Page 11 Art Unit: 2813 Application/Control Number: 18/085,291 Page 12 Art Unit: 2813
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