Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1, 12 and 18.
b. Claims 1-20 are pending on the application.
Drawings
2. The drawings were received on 12/20/2022. These drawings are review and accepted by examiner.
Information Disclosure Statement
3. Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 12/20/2022. The information disclosed therein was considered.
Specification
4. Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words. It is important that the abstract not exceed 150 words in length since the space provided for the abstract on the computer tape used by the printer is limited. The form and legal phraseology often used in patent claims, such as "means" and "said," should be avoided. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, "The disclosure concerns," "The disclosure defined by this invention," "The disclosure describes," etc.
The abstract of the disclosure is objected to because it uses the phrase “OF THE DICLOSURE” in page 30, line 1, which is implied. Correction is required. See MPEP § 608.01(b).
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1-2, 4, 12-14, 18 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yu et al (Pub. No.: US 2016/0329085 A1).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding to independent claim 1, Yu et al in Figures 1-6 are directly discloses a system (a memory system 1, Figures. 1-3) comprising:
programmable logic fabric (a system bus 16, Fig. 1);
a memory controller (a memory controller 10, Fig. 1) communicatively coupled to the programmable logic fabric (the system bus 16)(the system bus 16 connected to the memory controller 10, Fig. 1);
a physical layer (a memory physical layer interface circuit 14, Fig. 1) and IO circuit (input clock generation unit 30, input enabling switch 38/output clock output unit 32, 34 and 36, Fig. 3) coupled to the programmable logic fabric (the system bus 16) via the memory controller (the memory controller 10)(the system bus 16 coupled to the memory physical layer interface circuit 14 through the memory controller 10 (Fig. 1) and where is the memory physical layer interface circuit 14 (Fig. 2) includes input clock generation unit 30, input enabling switch 38/output clock output unit 32, 34 and 36, Fig. 3); and
a FIFO (a first FIFO 202, a second FIFO 204 and a third FIFO 206. Fig. 2) to receive read data from a memory device (a memory device 12, Fig. 1) coupled to the physical layer (the memory physical layer interface circuit 14) and IO circuit (input clock generation unit 30, input enabling switch 38/output clock output unit 32, 34 and 36), wherein the FIFO (the first FIFO 202, the second FIFO 204 and the third FIFO 206) is closer to the memory controller (the memory controller 10) than to the physical layer (the memory physical interface circuit 14) and IO circuit (input clock generation unit 30, input enabling switch 38/output clock output unit 32, 34 and 36)(see at least in Figures 1-3, column 1, paragraph 0018 to column 4, paragraph 0055 and the related disclosures).
Regarding dependent claim 2, Yu et al in Figures 1-6 are directly discloses a system (a memory system 1, Figures. 1-3) wherein the physical layer (a memory physical layer interface circuit 14, Fig. 1) and IO circuit (input clock generation unit 30, input enabling switch 38/output clock output unit 32, 34 and 36, Fig. 3) comprises an additional FIFO (a FIFO 204 and a FIFO 206, Fig. 2) used to convert write data from a clock domain of the memory controller (the memory controller 10) to a transmit clock domain of the physical layer and IO circuit (the memory controller 10 coupled to the memory physical layer interface circuit 14 which includes the FIFO 204 and 206).
Regarding dependent claim 4, Yu et al in Figures 1-6 are directly discloses a system (a memory system 1, Figures. 1-3) wherein the FIFO (the FIFO 202, 204 and 206) is to receive source synchronous data from physical layer and IO circuit (input clock generation unit 30, input enabling switch 38/output clock output unit 32, 34 and 36, Fig. 3).
Regarding to independent claim 12, Yu et al in Figures 1-6 are directly discloses a system (a memory system 1, Figures. 1-3) comprising:
core processing circuitry (a system bus 16, Fig. 1);
a memory controller (a memory controller 10, Fig. 1) communicatively coupled to the core processing circuitry (the system bus 16)(the system bus 16 connected to the memory controller 10, Fig. 1);
a physical layer (a memory physical layer interface circuit 14, Fig. 1) and IO circuit (input clock generation unit 30, input enabling switch 38/output clock output unit 32, 34 and 36, Fig. 3) coupled to the programmable logic fabric (the system bus 16) via the memory controller (the memory controller 10)(the system bus 16 coupled to the memory physical layer interface circuit 14 through the memory controller 10 (Fig. 1) and where is the memory physical layer interface circuit 14 (Fig. 2) includes input clock generation unit 30, input enabling switch 38/output clock output unit 32, 34 and 36, Fig. 3);
an IO circuit (input clock generation unit 30, input enabling switch 38/output clock output unit 32, 34 and 36) coupled to the core processing circuitry (a system bus 16, Fig. 1) via the memory controller (the memory controller 10); and
a FIFO (a first FIFO 202, a second FIFO 204 and a third FIFO 206. Fig. 2) to receive read data from a memory device (a memory device 12, Fig. 1) coupled to the IO circuit (input clock generation unit 30, input enabling switch 38/output clock output unit 32, 34 and 36), wherein the FIFO (the first FIFO 202, the second FIFO 204 and the third FIFO 206) is within the memory controller (the memory controller 10) or closer to the memory controller than to the IO circuit (input clock generation unit 30, input enabling switch 38/output clock output unit 32, 34 and 36)(see at least in Figures 1-3, column 1, paragraph 0018 to column 4, paragraph 0055 and the related disclosures).
Regarding dependent claim 13, Yu et al in Figures 1-6 are directly discloses a system (a memory system 1, Figures. 1-3) wherein the core processing circuitry (the system bus 16) comprises a programmable fabric core (the system bus 16 such as the programmable fabric core).
Regarding dependent claim 14, Yu et al in Figures 1-6 are directly discloses a system (a memory system 1, Figures. 1-3) wherein the core processing circuitry (the system bus 16) comprises a processor core (the system bus 16 such as the processor core).
Regarding claims 18 and 20, they encompass the same scope of invention as that of claims 1-2, 4 and 12-14, except they draft the invention in method format instead of apparatus format. Yu et al. teach all the necessary elements to perform the method of these claims. The aspects of the invention contained in claims 18 and 20, are therefore rejected in method format for the same reasons claims 1-2, 4 and 12-14, were rejected in apparatus format, as discussed above in the prior paragraphs of the office action.
Allowable Subject Matter
6. Claims 3, 5-11, 15-17 and 20, insofar as in compliance with the rejection above, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The cited are, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fail to teach or render obvious of the remaining claimed limitations.
With respected to dependent claim 3, the prior art fails to tech or suggest the claimed limitations, namely, there are no FIFOs in the physical layer and IO circuit between an IO of the physical layer and IO circuit and the FIFO for read data along a read path from the IO.
With respected to dependent claims 5-7, the prior art fails to tech or suggest the claimed limitations, namely, wherein the source synchronous data uses a data strobe (DQS) from the memory device, wherein the FIFO is to output data to the memory controller as system synchronous data, wherein the system synchronous data is based on clock that is common to the programmable logic fabric and the memory controller.
With respected to dependent claims 8-11, the prior art fails to tech or suggest the claimed limitations, namely, a main die that comprises the programmable logic fabric, the memory controller, and the FIFO; and a chiplet coupled to the main die and comprising the physical layer and IO circuit, wherein is no FIFO on the chiplet between an IO of the physical layer and IO circuit and the main die for read data from the memory device coupled to the IO, wherein the read data from the memory device coupled to an IO of the physical layer and IO circuit is source synchronous through the chiplet to the FIFO of the main die, the chiplet comprises an additional FIFO for write data received as source synchronous data from the memory controller to be sent to the memory device.
With respected to dependent claims 15-17, the prior art fails to tech or suggest the claimed limitations, namely, a main die that comprises the core processing circuitry, the memory controller, and the FIFO; and a chiplet coupled to the main die and comprising the IO circuit including a IO, wherein is no FIFO on the chiplet between the IO and the main die for data from the memory device coupled to the IO, wherein the main die comprises a more advanced technology node than the chiplet.
With respected to dependent claim 20, the prior art fails to tech or suggest the claimed limitations, namely, wherein driving the data from the memory controller to the IO comprises driving the data from a main die comprising the processing core, the memory controller, and the FIFO across an interconnect to a chiplet comprising the IO circuitry, and receiving the incoming data at the FIFO comprises receiving the data from the IO circuitry across the interconnect, and the incoming source synchronous data is driven using a data strobe (DQS) from the memory device.
Conclusion
Examiner's note: Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chung et al (US. 10,423,386 B1) discloses FIFO circuit for DDR memory system.
Earnest (US. 6,226,338 B1) discloses multiple channel data communication buffer with single transmit and receives memories.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see
http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/Pho M Luu/
Primary Examiner, Art Unit 2824.
571-272-1876.
Miner.Luu@uspto.gov