DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the subject matter of claims 5, 12, and 19, “wherein the gate cut comprises a dielectric liner and a dielectric fill on the dielectric liner,” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4, and 6 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al. (US Patent Application Publication 2023/0097159, hereinafter Lee ‘159).
With respect to claim 1, Lee ‘159 teaches (FIGs. 12A-14B) an integrated circuit as claimed, comprising:
a semiconductor device having a semiconductor region (115 and 125) extending in a first direction between a source region (120) and a drain region (an opposing 120), and a gate structure (142 and 145) extending in a second direction over the semiconductor region ([0020, 0024, 0026, 0064-0075]);
a dielectric layer (147) on a top surface of the gate structure (142 and 145) ([0025, 0064-0075]);
a first conductive contact (180) on the source region (120) and a second conductive contact (an opposing 180) on the drain region (an opposing 120) ([0029, 0064-0075]); and
a gate cut (160) extending in a third direction through an entire thickness of the gate structure (142 and 145), wherein the gate cut comprises a dielectric material and wherein a top surface of the gate cut is substantially coplanar with a top surface of the dielectric layer (147) and top surfaces of the first (180) and second (an opposing 180) conductive contacts ([0030, 0064-0075]).
With respect to claim 2, Lee ‘159 teaches wherein the dielectric material comprises silicon and nitrogen or comprises silicon and oxygen ([0030]).
With respect to claim 4, Lee ‘159 teaches wherein the dielectric layer (147) comprises silicon and nitrogen ([0025]).
With respect to claim 6, Lee ‘159 teaches wherein the semiconductor region (115 and 125) comprises a plurality of semiconductor nanoribbons (125) ([0064-0075]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘159 as applied to claim 1 above, and further in view of Huang et al. (US Patent Application Publication 2021/0407999, hereinafter Huang ‘999).
With respect to claim 3, Lee ‘159 teaches the device as described in claim 1 above with the exception of the additional limitation wherein the gate cut contacts at least a portion of the source region and/or the drain region.
However, Huang ‘999 teaches (FIG. 2) a gate cut (201) contacting at least a portion of a source region and/or a drain region (226) ([0037-0038]) in an arrangement that combats the demands of spacing between features ([0028]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the gate cut of Lee ‘159 contacting at least a portion of the source region and/or the drain region as taught by Huang ‘999 to combat the demands of spacing between features.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘159 as applied to claim 1 above, and further in view of Lim et al. (US Patent Application Publication 2020/0135848, hereinafter Lim ‘848).
With respect to claim 5, Lee ‘159 teaches the device as described in claim 1 above with the exception of the additional limitation wherein the gate cut comprises a dielectric liner and a dielectric fill on the dielectric liner, wherein the dielectric liner has a higher dielectric constant than the dielectric fill.
However, Lim ‘848 teaches (FIG. 2) a gate cut (GI and 80) comprising a dielectric liner (GI) and a dielectric fill (80) on the dielectric liner, wherein the dielectric liner (GI when selected from a high-k dielectric material; [0032]) has a higher dielectric constant than the dielectric fill (80 when selected from a low-k dielectric material; [0034]) as art-recognized materials suitable for the intended use as a gate cut in an arrangement that prevents bridging defects, thus increasing the yield or reliability of the semiconductor device ([0110]). Further, the selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination. Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) and In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960). See MPEP 2144.07.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the gate cut of Lee ‘159 comprising a dielectric liner and a dielectric fill on the dielectric liner, wherein the dielectric liner has a higher dielectric constant than the dielectric fill as taught by Lim ‘848 as art-recognized materials suitable for the intended use as a gate cut in an arrangement that prevents bridging defects, thus increasing the yield or reliability of the semiconductor device.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘159 as applied to claim 1 above, and further in view of Su et al. (US Patent Application Publication 2022/0262915, hereinafter Su ‘915).
With respect to claim 7, Lee ‘159 teaches the device as described in claim 1 above with the exception of the additional limitation wherein the gate structure includes a gate dielectric around the semiconductor region and the gate dielectric is not present on any sidewall of the gate cut.
However, Su ‘915 teaches (FIG. 24A) a gate structure (250) including a gate dielectric (254) around a semiconductor region (208) and the gate dielectric is not present on any sidewall of a gate cut (244-1) ([0018-0019, 0035]) to enlarge lateral distance between adjacent gate structures and thus reduce parasitic capacitance ([0031]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the gate structure of Lee ‘159 including a gate dielectric around the semiconductor region and the gate dielectric is not present on any sidewall of the gate cut as taught by Su ‘915 to enlarge lateral distance between adjacent gate structures and thus reduce parasitic capacitance.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘159 in view of Mehandru et al. (US Patent Application Publication 2020/0006559, hereinafter Mehandru ‘559).
With respect to claim 8, Lee ‘159 teaches the integrated circuit of claim 1 as claimed (see the 35 U.S.C. 102(a)(2) rejection of claim 1 above).
Thus, Lee ‘159 is shown to teach all the features of the claim with the exception of wherein a printed circuit board comprises the integrated circuit of claim 1.
However, Mehandru ‘559 teaches (FIG. 14) a gate-all-around (GAA) transistor device formed on a printed circuit board (PCB) (1002) that serves as a motherboard for a computing system (1000) ([0090]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the integrated circuit of claim 1 of Lee ‘159 on a printed circuit board as taught by Mehandru ‘559 to serve as a motherboard for a computing system.
Claims 9-11, 13, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘159 in view of Huang ‘999.
With respect to claim 9, Lee ‘159 teaches (FIGs. 12A-14B) an electronic device substantially as claimed, comprising:
at least one of one or more dies comprising
a semiconductor device having a semiconductor region (115 and 125) extending in a first direction between a source region (120) and a drain region (an opposing 120), and a gate structure (142 and 145) extending in a second direction over the semiconductor region ([0020, 0024, 0026, 0064-0075]);
a dielectric layer (147) on a top surface of the gate structure (142 and 145) ([0025, 0064-0075]);
a first conductive contact (180) on the source region (120) and a second conductive contact (an opposing 180) on the drain region (an opposing 120) ([0029, 0064-0075]); and
a gate cut (160) extending in a third direction through an entire thickness of the gate structure (142 and 145), wherein the gate cut comprises a dielectric material and wherein a top surface of the gate cut is substantially coplanar with a top surface of the dielectric layer (147) and a top surface of the first (180) and/or second (an opposing 180) conductive contact ([0030, 0064-0075]).
Thus, Lee ‘159 is shown to teach all the features of the claim with the exception of a chip package comprising the one or more dies.
However, Huang ‘999 teaches (FIG. 9) a chip package (906) comprising one or more dies of stacked transistors (200) ([0085]) to form an integrated circuit structure ([0036]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the one of more dies of Lee ‘159 as a chip package as taught by Huang ‘999 to form an integrated circuit structure.
With respect to claims 10 and 17, Lee ‘159 teaches wherein the dielectric material comprises silicon and nitrogen or comprises silicon and oxygen ([0030]).
With respect to claim 11, Lee ‘159 and Huang ‘999 teach the device as described in claim 9 above, but primary reference Lee ‘159 does not explicitly teach the additional limitation wherein the gate cut contacts at least a portion of the source region and/or the drain region.
However, Huang ‘999 teaches (FIG. 2) a gate cut (201) contacting at least a portion of a source region and/or a drain region (226) ([0037-0038]) in an arrangement that combats the demands of spacing between features ([0028]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the gate cut of Lee ‘159 and Huang ‘999 contacting at least a portion of the source region and/or the drain region as taught by Huang ‘999 to combat the demands of spacing between features.
With respect to claim 13, Lee ‘159 teaches wherein the gate structure (142 and 145) includes a gate dielectric (142) around the semiconductor region (115 and 125) ([0024, 0064-0075]).
With respect to claim 16, Lee ‘159 teaches (FIGs. 1-3B) an integrated circuit substantially as claimed, comprising:
a semiconductor region (115 and 125) extending in a first direction between a first source or drain region (120) and a second source or drain region (an opposing 120) ([0020, 0026, 0064-0075]);
a gate structure (142 and 145) extending in a second direction over the semiconductor region (115 and 125) ([0024, 0064-0075]);
a dielectric layer (147) on a top surface of the gate structure (142 and 145) ([0025, 0064-0075]);
a first conductive contact (180) on the first source or drain region (120) and a second conductive contact (an opposing 180) on the second source or drain region (an opposing 120) ([0029, 0064-0075]); and
a gate cut (160) extending in a third direction through an entire thickness of the gate structure (142 and 145) and extending in the first direction, the gate cut comprising a dielectric material and having a top surface that is substantially coplanar with a top surface of the dielectric layer (147) and a top surface of the first conductive contact (180) ([0030, 0064-0075]).
Thus, Lee ‘159 is shown to teach all the features of the claim with the exception of the gate cut contacting at least a portion of the first source or drain region and at least a portion of the first conductive contact.
However, Huang ‘999 teaches (FIG. 2) a gate cut (201) contacting at least a portion of a first source or drain region (226) and at least a portion of a first conductive contact (206) ([0037-0038]) in an arrangement that combats the demands of spacing between features ([0028]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the gate cut of Lee ‘159 contacting at least a portion of the first source or drain region and at least a portion of the first conductive contact as taught by Huang ‘999 to combat the demands of spacing between features.
With respect to claim 18, Lee ‘159 teaches wherein the dielectric layer (147) comprises silicon and nitrogen ([0025]).
Claims 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘159 and Huang ‘999 as applied to claims 9 and 16 above, and further in view of Lim ‘848.
With respect to claim 12 and 19, Lee ‘159 and Huang ‘999 teach the device as described in claims 9 and 16 above with the exception of the additional limitations wherein the gate cut comprises a dielectric liner and a dielectric fill on the dielectric liner, wherein the dielectric liner has a higher dielectric constant than the dielectric fill.
However, Lim ‘848 teaches (FIG. 2) a gate cut (GI and 80) comprising a dielectric liner (GI) and a dielectric fill (80) on the dielectric liner, wherein the dielectric liner (GI when selected from a high-k dielectric material; [0032]) has a higher dielectric constant than the dielectric fill (80 when selected from a low-k dielectric material; [0034]) as art-recognized materials suitable for the intended use as a gate cut in an arrangement that prevents bridging defects, thus increasing the yield or reliability of the semiconductor device ([0110]). Further, the selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination. Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) and In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960). See MPEP 2144.07.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the gate cut of Lee ‘159 comprising a dielectric liner and a dielectric fill on the dielectric liner, wherein the dielectric liner has a higher dielectric constant than the dielectric fill as taught by Lim ‘848 as art-recognized materials suitable for the intended use as a gate cut in an arrangement that prevents bridging defects, thus increasing the yield or reliability of the semiconductor device.
Claims 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘159 and Huang ‘999 as applied to claims 13 and 16 above, and further in view of Su ‘915.
With respect to claims 14 and 20, Lee ‘159 and Huang ‘999 teach the device as described in claims 13 and 16 above with the exception of the additional limitations wherein the gate dielectric is not present on any sidewall of the gate cut; and wherein the gate structure includes a gate dielectric around the semiconductor region and the gate dielectric is not present on any sidewall of the gate cut.
However, Su ‘915 teaches (FIG. 24A) a gate structure (250) including a gate dielectric (254) around a semiconductor region (208) and the gate dielectric is not present on any sidewall of a gate cut (244-1) ([0018-0019, 0035]) to enlarge lateral distance between adjacent gate structures and thus reduce parasitic capacitance ([0031]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the gate dielectric and the gate structure of Lee ‘159 and Huang ‘999 not present on any sidewall of the gate cut, and including a gate dielectric around the semiconductor region and the gate dielectric is not present on any sidewall of the gate cut respectively as taught by Su ‘915 to enlarge lateral distance between adjacent gate structures and thus reduce parasitic capacitance.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘159 and Huang ‘999 as applied to claim 9 above, and further in view of Mehandru ‘559.
With respect to claim 15, Lee ‘159 and Huang ‘999 teach the device as described in claim 9 above with the exception of the additional limitation further comprising a printed circuit board, wherein the chip package is coupled to the printed circuit board.
However, Mehandru ‘559 teaches (FIG. 14) a gate-all-around (GAA) transistor device chip package formed on a printed circuit board (PCB) (1002) that serves as a motherboard for a computing system (1000) ([0090]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the electronic device of Lee ‘159 and Huang ‘999 further comprising a printed circuit board, wherein the chip package is coupled to the printed circuit board as taught by Mehandru ‘559 to serve as a motherboard for a computing system.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher M. Roland whose telephone number is (571)270-1271. The examiner can normally be reached Monday-Friday, 10:00AM-7:00PM Eastern.
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/C.M.R./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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