DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Amendment filed 13 July 2026 is acknowledged. Claims 3 and 11 have been canceled. Claims 1, 4, 9, 16, and 18 have been amended. Claims 21 and 22 have been added. Claims 1, 2, 4-10, and 12-22 are pending.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the subject matter of claims 5, 9, 12, and 19, “wherein the gate cut comprises a dielectric liner and a dielectric fill on the dielectric liner,” and, “wherein the gate cut directly contacts at least a portion of the source region, at least a portion of the drain region, at least a portion of the first conductive contact, and at least a portion of the second conductive contact,” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: the subject matter of claim 9, “wherein the gate cut directly contacts at least a portion of the source region, at least a portion of the drain region, at least a portion of the first conductive contact, and at least a portion of the second conductive contact,” must find support in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 9, 10, 12-15, and 22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 9 recites the limitation, “wherein the gate cut directly contacts at least a portion of the source region, at least a portion of the drain region, at least a portion of the first conductive contact, and at least a portion of the second conductive contact.” This limitation is not supported by the disclosure as originally filed. As best understood by Examiner, the gate cut (128) directly contacts only one of a source or drain region (110 and 130) and only one of a first and second conductive contact (116 and 132), not both.
Claims 10, 12-15, and 22 are rejected for merely containing the flaws of the parent claim.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9, 10, 12-15, and 22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation, “wherein the gate cut directly contacts at least a portion of the source region, at least a portion of the drain region, at least a portion of the first conductive contact, and at least a portion of the second conductive contact.” It is unclear how the gate cut directly contacts both of the source and drain regions, and both of the first and second conductive contacts. As best understood by Examiner, the gate cut (128) directly contacts only one of a source or drain region (110 and 130) and only one of a first and second conductive contact (116 and 132), not both.
Claims 10, 12-15, and 22 are rejected for merely containing the flaws of the parent claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 6, 7, 16-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US Patent Application Publication 2023/0097159, hereinafter Lee ‘159) of record in view of Xie et al. (US Patent Application Publication 2024/0105799, hereinafter Xie ‘799).
With respect to claim 1, Lee ‘159 teaches (FIGs. 12A-14B) an integrated circuit substantially as claimed, comprising:
a semiconductor device having a semiconductor region (115 and 125) extending in a first direction between a first source or drain region (120) and a second source or drain region (an opposing 120), and a gate structure (142 and 145) extending in a second direction over the semiconductor region ([0020, 0024, 0026, 0064-0075]);
a first conductive contact (180) on the first source or drain region (120) and a second conductive contact (an opposing 180) on the second source or drain region (an opposing 120) ([0029, 0064-0075]); and
a gate cut (160) extending in a third direction through an entire thickness of the gate structure (142 and 145), wherein the gate cut comprises a dielectric material and wherein a top surface of the gate cut is substantially coplanar with top surfaces of the first (180) and second (an opposing 180) conductive contacts ([0030, 0064-0075]).
Thus, Lee ‘159 is shown to teach all the features of the claim with the exception of wherein the gate cut directly contacts at least a portion of the first source or drain region and at least a portion of the first conductive contact and does not directly contact any portion of the semiconductor region.
However, Xie ‘799 teaches (FIGs. 14A-14C) a gate cut (1412) directly contacting at least a portion of a first source or drain region (1302 and 1304) and at least a portion of a first conductive contact (1416) and does not directly contact any portion of a semiconductor region (208) ([0038, 0060, 0064]) to isolate the gates of different field-effect transistors ([0070]) in a process flow that enables the formation of very uniform, high-quality/low-defect source/drain region epitaxy ([0030]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the gate cut of Lee ‘159 directly contacting at least a portion of the first source or drain region and at least a portion of the first conductive contact and does not directly contact any portion of the semiconductor region as taught by Xie ‘799 to isolate the gates of different field-effect transistors in a process flow that enables the formation of very uniform, high-quality/low-defect source/drain region epitaxy.
With respect to claim 2, Lee ‘159 teaches wherein the dielectric material comprises silicon and nitrogen or comprises silicon and oxygen ([0030]).
With respect to claims 4 and 18, Lee ‘159 teaches further comprising a dielectric layer (147) on a top surface of the gate structure (142 and 145), wherein the top surface of the gate cut (160) is substantially coplanar with a top surface of the dielectric layer ([0025]).
With respect to claim 6, Lee ‘159 teaches wherein the semiconductor region (115 and 125) comprises a plurality of semiconductor nanoribbons (125) ([0064-0075]).
With respect to claims 7 and 20, Lee ‘159 and Xie ‘799 teach the device as described in claims 1 and 16 above, but primary reference Lee ‘159 does not explicitly teach the additional limitation wherein the gate structure includes a gate dielectric around the semiconductor region and the gate dielectric is not present on any sidewall of the gate cut.
However, Xie ‘799 teaches (FIGs. 14A-14C) a gate structure (1402 and 1406) including a gate dielectric (1406) around a semiconductor region (208) and the gate dielectric is not present on any sidewall of a gate cut (1412) so that a gate electrode (1402) may effectively control the conductivity of said semiconductor region ([0066]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the gate structure of Lee ‘159 and Xie ‘799 including a gate dielectric around the semiconductor region and the gate dielectric is not present on any sidewall of the gate cut as taught by Xie ‘799 so that a gate electrode may effectively control the conductivity of said semiconductor region.
With respect to claim 16, Lee ‘159 teaches (FIGs. 1-3B) an integrated circuit substantially as claimed, comprising:
a semiconductor region (115 and 125) extending in a first direction between a first source or drain region (120) and a second source or drain region (an opposing 120) ([0020, 0026, 0064-0075]);
a gate structure (142 and 145) extending in a second direction over the semiconductor region (115 and 125) ([0024, 0064-0075]);
a first conductive contact (180) on the first source or drain region (120) and a second conductive contact (an opposing 180) on the second source or drain region (an opposing 120) ([0029, 0064-0075]); and
a gate cut (160) extending in a third direction through an entire thickness of the gate structure (142 and 145) and extending in the first direction, the gate cut comprising a dielectric material and having a top surface that is substantially coplanar with a top surface of the first conductive contact (180) ([0030, 0064-0075]).
Thus, Lee ‘159 is shown to teach all the features of the claim with the exception of:
the gate cut contacting at least a portion of the first source or drain region and at least a portion of the first conductive contact;
wherein the gate cut does not directly contact any portion of the semiconductor region.
However, Xie ‘799 teaches (FIGs. 14A-14C) a gate cut (1412) directly contacting at least a portion of a first source or drain region (1302 and 1304) and at least a portion of a first conductive contact (1416) and does not directly contact any portion of a semiconductor region (208) ([0038, 0060, 0064]) to isolate the gates of different field-effect transistors ([0070]) in a process flow that enables the formation of very uniform, high-quality/low-defect source/drain region epitaxy ([0030]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the gate cut of Lee ‘159 contacting at least a portion of the first source or drain region and at least a portion of the first conductive contact; wherein the gate cut does not directly contact any portion of the semiconductor region as taught by Xie ‘799 to isolate the gates of different field-effect transistors in a process flow that enables the formation of very uniform, high-quality/low-defect source/drain region epitaxy.
With respect to claim 17, Lee ‘159 teaches wherein the dielectric material comprises silicon and nitrogen or comprises silicon and oxygen ([0030]).
Claims 5 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘159 and Xie ‘799 as applied to claims 1 and 16 above, and further in view of Lim et al. (US Patent Application Publication 2020/0135848, hereinafter Lim ‘848) of record.
With respect to claims 5 and 19, Lee ‘159 and Xie ‘799 teach the device as described in claims 1 and 16 above with the exception of the additional limitation wherein the gate cut comprises a dielectric liner and a dielectric fill on the dielectric liner, wherein the dielectric liner has a higher dielectric constant than the dielectric fill.
However, Lim ‘848 teaches (FIG. 2) a gate cut (GI and 80) comprising a dielectric liner (GI) and a dielectric fill (80) on the dielectric liner, wherein the dielectric liner (GI when selected from a high-k dielectric material; [0032]) has a higher dielectric constant than the dielectric fill (80 when selected from a low-k dielectric material; [0034]) as art-recognized materials suitable for the intended use as a gate cut in an arrangement that prevents bridging defects, thus increasing the yield or reliability of the semiconductor device ([0110]). Further, the selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination. Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) and In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960). See MPEP 2144.07.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the gate cut of Lee ‘159 and Xie ‘799 comprising a dielectric liner and a dielectric fill on the dielectric liner, wherein the dielectric liner has a higher dielectric constant than the dielectric fill as taught by Lim ‘848 as art-recognized materials suitable for the intended use as a gate cut in an arrangement that prevents bridging defects, thus increasing the yield or reliability of the semiconductor device.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘159 in view of Xie ‘799 and Mehandru et al. (US Patent Application Publication 2020/0006559, hereinafter Mehandru ‘559) of record.
With respect to claim 8, Lee ‘159 and Xie ‘799 teach the integrated circuit of claim 1 as claimed (see the 35 U.S.C. 103 rejection of claim 1 above).
Thus, Lee ‘159 is shown to teach all the features of the claim with the exception of wherein a printed circuit board comprises the integrated circuit of claim 1.
However, Mehandru ‘559 teaches (FIG. 14) a gate-all-around (GAA) transistor device formed on a printed circuit board (PCB) (1002) that serves as a motherboard for a computing system (1000) ([0090]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the integrated circuit of claim 1 of Lee ‘159 and Xie ‘799 on a printed circuit board as taught by Mehandru ‘559 to serve as a motherboard for a computing system.
Claims 9, 10, 13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘159 in view of Huang ‘999 and Xie ‘799.
With respect to claim 9, Lee ‘159 teaches (FIGs. 12A-14B) an electronic device substantially as claimed, comprising:
at least one of one or more dies comprising
a semiconductor device having a semiconductor region (115 and 125) extending in a first direction between a source region (120) and a drain region (an opposing 120), and a gate structure (142 and 145) extending in a second direction over the semiconductor region ([0020, 0024, 0026, 0064-0075]);
a dielectric layer (147) on a top surface of the gate structure (142 and 145) ([0025, 0064-0075]);
a first conductive contact (180) on the source region (120) and a second conductive contact (an opposing 180) on the drain region (an opposing 120) ([0029, 0064-0075]); and
a gate cut (160) extending in a third direction through an entire thickness of the gate structure (142 and 145), wherein the gate cut comprises a dielectric material and wherein a top surface of the gate cut is substantially coplanar with a top surface of the dielectric layer (147) and a top surface of the first (180) and/or second (an opposing 180) conductive contact ([0030, 0064-0075]).
Thus, Lee ‘159 is shown to teach all the features of the claim with the exception of:
a chip package comprising the one or more dies;
wherein the gate cut directly contacts at least a portion of the source region, at least a portion of the drain region, at least a portion of the first conductive contact, and at least a portion of the second conductive contact and does not directly contact any portion of the semiconductor region.
However, Huang ‘999 teaches (FIG. 9) a chip package (906) comprising one or more dies of stacked transistors (200) ([0085]) to form an integrated circuit structure ([0036]).
Further, Xie ‘799 teaches (FIGs. 14A-14C) a gate cut (1412) directly contacting at least a portion of a source region (1302) and drain region (1304) and at least a portion of a conductive contact (1416) and does not directly contact any portion of a semiconductor region (208) ([0038, 0060, 0064]) to isolate the gates of different field-effect transistors ([0070]) in a process flow that enables the formation of very uniform, high-quality/low-defect source/drain region epitaxy ([0030]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the one of more dies of Lee ‘159 as a chip package as taught by Huang ‘999 to form an integrated circuit structure; and to have formed the gate cut of Lee ‘159 directly contacting at least a portion of the source region, at least a portion of the drain region, at least a portion of the first conductive contact, and at least a portion of the second conductive contact and does not directly contact any portion of the semiconductor region as taught by Xie ‘799 to isolate the gates of different field-effect transistors in a process flow that enables the formation of very uniform, high-quality/low-defect source/drain region epitaxy.
With respect to claim 10, Lee ‘159 teaches wherein the dielectric material comprises silicon and nitrogen or comprises silicon and oxygen ([0030]).
With respect to claim 13, Lee ‘159 teaches wherein the gate structure (142 and 145) includes a gate dielectric (142) around the semiconductor region (115 and 125) ([0024, 0064-0075]).
With respect to claim 14, Lee ‘159, Huang ‘999, and Xie ‘799 teach the device as described in claim 13 above, but primary reference Lee ‘159 does not explicitly teach the additional limitation wherein the gate dielectric is not present on any sidewall of the gate cut.
However, Xie ‘799 teaches (FIGs. 14A-14C) a gate structure (1402 and 1406) including a gate dielectric (1406) around a semiconductor region (208) and the gate dielectric is not present on any sidewall of a gate cut (1412) so that a gate electrode (1402) may effectively control the conductivity of said semiconductor region ([0066]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the gate dielectric of Lee ‘159, Huang ‘999, and Xie ‘799 not present on any sidewall of the gate cut as taught by Xie ‘799 so that a gate electrode may effectively control the conductivity of said semiconductor region.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘159, Huang ‘999, and Xie ‘799 as applied to claim 9 above, and further in view of Lim ‘848.
With respect to claim 12, Lee ‘159, Huang ‘999, and Xie ‘799 teach the device as described in claim 9 above with the exception of the additional limitations wherein the gate cut comprises a dielectric liner and a dielectric fill on the dielectric liner, wherein the dielectric liner has a higher dielectric constant than the dielectric fill.
However, Lim ‘848 teaches (FIG. 2) a gate cut (GI and 80) comprising a dielectric liner (GI) and a dielectric fill (80) on the dielectric liner, wherein the dielectric liner (GI when selected from a high-k dielectric material; [0032]) has a higher dielectric constant than the dielectric fill (80 when selected from a low-k dielectric material; [0034]) as art-recognized materials suitable for the intended use as a gate cut in an arrangement that prevents bridging defects, thus increasing the yield or reliability of the semiconductor device ([0110]). Further, the selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination. Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) and In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960). See MPEP 2144.07.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the gate cut of Lee ‘159, Huang ‘999, and Xie ‘799 comprising a dielectric liner and a dielectric fill on the dielectric liner, wherein the dielectric liner has a higher dielectric constant than the dielectric fill as taught by Lim ‘848 as art-recognized materials suitable for the intended use as a gate cut in an arrangement that prevents bridging defects, thus increasing the yield or reliability of the semiconductor device.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘159, Huang ‘999, and Xie ‘799 as applied to claim 9 above, and further in view of Mehandru ‘559.
With respect to claim 15, Lee ‘159, Huang ‘999, and Xie ‘799 teach the device as described in claim 9 above with the exception of the additional limitation further comprising a printed circuit board, wherein the chip package is coupled to the printed circuit board.
However, Mehandru ‘559 teaches (FIG. 14) a gate-all-around (GAA) transistor device chip package formed on a printed circuit board (PCB) (1002) that serves as a motherboard for a computing system (1000) ([0090]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the electronic device of Lee ‘159, Huang ‘999, and Xie ‘799 further comprising a printed circuit board, wherein the chip package is coupled to the printed circuit board as taught by Mehandru ‘559 to serve as a motherboard for a computing system.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘159 and Xie ‘799 as applied to claim 4 above, and further in view of Su et al. (US Patent Application Publication 2022/0262915, hereinafter Su ‘915) of record.
With respect to claim 21, Lee ‘159 and Xie ‘799 teach the device as described in claim 4 above with the exception of the additional limitation wherein the dielectric layer has a thickness between about 10 nm and about 20 nm.
However, Su ‘915 teaches a dielectric layer (226) having a thickness between about 10 nm and about 20 nm, and an adjacent S/D contact (260) having similar proportions as art-recognized dimensions for such features within a gate-all-around transistor ([0024, 0031]). In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); and In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). See MPEP 2144.05 I. One of ordinary skill in the art, based on the dimensions provided in Su ‘915, could form the dielectric layer of Lee ‘159 and Xie ‘799 to a thickness between about 10 nm and about 20 nm with a reasonable expectation of success.
Further, such a modification would have involved a mere change in size or proportion of a component. A change in size or proportion is generally recognized as being with the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04 IV. A.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the dielectric layer of Lee ‘159 and Xie ‘799 having a thickness between about 10 nm and about 20 nm as taught by Su ‘915 using art-recognized dimensions for such features within a gate-all-around transistor and because such a modification would have involved a mere change in size or proportion of a component.
Further, the specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom. Where patentability is said to be based upon a particular chosen distance or upon another variable recited in the claim, Applicant must show that the chosen variable is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘159, Huang ‘999, and Xie ‘799 as applied to claim 9 above, and further in view of Su ‘915.
With respect to claim 21, Lee ‘159, Huang ‘999, and Xie ‘799 teach the device as described in claim 9 above with the exception of the additional limitation wherein the dielectric layer has a thickness between about 10 nm and about 20 nm.
However, Su ‘915 teaches a dielectric layer (226) having a thickness between about 10 nm and about 20 nm, and an adjacent S/D contact (260) having similar proportions as art-recognized dimensions for such features within a gate-all-around transistor ([0024, 0031]). In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); and In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). See MPEP 2144.05 I. One of ordinary skill in the art, based on the dimensions provided in Su ‘915, could form the dielectric layer of Lee ‘159, Huang ‘999, and Xie ‘799 to a thickness between about 10 nm and about 20 nm with a reasonable expectation of success.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the dielectric layer of Lee ‘159, Huang ‘999, and Xie ‘799 having a thickness between about 10 nm and about 20 nm as taught by Su ‘915 using art-recognized dimensions for such features within a gate-all-around transistor and because such a modification would have involved a mere change in size or proportion of a component.
Further, the specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom. Where patentability is said to be based upon a particular chosen distance or upon another variable recited in the claim, Applicant must show that the chosen variable is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Response to Arguments
Applicant's arguments filed 13 July 2026 with respect to the objection to the drawings have been fully considered but they are not persuasive.
Applicant argues (remarks, p. 6) that a skilled artisan would readily understand how a gate cut could include a dielectric liner and a dielectric fill as it is described in the instant application at, for example, [0066]. As such, illustrations of the claimed dielectric liner and dielectric fill are not required, “for the understanding of the subject matter sought to be patented.” Examiner respectfully disagrees.
The drawings must show every feature of the invention specified in the claims. 37 C.F.R. 1.83(a). Any structural detail that is of sufficient importance to be described should be shown in the drawing. Ex parte Good, 1911 C.D. 43, 164 OG 739 (Comm’r Pat. 1911). The features of claims 5, 12, and 19, “wherein the gate cut comprises a dielectric liner and a dielectric fill on the dielectric liner,” must be shown in the drawings.
Applicant’s arguments with respect to amended claim(s) 1, 9, and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Kane et al. (US Patent Application Publication 2024/0194696) teaches GAA FETs comprising gate cuts.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher M. Roland whose telephone number is (571)270-1271. The examiner can normally be reached Monday-Friday, 10:00AM-7:00PM Eastern.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at (571)270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.M.R./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
Prosecution Insights