Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/22/2022 is being
considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 5-6, 8-10 and 14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by He et al. (US 20220068329 A1) hereinafter He.
Regarding claim 1, He teaches An integrated circuit comprising: a buffer circuit; a memory circuit; (See Fig 1, paragraph [0013], illustrates a semiconductor device 100 includes a low latency register or buffer 122 and a memory array 145)
and a controller circuit to determine whether the memory circuit stores information, (See Fig 1, paragraph [0021], illustrates control circuit 121 may make determination if the address provided by read command is a match or in other words, data is stored in that address of memory cell array 145)
the controller circuit to determine whether to transmit the information stored in the memory circuit to the buffer circuit based on credits that indicate an amount of storage space available in the buffer circuit, and (See Fig 1, paragraph [0011], illustrates control circuit 121 may determine whether a slot is available based on a register full indication provided from the low latency register circuit 122. In other words, control circuit may determine availability of space based on credit or register full indication)
the controller circuit to transmit the information to the buffer circuit if the credits indicate that sufficient storage space is available in the buffer circuit to store the information. (See Fig 1, paragraph [0022], illustrates the low latency register or buffer 122 may store the address and write data received from the I0 circuit 170 if indication is there that there is available slot in the buffer)
Regarding claim 3, He teaches The integrated circuit of claim 1, wherein the memory circuit is one of a set of memory circuits, and wherein the controller circuit is one of a set of controller circuits to determine whether to transmit information stored in the memory circuits to the buffer circuit based on the credits that indicate the amount of storage space available in the buffer circuit and allocated for storing the information stored in the memory circuits. (See Fig 1, paragraph [0011] and [0022], illustrates control circuit 121 may determine whether a slot is available based on a register full indication provided from the low latency register circuit 122. In other words, control circuit may determine availability of space based on credit or register full indication either to send to buffer or memory array)
Regarding claim 5, He teaches The integrated circuit of claim 1, the buffer circuit to store the information received from the controller circuit. (See Fig 1, paragraph [0022], illustrates the low latency register 122 may store the address and write data received from the I0 circuit 170 in an available slot)
Regarding claim 6, He teaches The integrated circuit of claim 1, the memory circuit to store the information in response to a write request from a requesting circuit in the integrated circuit. (See Fig 1, paragraph [0022], illustrates if no slots are available, the control circuit 121 may cause the write data to be written to the memory cell array 145 based on the address)
Regarding claim 8, He teaches The integrated circuit of claim 1, wherein the information stored in the memory circuit is one of a write address or write data for a write operation. (See Fig 1, paragraph [0022], illustrates if no slots are available in register 122, the control circuit 121 may cause the write data to be written to the memory cell array 145 based on the address)
Regarding claim 9, He teaches A method comprising: determining whether a memory circuit stores information; (See Fig 1, paragraph [0013], illustrates a semiconductor device 100 includes a low latency register or buffer 122 and a memory array 145)
determining whether to transmit the information stored in the memory circuit to a buffer circuit using a controller circuit based on credits that indicate an amount of available storage in the buffer circuit; (See Fig 1, paragraph [0011], illustrates control circuit 121 may determine whether a slot is available based on a register full indication provided from the low latency register circuit 122. In other words, control circuit may determine availability of space based on credit or register full indication)
transmitting the information from the controller circuit to the buffer circuit if the credits indicate that enough storage is available in the buffer circuit to store the information; and storing the information in the buffer circuit. (See Fig 1, paragraph [0022], illustrates the low latency register or buffer 122 may store the address and write data received from the I0 circuit 170 if indication is there that there is available slot in the buffer)
Regarding claim 10, He teaches The method of claim 9 further comprising: storing the information in the memory circuit in response to a write request from a requesting circuit. (See Fig 1, paragraph [0022], illustrates if no slots are available, the control circuit 121 may cause the write data to be written to the memory cell array 145 based on the address)
Regarding claim 14, He teaches The method of claim 9 further comprising: determining whether to transmit information stored in memory circuits to the buffer circuit based on the credits that indicate the amount of available storage in the buffer circuit allocated for storing the information stored in the memory circuits using controller circuits that comprise the controller circuit, wherein the memory circuits comprise the memory circuit. (See Fig 1, paragraph [0011] and [0022], illustrates control circuit 121 may determine whether a slot is available based on a register full indication provided from the low latency register circuit 122. In other words, control circuit may determine availability of space based on credit or register full indication either to send to buffer or memory array)
Claim(s) 16 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Baeckler et al. (US 9330740 B1) hereinafter Baeckler.
Regarding claim 16, Baeckler teaches An integrated circuit comprising a first configurable memory block circuit, wherein the first configurable memory block circuit comprises: a write address generator circuit to generate a write pointer for a write operation to a first memory circuit; (See Fig 1, col 6 line 42-43, illustrates Write pointer generator circuit 102 also generates write pointer signals WPTRWC that indicate a write pointer)
a read address generator circuit to generate a read pointer for a read operation to the first memory circuit; (See Fig 1, col 6 line 42-43, illustrates Read pointer generator circuit 103 also generates read pointer signals RPTRRC that indicate a read pointer)
a write control logic circuit to generate a write status control signal that indicates that the first memory circuit is full when a separation between the read pointer and the write pointer reaches a predefined full value; and a read control logic circuit to generate a read status control signal that indicates that the first memory circuit is empty when the separation between the read pointer and the write pointer reaches zero. (See Fig 1, col 8 line 4-13, illustrates the write pointer signals WPTRWC include one or more additional bits relative to the write address signals WADDR and the read pointer signals RPTRRC include one or more additional bits relative to the read address signals RADDR where The additional bits in the read and write pointer signals can be used to differentiate when storage circuit 101 is full of words of data and when storage circuit 101 is empty)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 4, 7, 11-13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over He in view of Dropps et al. (US 9094294 B1) hereinafter Dropps.
Regarding claim 2, He teaches techniques of accessing memory circuits in claim 1. However, He does not explicitly teach The integrated circuit of claim 1, the buffer circuit to change a number of the credits in response to changes in the amount of storage space available in the buffer circuit
On the other hand, Dropps which also relates to techniques of accessing memory circuits teaches The integrated circuit of claim 1, the buffer circuit to change a number of the credits in response to changes in the amount of storage space available in the buffer circuit. (See Fig 1, col 7 line 62-66, illustrates concept of credit is used based on based on the space that is available at PBUF 204)
Both He and Dropps relate to techniques of accessing memory circuits (see
He, abstract, and see Dropps, abstract, regarding bad block management for memory
devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine He with Dropps by incorporating
techniques of accessing memory circuits using amount of buffer spaces, as taught by Dropps; to illustrate concept of credit is used based on based on the space that is available at PBUF 204. The combined system of He – Dropps allows same out-of-credit logic to be used to monitor out-of-credit conditions as mentioned in col 1 line 63. Therefore, the combination of He - Dropps improves situations where the receiving port may overflow with received frames. See Dropps, col 3 line 66-67.
Regarding claim 4, He teaches techniques of accessing memory circuits in claim 1. However, He does not explicitly teach teaches The integrated circuit of claim 1, the controller circuit to generate an interrupt request on a bus to interrupt signal transmission on the bus prior to transmitting the information to the buffer circuit on the bus
On the other hand, Dropps which also relates to techniques of accessing memory circuits teaches The integrated circuit of claim 1, the controller circuit to generate an interrupt request on a bus to interrupt signal transmission on the bus prior to transmitting the information to the buffer circuit on the bus. (See Fig 4, col 10 line 25-31, illustrates at step B418 if it is determined in block B416 that the count in the counter 302 has reached or exceeded a threshold value, the interrupt process for notifying processor 224 is set and a dedicated register may be used to store an out-of-credit information)
Both He and Dropps relate to techniques of accessing memory circuits (see
He, abstract, and see Dropps, abstract, regarding bad block management for memory
devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine He with Dropps by incorporating
techniques of accessing memory circuits using amount of buffer spaces, as taught by Dropps; to illustrate at step B418 if it is determined in block B416 that the count in the counter 302 has reached or exceeded a threshold value, the interrupt process for notifying processor 224 is set and a dedicated register may be used to store an out-of-credit information. The combined system of He – Dropps allows same out-of-credit logic to be used to monitor out-of-credit conditions as mentioned in col 1 line 63. Therefore, the combination of He - Dropps improves situations where the receiving port may overflow with received frames. See Dropps, col 3 line 66-67.
Regarding claim 7, He teaches techniques of accessing memory circuits in claim 1. However, He does not explicitly teach teaches The integrated circuit of claim 1, the buffer circuit to store and manage the credits that indicate the amount of available storage space in the buffer circuit for storing the information received from the controller circuit
On the other hand, Dropps which also relates to techniques of accessing memory circuits teaches The integrated circuit of claim 1, the buffer circuit to store and manage the credits that indicate the amount of available storage space in the buffer circuit for storing the information received from the controller circuit. (See Fig 1, col 7-8 line 66, 1-2, illustrates credit information based on the space that is available or stored in a receive data buffer PBUF 204)
Both He and Dropps relate to techniques of accessing memory circuits (see
He, abstract, and see Dropps, abstract, regarding bad block management for memory
devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine He with Dropps by incorporating
techniques of accessing memory circuits using amount of buffer spaces, as taught by Dropps; to illustrate credit information based on the space that is available or stored in a receive data buffer PBUF 204. The combined system of He – Dropps allows same out-of-credit logic to be used to monitor out-of-credit conditions as mentioned in col 1 line 63. Therefore, the combination of He - Dropps improves situations where the receiving port may overflow with received frames. See Dropps, col 3 line 66-67.
Regarding claim 11, He teaches techniques of accessing memory circuits in claim 9. However, He does not explicitly teach teaches The method of claim 9 further comprising: changing a number of the credits in response to changes in the amount of storage available in the buffer circuit for storing the information
On the other hand, Dropps which also relates to techniques of accessing memory circuits teaches The method of claim 9 further comprising: changing a number of the credits in response to changes in the amount of storage available in the buffer circuit for storing the information. (See Fig 1, col 7 line 62-66, illustrates concept of credit is used based on based on the space that is available at PBUF 204)
Both He and Dropps relate to techniques of accessing memory circuits (see
He, abstract, and see Dropps, abstract, regarding bad block management for memory
devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine He with Dropps by incorporating
techniques of accessing memory circuits using amount of buffer spaces, as taught by Dropps; to illustrate concept of credit is used based on based on the space that is available at PBUF 204. The combined system of He – Dropps allows same out-of-credit logic to be used to monitor out-of-credit conditions as mentioned in col 1 line 63. Therefore, the combination of He - Dropps improves situations where the receiving port may overflow with received frames. See Dropps, col 3 line 66-67.
Regarding claim 12, He teaches techniques of accessing memory circuits in claim 9. However, He does not explicitly teach teaches The method of claim 9 further comprising: generating an interrupt request on a bus using the controller circuit to interrupt signal transmission on the bus prior to transmitting the information from the controller circuit to the buffer circuit
On the other hand, Dropps which also relates to techniques of accessing memory circuits teaches The method of claim 9 further comprising: generating an interrupt request on a bus using the controller circuit to interrupt signal transmission on the bus prior to transmitting the information from the controller circuit to the buffer circuit. (See Fig 4, col 10 line 25-31, illustrates at step B418 if it is determined in block B416 that the count in the counter 302 has reached or exceeded a threshold value, the interrupt process for notifying processor 224 is set and a dedicated register may be used to store an out-of-credit information)
Both He and Dropps relate to techniques of accessing memory circuits (see
He, abstract, and see Dropps, abstract, regarding bad block management for memory
devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine He with Dropps by incorporating
techniques of accessing memory circuits using amount of buffer spaces, as taught by Dropps; to illustrate at step B418 if it is determined in block B416 that the count in the counter 302 has reached or exceeded a threshold value, the interrupt process for notifying processor 224 is set and a dedicated register may be used to store an out-of-credit information. The combined system of He – Dropps allows same out-of-credit logic to be used to monitor out-of-credit conditions as mentioned in col 1 line 63. Therefore, the combination of He - Dropps improves situations where the receiving port may overflow with received frames. See Dropps, col 3 line 66-67.
Regarding claim 13, He teaches techniques of accessing memory circuits in claim 9. However, He does not explicitly teach teaches The method of claim 9 further comprising: storing the credits in the buffer circuit; and providing the credits to the controller circuit
On the other hand, Dropps which also relates to techniques of accessing memory circuits teaches The method of claim 9 further comprising: storing the credits in the buffer circuit; and providing the credits to the controller circuit. (See Fig 1, col 7-8 line 66, 1-2, illustrates credit information based on the space that is available or stored in a receive data buffer PBUF 204)
Both He and Dropps relate to techniques of accessing memory circuits (see
He, abstract, and see Dropps, abstract, regarding bad block management for memory
devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine He with Dropps by incorporating
techniques of accessing memory circuits using amount of buffer spaces, as taught by Dropps; to illustrate credit information based on the space that is available or stored in a receive data buffer PBUF 204. The combined system of He – Dropps allows same out-of-credit logic to be used to monitor out-of-credit conditions as mentioned in col 1 line 63. Therefore, the combination of He - Dropps improves situations where the receiving port may overflow with received frames. See Dropps, col 3 line 66-67.
Regarding claim 15, He teaches techniques of accessing memory circuits in claim 14. However, He does not explicitly teach teaches The method of claim 14 further comprising: transmitting the information stored in the memory circuits from the controller circuits to the buffer circuit through a bus if the credits indicate that enough storage is available in the buffer circuit and allocated to the memory circuits
On the other hand, Dropps which also relates to techniques of accessing memory circuits teaches The method of claim 14 further comprising: transmitting the information stored in the memory circuits from the controller circuits to the buffer circuit through a bus if the credits indicate that enough storage is available in the buffer circuit and allocated to the memory circuits. (See Fig 1, col 6 line 35-38, illustrates TPORT 208 includes a memory device shown as a transmit buffer (TBUF) 206 which may be used to stage information related to frames before being transmitted. In other words, TPORT 208 is used to transmit the information between memory and buffer)
Both He and Dropps relate to techniques of accessing memory circuits (see
He, abstract, and see Dropps, abstract, regarding bad block management for memory
devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine He with Dropps by incorporating
techniques of accessing memory circuits using amount of buffer spaces, as taught by Dropps; to illustrate TPORT 208 which includes a memory device shown as a transmit buffer (TBUF) 206 which may be used to stage information related to frames before being transmitted. In other words, TPORT 208 is used to transmit the information between memory and buffer. The combined system of He – Dropps allows same out-of-credit logic to be used to monitor out-of-credit conditions as mentioned in col 1 line 63. Therefore, the combination of He - Dropps improves situations where the receiving port may overflow with received frames. See Dropps, col 3 line 66-67.
Claim(s) 17 is rejected under 35 U.S.C. 103 as being unpatentable over Baeckler in view of He et al. (US 20220068329 A1) hereinafter He.
Regarding claim 17, Baeckler teaches techniques of accessing memory circuits in claim 16. However, Baeckler does not explicitly teach teaches The integrated circuit of claim 16, wherein the first configurable memory block circuit further comprises: an address decoder circuit to provide a read address to the first memory circuit for performing the read operation in response to the read pointer,
the address decoder circuit to provide a write address to the first memory circuit for performing the write operation in response to the write pointer
On the other hand, He which also relates to techniques of accessing memory circuits teaches The integrated circuit of claim 16, wherein the first configurable memory block circuit further comprises: an address decoder circuit to provide a read address to the first memory circuit for performing the read operation in response to the read pointer,
the address decoder circuit to provide a write address to the first memory circuit for performing the write operation in response to the write pointer. (See Fig 1, paragraph [0015], illustrates address decoder 120 may decode the address signal received from the address/command input circuit 115 and provide a row address signal XADD to the row decoder 130, and a column address signal YARD to the column decoder 140)
Both Baeckler and He relate to techniques of accessing memory circuits (see
Baeckler, abstract, and see He, abstract, regarding bad block management for memory
devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Baeckler with He by incorporating
techniques of accessing memory circuits using amount of buffer spaces, as taught by He; to illustrate TPORT 208 which includes a memory device shown as a transmit buffer (TBUF) 206 which may be used to stage information related to frames before being transmitted. In other words, TPORT 208 is used to transmit the information between memory and buffer. The combined system of Baeckler – He allows a control circuit of the memory to be configured to cause data to be read from or written to the low latency register circuit as mentioned in paragraph [0007]. Therefore, the combination of Baeckler - He improves performance. See He, paragraph [0001].
Claim(s) 18-19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Baeckler in view of Rudosky et al. (US 20130151793 A1) hereinafter Rudosky.
Regarding claim 18, Baeckler teaches techniques of accessing memory circuits in claim 16. However, Baeckler does not explicitly teach teaches The integrated circuit of claim 16 further comprising: a second configurable memory block circuit comprising a second memory circuit, wherein the first configurable memory block circuit further comprises a multiplexer circuit and a round robin arbiter circuit to manage traffic through the multiplexer circuit between first read data accessed from the first memory circuit during the read operation and second read data accessed from the second memory circuit
On the other hand, Rudosky which also relates to techniques of accessing memory circuits teaches The integrated circuit of claim 16 further comprising: a second configurable memory block circuit comprising a second memory circuit, wherein the first configurable memory block circuit further comprises a multiplexer circuit and a round robin arbiter circuit to manage traffic through the multiplexer circuit between first read data accessed from the first memory circuit during the read operation and second read data accessed from the second memory circuit. (See Fig 27 and 37, paragraph [0256] and [0256], illustrates input multiplexer (MUX) 335A may allow or not allow data into input queue and round robin arbitration scheme maybe used to determine conflicting contexts)
Both Baeckler and Rudosky relate to techniques of accessing memory circuits (see Baeckler, abstract, and see Rudosky, abstract, regarding bad block management for memory devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Baeckler with Rudosky by incorporating
techniques of accessing memory circuits using amount of buffer spaces, as taught by Rudosky; to illustrate input multiplexer (MUX) 335A may allow or not allow data into input queue and round robin arbitration scheme maybe used to determine conflicting contexts. The combined system of Baeckler – Rudosky allows some amount of configurability to be added to correct for design errors and other defects after the IC has been fabricated, or to allow modification of inputs and outputs, such as for configurable I/O and configurable data path widths as mentioned in paragraph [0008]. Therefore, the combination of Baeckler - Rudosky improves efficient use of resources. See Rudosky, paragraph [0124].
Regarding claim 19, Baeckler teaches techniques of accessing memory circuits in claim 18. However, Baeckler does not explicitly teach teaches The integrated circuit of claim 18 further comprising: a third configurable memory block circuit coupled to the first configurable memory block circuit, the round robin arbiter circuit to manage traffic through the multiplexer circuit to the third configurable memory block circuit
On the other hand, Rudosky which also relates to techniques of accessing memory circuits teaches The integrated circuit of claim 18 further comprising: a third configurable memory block circuit coupled to the first configurable memory block circuit, the round robin arbiter circuit to manage traffic through the multiplexer circuit to the third configurable memory block circuit. (See Fig 27 and 37, paragraph [0256] and [0256], illustrates input multiplexer (MUX) 335A may allow or not allow data into input queue and round robin arbitration scheme maybe used to determine conflicting contexts and examiner considers doing it for multiple configurable memory is same as doing for a single memory)
Both Baeckler and Rudosky relate to techniques of accessing memory circuits (see Baeckler, abstract, and see Rudosky, abstract, regarding bad block management for memory devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Baeckler with Rudosky by incorporating
techniques of accessing memory circuits using amount of buffer spaces, as taught by Rudosky; to illustrate input multiplexer (MUX) 335A which may allow or not allow data into input queue and round robin arbitration scheme maybe used to determine conflicting contexts and examiner considers doing it for multiple configurable memory is same as doing for a single memory. The combined system of Baeckler – Rudosky allows some amount of configurability to be added to correct for design errors and other defects after the IC has been fabricated, or to allow modification of inputs and outputs, such as for configurable I/O and configurable data path widths as mentioned in paragraph [0008]. Therefore, the combination of Baeckler - Rudosky improves efficient use of resources. See Rudosky, paragraph [0124].
20. Regarding claim 20, Baeckler teaches techniques of accessing memory circuits in claim 16. However, Baeckler does not explicitly teach teaches The integrated circuit of claim 16, wherein the first configurable memory block circuit further comprises a multiplexer circuit configurable to provide a write control signal from a second configurable memory block circuit or the write pointer to a third configurable memory block circuit
On the other hand, Rudosky which also relates to techniques of accessing memory circuits teaches The integrated circuit of claim 16, wherein the first configurable memory block circuit further comprises a multiplexer circuit configurable to provide a write control signal from a second configurable memory block circuit or the write pointer to a third configurable memory block circuit. (See Fig 9, paragraph [0339], illustrates a configurable element 270 which includes multiplexer 383 and 384 to control input signals)
Both Baeckler and Rudosky relate to techniques of accessing memory circuits (see Baeckler, abstract, and see Rudosky, abstract, regarding bad block management for memory devices).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Baeckler with Rudosky by incorporating
techniques of accessing memory circuits using amount of buffer spaces, as taught by Rudosky; to illustrate a configurable element 270 which includes multiplexer 383 and 384 to control input signals. The combined system of Baeckler – Rudosky allows some amount of configurability to be added to correct for design errors and other defects after the IC has been fabricated, or to allow modification of inputs and outputs, such as for configurable I/O and configurable data path widths as mentioned in paragraph [0008]. Therefore, the combination of Baeckler - Rudosky improves efficient use of resources. See Rudosky, paragraph [0124].
Conclusion
The prior art made of record and not relied upon is considered pertinent to
applicant's disclosure.
a. Tan et al. (US 20190214996 A1) teaches An integrated circuit may include integrated memory that is formed from a chain of memory blocks. Each memory block may have configurable input and output circuits. The configurable input and output circuits may be interposed between memory circuitry such as a memory array from circuitry external to the memory circuitry. The configurable input and output circuits may have upstream and downstream memory block connection ports. In such a way, configurable input and output circuits in a first memory block may pass control and address signals and data to configurable input and output circuits in a second memory block. By using the configurable input and output circuits, the integrated memory in the integrated circuit may operate to accommodate large bandwidth flows without using the general routing fabric of the integrated circuit.
b. Abdelfattah et al. (US 20150109024 A1) teaches An enhanced field programmable gate-array (FPGA) incorporates one or more programmable networks-on-chip (NoCs) or NoC components integrated within the FPGA fabric. This NoC interconnect augments the existing FPGA interconnect. In one embodiment, the NoC is used as system-level interconnect to connect compute and communication modules to one another and integrate large systems on the FPGA. The NoC components include a "fabric port", which is a configurable interface that bridges both data width and frequency between the embedded NoC routers and the FPGA fabric components such as logic blocks, block memory, multipliers, processors or I/Os. Finally, the FPGA design flow is modified to target the embedded NoC components either manually through designer intervention, or automatically.
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/S.K.C./Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132