CTFR 18/085,819 CTFR 91398 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Amendment The office action is responding to the arguments filed on 04/28/2026. Claims 1- 20 are pending. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1, 3, 5-6, 8-10 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over He et al. (US 20220068329 A1) in view of NADEAU-DOSTIE et al. (US 20080065929 A1) hereinafter He and NADEAU-DOSTIE. Regarding claim 1, He teaches An integrated circuit comprising: a buffer circuit; each of the first memory block circuit and the second memory block circuit including a memory circuit; (See Fig 1, paragraph [0013], illustrates a semiconductor device 100 includes a low latency register or buffer 122 and a memory array 145) and a controller circuit to determine whether the memory circuit stores information, (See Fig 1, paragraph [0021], illustrates control circuit 121 may make determination if the address provided by read command is a match or in other words, data is stored in that address of memory cell array 145) the controller circuit to determine whether to transmit the information stored in the memory circuit to the buffer circuit based on credits that indicate an amount of storage space available in the buffer circuit, and (See Fig 1, paragraph [0011], illustrates control circuit 121 may determine whether a slot is available based on a register full indication provided from the low latency register circuit 122. In other words, control circuit may determine availability of space based on credit or register full indication) the controller circuit to transmit the information to the buffer circuit if the credits indicate that sufficient storage space is available in the buffer circuit to store the information. (See Fig 1, paragraph [0022], illustrates the low latency register or buffer 122 may store the address and write data received from the I0 circuit 170 if indication is there that there is available slot in the buffer) He teaches techniques of accessing memory circuits above. However, He does not explicitly teach a memory block circuit chain including at least a first memory block circuit and a second memory block circuit, the first memory block circuit having a write data input port coupled directly to a write data output port of the second memory block circuit, On the other hand, NADEAU-DOSTIE which also relates to techniques of accessing memory circuits teaches a memory block circuit chain including at least a first memory block circuit and a second memory block circuit, (See Fig 3 and 10, paragraph [0088], illustrates flip-flop 730 which is associated with memory may be interposed after its corresponding multiplexer 353, 351 in the daisy chain . In other words, memory blocks can be in daisy chain using flip-flop to interpose in between) the first memory block circuit having a write data input port coupled directly to a write data output port of the second memory block circuit, (See Fig 3 and 10, paragraph [0088], illustrates flip-flop 730 which maybe interposed in daisy chain between memory circuits accepts at its input D the signal from output Q of the lowest order flip-flop 700. In other words, memory logic circuits may have input port coupled to output port of second memory circuit) Both He and NADEAU-DOSTIE relate to techniques of accessing memory circuits (see He, abstract, and see NADEAU-DOSTIE, abstract, regarding bad block management for memory devices). Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine He with NADEAU-DOSTIE by incorporating techniques of accessing memory circuits using amount of buffer spaces, as taught by NADEAU-DOSTIE; to enable flip-flop 730 which is associated with memory to be interposed after its corresponding multiplexer 353, 351 in the daisy chain or In other words, memory blocks can be in daisy chain using flip-flop to interpose in between and flip-flop 730 which maybe interposed in daisy chain between memory circuits to accept at its input D the signal from output Q of the lowest order flip-flop 700 or In other words, memory logic circuits may have input port coupled to output port of second memory circuit. The combined system of He – NADEAU-DOSTIE allows serial transfer approach which minimizes the integrated circuit real estate that may be otherwise dedicated to distribution of repair information as mentioned in paragraph [0016]. Therefore, the combination of He - NADEAU-DOSTIE improves repair performance. See NADEAU-DOSTIE, paragraph [0016]. Regarding claim 3, He in view of NADEAU-DOSTIE teaches techniques of accessing memory circuits in claim 1. However, He - NADEAU-DOSTIE combination does not explicitly teach The integrated circuit of claim 1, wherein the memory circuit is one of a set of memory circuits, and wherein the controller circuit is one of a set of controller circuits to determine whether to transmit information stored in the memory circuits to the buffer circuit based on the credits that indicate the amount of storage space available in the buffer circuit and allocated for storing the information stored in the memory circuits On the other hand, He which also relates to techniques of accessing memory circuits teaches The integrated circuit of claim 1, wherein the memory circuit is one of a set of memory circuits, and wherein the controller circuit is one of a set of controller circuits to determine whether to transmit information stored in the memory circuits to the buffer circuit based on the credits that indicate the amount of storage space available in the buffer circuit and allocated for storing the information stored in the memory circuits. (See Fig 1, paragraph [0011] and [0022], illustrates control circuit 121 may determine whether a slot is available based on a register full indication provided from the low latency register circuit 122. In other words, control circuit may determine availability of space based on credit or register full indication either to send to buffer or memory array) The same motivation that was utilized for combining He with NADEAU-DOSTIE as set forth in claim 1 is equally applicable to claim 3. Regarding claim 5, He in view of NADEAU-DOSTIE teaches techniques of accessing memory circuits in claim 1. However, He - NADEAU-DOSTIE combination does not explicitly teach The integrated circuit of claim 1, the buffer circuit to store the information received from the controller circuit On the other hand, He which also relates to techniques of accessing memory circuits teaches The integrated circuit of claim 1, the buffer circuit to store the information received from the controller circuit . (See Fig 1, paragraph [0022], illustrates the low latency register 122 may store the address and write data received from the I0 circuit 170 in an available slot) The same motivation that was utilized for combining He with NADEAU-DOSTIE as set forth in claim 1 is equally applicable to claim 5. Regarding claim 6, He in view of NADEAU-DOSTIE teaches techniques of accessing memory circuits in claim 1. However, He - NADEAU-DOSTIE combination does not explicitly teach The integrated circuit of claim 1, the memory circuit to store the information in response to a write request from a requesting circuit in the integrated circuit On the other hand, He which also relates to techniques of accessing memory circuits teaches The integrated circuit of claim 1, the memory circuit to store the information in response to a write request from a requesting circuit in the integrated circuit. (See Fig 1, paragraph [0022], illustrates if no slots are available, the control circuit 121 may cause the write data to be written to the memory cell array 145 based on the address) The same motivation that was utilized for combining He with NADEAU-DOSTIE as set forth in claim 1 is equally applicable to claim 6. Regarding claim 8, He in view of NADEAU-DOSTIE teaches techniques of accessing memory circuits in claim 1. However, He - NADEAU-DOSTIE combination does not explicitly teach The integrated circuit of claim 1, wherein the information stored in the memory circuit is one of a write address or write data for a write operation On the other hand, He which also relates to techniques of accessing memory circuits teaches The integrated circuit of claim 1, wherein the information stored in the memory circuit is one of a write address or write data for a write operation. (See Fig 1, paragraph [0022], illustrates if no slots are available in register 122, the control circuit 121 may cause the write data to be written to the memory cell array 145 based on the address) The same motivation that was utilized for combining He with NADEAU-DOSTIE as set forth in claim 1 is equally applicable to claim 8. Regarding claim 9, He teaches A method comprising: determining whether a memory circuit stores information; (See Fig 1, paragraph [0013], illustrates a semiconductor device 100 includes a low latency register or buffer 122 and a memory array 145) determining whether to transmit the information stored in the memory circuit to a buffer circuit using a controller circuit based on credits that indicate an amount of available storage in the buffer circuit; (See Fig 1, paragraph [0011], illustrates control circuit 121 may determine whether a slot is available based on a register full indication provided from the low latency register circuit 122. In other words, control circuit may determine availability of space based on credit or register full indication) transmitting the information from the controller circuit to the buffer circuit if the credits indicate that enough storage is available in the buffer circuit to store the information; and storing the information in the buffer circuit. (See Fig 1, paragraph [0022], illustrates the low latency register or buffer 122 may store the address and write data received from the I0 circuit 170 if indication is there that there is available slot in the buffer) He teaches techniques of accessing memory circuits above. However, He does not explicitly teach a memory circuit of memory block circuit chain stores information, the memory block circuit chain including at least a first memory block circuit and a second memory block circuit, the first memory block circuit having a write data input port coupled directly to a write data output port of the second memory block circuit, On the other hand, NADEAU-DOSTIE which also relates to techniques of accessing memory circuits teaches a memory circuit of memory block circuit chain stores information, the memory block circuit chain including at least a first memory block circuit and a second memory block circuit, (See Fig 3 and 10, paragraph [0087] and [0088], illustrates flip-flop 730 which is associated with memory may be interposed after its corresponding multiplexer 353, 351 in the daisy chain and also data may be stored in flip-flops. In other words, memory blocks can be in daisy chain using flip-flop to interpose in between) the first memory block circuit having a write data input port coupled directly to a write data output port of the second memory block circuit, (See Fig 3 and 10, paragraph [0088], illustrates flip-flop 730 which maybe interposed in daisy chain between memory circuits accepts at its input D the signal from output Q of the lowest order flip-flop 700. In other words, memory logic circuits may have input port coupled to output port of second memory circuit) Both He and NADEAU-DOSTIE relate to techniques of accessing memory circuits (see He, abstract, and see NADEAU-DOSTIE, abstract, regarding bad block management for memory devices). Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine He with NADEAU-DOSTIE by incorporating techniques of accessing memory circuits using amount of buffer spaces, as taught by NADEAU-DOSTIE; to enable flip-flop 730 which is associated with memory to be interposed after its corresponding multiplexer 353, 351 in the daisy chain or In other words, memory blocks can be in daisy chain using flip-flop to interpose in between and flip-flop 730 which maybe interposed in daisy chain between memory circuits to accept at its input D the signal from output Q of the lowest order flip-flop 700 or In other words, memory logic circuits may have input port coupled to output port of second memory circuit. The combined system of He – NADEAU-DOSTIE allows serial transfer approach which minimizes the integrated circuit real estate that may be otherwise dedicated to distribution of repair information as mentioned in paragraph [0016]. Therefore, the combination of He - NADEAU-DOSTIE improves repair performance. See NADEAU-DOSTIE, paragraph [0016]. Regarding claim 10, He in view of NADEAU-DOSTIE teaches techniques of accessing memory circuits in claim 9. However, He - NADEAU-DOSTIE combination does not explicitly teach The method of claim 9 further comprising: storing the information in the memory circuit in response to a write request from a requesting circuit On the other hand, He which also relates to techniques of accessing memory circuits teaches The method of claim 9 further comprising: storing the information in the memory circuit in response to a write request from a requesting circuit. (See Fig 1, paragraph [0022], illustrates if no slots are available, the control circuit 121 may cause the write data to be written to the memory cell array 145 based on the address) The same motivation that was utilized for combining He with NADEAU-DOSTIE as set forth in claim 9 is equally applicable to claim 10. Regarding claim 14, He in view of NADEAU-DOSTIE teaches techniques of accessing memory circuits in claim 9. However, He - NADEAU-DOSTIE combination does not explicitly teach The method of claim 9 further comprising: determining whether to transmit information stored in memory circuits to the buffer circuit based on the credits that indicate the amount of available storage in the buffer circuit allocated for storing the information stored in the memory circuits using controller circuits that comprise the controller circuit, wherein the memory circuits comprise the memory circuit On the other hand, He which also relates to techniques of accessing memory circuits teaches The method of claim 9 further comprising: determining whether to transmit information stored in memory circuits to the buffer circuit based on the credits that indicate the amount of available storage in the buffer circuit allocated for storing the information stored in the memory circuits using controller circuits that comprise the controller circuit, wherein the memory circuits comprise the memory circuit. (See Fig 1, paragraph [0011] and [0022], illustrates control circuit 121 may determine whether a slot is available based on a register full indication provided from the low latency register circuit 122. In other words, control circuit may determine availability of space based on credit or register full indication either to send to buffer or memory array) The same motivation that was utilized for combining He with NADEAU-DOSTIE as set forth in claim 9 is equally applicable to claim 14. 07-21-aia AIA Claim (s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over He in view of NADEAU-DOSTIE and further in view of Baeckler hereinafter He and NADEAU-DOSTIE . Regarding claim 16, He in view of NADEAU-DOSTIE teaches techniques of accessing memory circuits in claim 1. However, He - NADEAU-DOSTIE combination does not explicitly teach An integrated circuit of claim 1, wherein each of the first memory block circuit and the second memory block circuit also includes: a write address generator circuit to generate a write pointer for a write operation to a first memory circuit; a read address generator circuit to generate a read pointer for a read operation to the first memory circuit; a write control logic circuit to generate a write status control signal that indicates that the first memory circuit is full when a separation between the read pointer and the write pointer reaches a predefined full value; and a read control logic circuit to generate a read status control signal that indicates that the first memory circuit is empty when the separation between the read pointer and the write pointer reaches zero On the other hand, Baeckler which also relates to techniques of accessing memory circuits teaches An integrated circuit of claim 1, wherein each of the first memory block circuit and the second memory block circuit also includes: (See Fig 1, col 9 line 37-39, illustrates storage circuit 201 may include multiple RAM cells or register circuits that can store a word of data, in other words, storage circuit may include multiple memory block circuits) a write address generator circuit to generate a write pointer for a write operation to a first memory circuit; (See Fig 1, col 6 line 42-43, illustrates Write pointer generator circuit 102 also generates write pointer signals WPTRWC that indicate a write pointer) a read address generator circuit to generate a read pointer for a read operation to the first memory circuit; (See Fig 1, col 6 line 42-43, illustrates Read pointer generator circuit 103 also generates read pointer signals RPTRRC that indicate a read pointer) a write control logic circuit to generate a write status control signal that indicates that the first memory circuit is full when a separation between the read pointer and the write pointer reaches a predefined full value; and a read control logic circuit to generate a read status control signal that indicates that the first memory circuit is empty when the separation between the read pointer and the write pointer reaches zero. (See Fig 1, col 8 line 4-13, illustrates the write pointer signals WPTRWC include one or more additional bits relative to the write address signals WADDR and the read pointer signals RPTRRC include one or more additional bits relative to the read address signals RADDR where The additional bits in the read and write pointer signals can be used to differentiate when storage circuit 101 is full of words of data and when storage circuit 101 is empty) Both He, NADEAU-DOSTIE and Baeckler relate to techniques of accessing memory circuits (see He, abstract, and see NADEAU-DOSTIE, abstract, and see Baeckler, abstract, regarding bad block management for memory devices). Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine He - NADEAU-DOSTIE combination with Baeckler by incorporating techniques of accessing memory circuits using amount of buffer spaces, as taught by Baeckler; to enable flip-flop 730 which is associated with memory to be interposed after its corresponding multiplexer 353, 351 in the daisy chain or In other words, memory blocks can be in daisy chain using flip-flop to interpose in between and flip-flop 730 which maybe interposed in daisy chain between memory circuits to accept at its input D the signal from output Q of the lowest order flip-flop 700 or In other words, memory logic circuits may have input port coupled to output port of second memory circuit. The combined system of He - NADEAU-DOSTIE – Baeckler allows serial transfer approach which minimizes the integrated circuit real estate that may be otherwise dedicated to distribution of repair information as mentioned in paragraph [0016]. Therefore, the combination of He - NADEAU-DOSTIE – Baeckler improves repair performance. See Baeckler, paragraph [0016] . 07-21-aia AIA Claim (s) 2, 4, 7, 11-13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over He in view of NADEAU-DOSTIE and further in view of Dropps et al. (US 9094294 B1) hereinafter Dropps . Regarding claim 2, He in view of NADEAU-DOSTIE teaches techniques of accessing memory circuits in claim 1. However, He - NADEAU-DOSTIE combination does not explicitly teach The integrated circuit of claim 1, the buffer circuit to change a number of the credits in response to changes in the amount of storage space available in the buffer circuit On the other hand, Dropps which also relates to techniques of accessing memory circuits teaches The integrated circuit of claim 1, the buffer circuit to change a number of the credits in response to changes in the amount of storage space available in the buffer circuit. (See Fig 1, col 7 line 62-66, illustrates concept of credit is used based on based on the space that is available at PBUF 204) Both He, NADEAU-DOSTIE and Dropps relate to techniques of accessing memory circuits (see He, abstract, and see NADEAU-DOSTIE, abstract, and see Dropps, abstract, regarding bad block management for memory devices). Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine He - NADEAU-DOSTIE with Dropps by incorporating techniques of accessing memory circuits using amount of buffer spaces, as taught by Dropps; to illustrate concept of credit is used based on based on the space that is available at PBUF 204. The combined system of He - NADEAU-DOSTIE – Dropps allows same out-of-credit logic to be used to monitor out-of-credit conditions as mentioned in col 1 line 63. Therefore, the combination of He - NADEAU-DOSTIE - Dropps improves situations where the receiving port may overflow with received frames. See Dropps, col 3 line 66-67. Regarding claim 4, He in view of NADEAU-DOSTIE teaches techniques of accessing memory circuits in claim 1. However, He - NADEAU-DOSTIE combination does not explicitly teach The integrated circuit of claim 1, the controller circuit to generate an interrupt request on a bus to interrupt signal transmission on the bus prior to transmitting the information to the buffer circuit on the bus On the other hand, Dropps which also relates to techniques of accessing memory circuits teaches The integrated circuit of claim 1, the controller circuit to generate an interrupt request on a bus to interrupt signal transmission on the bus prior to transmitting the information to the buffer circuit on the bus. (See Fig 4, col 10 line 25-31, illustrates at step B418 if it is determined in block B416 that the count in the counter 302 has reached or exceeded a threshold value, the interrupt process for notifying processor 224 is set and a dedicated register may be used to store an out-of-credit information) Both He, NADEAU-DOSTIE and Dropps relate to techniques of accessing memory circuits (see He, abstract, and see NADEAU-DOSTIE, abstract, and see Dropps, abstract, regarding bad block management for memory devices). Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine He - NADEAU-DOSTIE combination with Dropps by incorporating techniques of accessing memory circuits using amount of buffer spaces, as taught by Dropps; to illustrate at step B418 if it is determined in block B416 that the count in the counter 302 has reached or exceeded a threshold value, the interrupt process for notifying processor 224 is set and a dedicated register may be used to store an out-of-credit information. The combined system of He - NADEAU-DOSTIE – Dropps allows same out-of-credit logic to be used to monitor out-of-credit conditions as mentioned in col 1 line 63. Therefore, the combination of He - NADEAU-DOSTIE - Dropps improves situations where the receiving port may overflow with received frames. See Dropps, col 3 line 66-67. Regarding claim 7, He in view of NADEAU-DOSTIE teaches techniques of accessing memory circuits in claim 1. However, He - NADEAU-DOSTIE combination does not explicitly teach The integrated circuit of claim 1, the buffer circuit to store and manage the credits that indicate the amount of available storage space in the buffer circuit for storing the information received from the controller circuit On the other hand, Dropps which also relates to techniques of accessing memory circuits teaches The integrated circuit of claim 1, the buffer circuit to store and manage the credits that indicate the amount of available storage space in the buffer circuit for storing the information received from the controller circuit. (See Fig 1, col 7-8 line 66, 1-2, illustrates credit information based on the space that is available or stored in a receive data buffer PBUF 204) Both He, NADEAU-DOSTIE and Dropps relate to techniques of accessing memory circuits (see He, abstract, and see NADEAU-DOSTIE, abstract, and see Dropps, abstract, regarding bad block management for memory devices). Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine He - NADEAU-DOSTIE combination with Dropps by incorporating techniques of accessing memory circuits using amount of buffer spaces, as taught by Dropps; to illustrate credit information based on the space that is available or stored in a receive data buffer PBUF 204. The combined system of He - NADEAU-DOSTIE – Dropps allows same out-of-credit logic to be used to monitor out-of-credit conditions as mentioned in col 1 line 63. Therefore, the combination of He - NADEAU-DOSTIE - Dropps improves situations where the receiving port may overflow with received frames. See Dropps, col 3 line 66-67. Regarding claim 11, He in view of NADEAU-DOSTIE teaches techniques of accessing memory circuits in claim 9. However, He - NADEAU-DOSTIE combination does not explicitly teach The method of claim 9 further comprising: changing a number of the credits in response to changes in the amount of storage available in the buffer circuit for storing the information On the other hand, Dropps which also relates to techniques of accessing memory circuits teaches The method of claim 9 further comprising: changing a number of the credits in response to changes in the amount of storage available in the buffer circuit for storing the information. (See Fig 1, col 7 line 62-66, illustrates concept of credit is used based on based on the space that is available at PBUF 204) Both He, NADEAU-DOSTIE and Dropps relate to techniques of accessing memory circuits (see He, abstract, and see NADEAU-DOSTIE, abstract, and see Dropps, abstract, regarding bad block management for memory devices). Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine He - NADEAU-DOSTIE combination with Dropps by incorporating techniques of accessing memory circuits using amount of buffer spaces, as taught by Dropps; to illustrate concept of credit is used based on based on the space that is available at PBUF 204. The combined system of He - NADEAU-DOSTIE – Dropps allows same out-of-credit logic to be used to monitor out-of-credit conditions as mentioned in col 1 line 63. Therefore, the combination of He - NADEAU-DOSTIE - Dropps improves situations where the receiving port may overflow with received frames. See Dropps, col 3 line 66-67. Regarding claim 12, He in view of NADEAU-DOSTIE teaches techniques of accessing memory circuits in claim 9. However, He - NADEAU-DOSTIE combination does not explicitly teach The method of claim 9 further comprising: generating an interrupt request on a bus using the controller circuit to interrupt signal transmission on the bus prior to transmitting the information from the controller circuit to the buffer circuit On the other hand, Dropps which also relates to techniques of accessing memory circuits teaches The method of claim 9 further comprising: generating an interrupt request on a bus using the controller circuit to interrupt signal transmission on the bus prior to transmitting the information from the controller circuit to the buffer circuit. (See Fig 4, col 10 line 25-31, illustrates at step B418 if it is determined in block B416 that the count in the counter 302 has reached or exceeded a threshold value, the interrupt process for notifying processor 224 is set and a dedicated register may be used to store an out-of-credit information) Both He, NADEAU-DOSTIE and Dropps relate to techniques of accessing memory circuits (see He, abstract, and see NADEAU-DOSTIE, abstract, and see Dropps, abstract, regarding bad block management for memory devices). Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine He - NADEAU-DOSTIE combination with Dropps by incorporating techniques of accessing memory circuits using amount of buffer spaces, as taught by Dropps; to illustrate at step B418 if it is determined in block B416 that the count in the counter 302 has reached or exceeded a threshold value, the interrupt process for notifying processor 224 is set and a dedicated register may be used to store an out-of-credit information. The combined system of He - NADEAU-DOSTIE – Dropps allows same out-of-credit logic to be used to monitor out-of-credit conditions as mentioned in col 1 line 63. Therefore, the combination of He - NADEAU-DOSTIE - Dropps improves situations where the receiving port may overflow with received frames. See Dropps, col 3 line 66-67. Regarding claim 13, He in view of NADEAU-DOSTIE teaches techniques of accessing memory circuits in claim 9. However, He - NADEAU-DOSTIE combination does not explicitly teach The method of claim 9 further comprising: storing the credits in the buffer circuit; and providing the credits to the controller circuit On the other hand, Dropps which also relates to techniques of accessing memory circuits teaches The method of claim 9 further comprising: storing the credits in the buffer circuit; and providing the credits to the controller circuit. (See Fig 1, col 7-8 line 66, 1-2, illustrates credit information based on the space that is available or stored in a receive data buffer PBUF 204) Both He, NADEAU-DOSTIE and Dropps relate to techniques of accessing memory circuits (see He, abstract, and see NADEAU-DOSTIE, abstract, and see Dropps, abstract, regarding bad block management for memory devices). Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine He - NADEAU-DOSTIE combination with Dropps by incorporating techniques of accessing memory circuits using amount of buffer spaces, as taught by Dropps; to illustrate credit information based on the space that is available or stored in a receive data buffer PBUF 204. The combined system of He - NADEAU-DOSTIE – Dropps allows same out-of-credit logic to be used to monitor out-of-credit conditions as mentioned in col 1 line 63. Therefore, the combination of He - NADEAU-DOSTIE - Dropps improves situations where the receiving port may overflow with received frames. See Dropps, col 3 line 66-67. Regarding claim 15, He in view of NADEAU-DOSTIE teaches techniques of accessing memory circuits in claim 14. However, He - NADEAU-DOSTIE combination does not explicitly teach The method of claim 14 further comprising: transmitting the information stored in the memory circuits from the controller circuits to the buffer circuit through a bus if the credits indicate that enough storage is available in the buffer circuit and allocated to the memory circuits On the other hand, Dropps which also relates to techniques of accessing memory circuits teaches The method of claim 14 further comprising: transmitting the information stored in the memory circuits from the controller circuits to the buffer circuit through a bus if the credits indicate that enough storage is available in the buffer circuit and allocated to the memory circuits. (See Fig 1, col 6 line 35-38, illustrates TPORT 208 includes a memory device shown as a transmit buffer (TBUF) 206 which may be used to stage information related to frames before being transmitted. In other words, TPORT 208 is used to transmit the information between memory and buffer) Both He, NADEAU-DOSTIE and Dropps relate to techniques of accessing memory circuits (see He, abstract, and see NADEAU-DOSTIE, abstract, and see Dropps, abstract, regarding bad block management for memory devices). Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine He - NADEAU-DOSTIE combination with Dropps by incorporating techniques of accessing memory circuits using amount of buffer spaces, as taught by Dropps; to illustrate TPORT 208 which includes a memory device shown as a transmit buffer (TBUF) 206 which may be used to stage information related to frames before being transmitted. In other words, TPORT 208 is used to transmit the information between memory and buffer. The combined system of He - NADEAU-DOSTIE – Dropps allows same out-of-credit logic to be used to monitor out-of-credit conditions as mentioned in col 1 line 63. Therefore, the combination of He - NADEAU-DOSTIE - Dropps improves situations where the receiving port may overflow with received frames. See Dropps, col 3 line 66-67 . 07-21-aia AIA Claim (s) 17 is rejected under 35 U.S.C. 103 as being unpatentable over He in view of NADEAU-DOSTIE and further in view of Baeckler . Regarding claim 17, He in view of NADEAU-DOSTIE and further in view of Baeckler teaches techniques of accessing memory circuits in claim 16. However, He - NADEAU-DOSTIE - Baeckler combination does not explicitly teach teaches The integrated circuit of claim 16, wherein the first configurable memory block circuit further comprises: an address decoder circuit to provide a read address to the first memory circuit for performing the read operation in response to the read pointer, the address decoder circuit to provide a write address to the first memory circuit for performing the write operation in response to the write pointer On the other hand, He which also relates to techniques of accessing memory circuits teaches The integrated circuit of claim 16, wherein the first configurable memory block circuit further comprises: an address decoder circuit to provide a read address to the first memory circuit for performing the read operation in response to the read pointer, the address decoder circuit to provide a write address to the first memory circuit for performing the write operation in response to the write pointer. (See Fig 1, paragraph [0015], illustrates address decoder 120 may decode the address signal received from the address/command input circuit 115 and provide a row address signal XADD to the row decoder 130, and a column address signal YARD to the column decoder 140) The same motivation that was utilized for combining He - NADEAU-DOSTIE combination with Baeckler as set forth in claim 16 is equally applicable to claim 17 . 07-21-aia AIA Claim (s) 18-19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over He in view of NADEAU-DOSTIE and further in view of Baeckler and further in view of Rudosky et al. (US 20130151793 A1) hereinafter Rudosky . Regarding claim 18, He in view of NADEAU-DOSTIE and further in view of Baeckler teaches techniques of accessing memory circuits in claim 16. However, He - NADEAU-DOSTIE - Baeckler combination does not explicitly teach teaches The integrated circuit of claim 16 further comprising: a second configurable memory block circuit comprising a second memory circuit, wherein the first configurable memory block circuit further comprises a multiplexer circuit and a round robin arbiter circuit to manage traffic through the multiplexer circuit between first read data accessed from the first memory circuit during the read operation and second read data accessed from the second memory circuit On the other hand, Rudosky which also relates to techniques of accessing memory circuits teaches The integrated circuit of claim 16 further comprising: a second configurable memory block circuit comprising a second memory circuit, wherein the first configurable memory block circuit further comprises a multiplexer circuit and a round robin arbiter circuit to manage traffic through the multiplexer circuit between first read data accessed from the first memory circuit during the read operation and second read data accessed from the second memory circuit. (See Fig 27 and 37, paragraph [0256] and [0256], illustrates input multiplexer (MUX) 335A may allow or not allow data into input queue and round robin arbitration scheme maybe used to determine conflicting contexts) Both He, NADEAU-DOSTIE, Baeckler and Rudosky relate to techniques of accessing memory circuits (see He, abstract, and see NADEAU-DOSTIE, abstract, and see Baeckler, abstract, and see Rudosky, abstract, regarding bad block management for memory devices). Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine He - NADEAU-DOSTIE - Baeckler combination with Rudosky by incorporating techniques of accessing memory circuits using amount of buffer spaces, as taught by Rudosky; to illustrate input multiplexer (MUX) 335A may allow or not allow data into input queue and round robin arbitration scheme maybe used to determine conflicting contexts. The combined system of He - NADEAU-DOSTIE - Baeckler – Rudosky allows some amount of configurability to be added to correct for design errors and other defects after the IC has been fabricated, or to allow modification of inputs and outputs, such as for configurable I/O and configurable data path widths as mentioned in paragraph [0008]. Therefore, the combination of He - NADEAU-DOSTIE - Baeckler - Rudosky improves efficient use of resources. See Rudosky, paragraph [0124]. Regarding claim 19, He in view of NADEAU-DOSTIE and further in view of Baeckler teaches techniques of accessing memory circuits in claim 18. However, He - NADEAU-DOSTIE - Baeckler combination does not explicitly teach teaches The integrated circuit of claim 18 further comprising: a third configurable memory block circuit coupled to the first configurable memory block circuit, the round robin arbiter circuit to manage traffic through the multiplexer circuit to the third configurable memory block circuit On the other hand, Rudosky which also relates to techniques of accessing memory circuits teaches The integrated circuit of claim 18 further comprising: a third configurable memory block circuit coupled to the first configurable memory block circuit, the round robin arbiter circuit to manage traffic through the multiplexer circuit to the third configurable memory block circuit. (See Fig 27 and 37, paragraph [0256] and [0256], illustrates input multiplexer (MUX) 335A may allow or not allow data into input queue and round robin arbitration scheme maybe used to determine conflicting contexts and examiner considers doing it for multiple configurable memory is same as doing for a single memory) Both He, NADEAU-DOSTIE, Baeckler and Rudosky relate to techniques of accessing memory circuits (see He, abstract, and see NADEAU-DOSTIE, abstract, and see Baeckler, abstract, and see Rudosky, abstract, regarding bad block management for memory devices). Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine He - NADEAU-DOSTIE - Baeckler combination with Rudosky by incorporating techniques of accessing memory circuits using amount of buffer spaces, as taught by Rudosky; to illustrate input multiplexer (MUX) 335A which may allow or not allow data into input queue and round robin arbitration scheme maybe used to determine conflicting contexts and examiner considers doing it for multiple configurable memory is same as doing for a single memory. The combined system of He - NADEAU-DOSTIE - Baeckler – Rudosky allows some amount of configurability to be added to correct for design errors and other defects after the IC has been fabricated, or to allow modification of inputs and outputs, such as for configurable I/O and configurable data path widths as mentioned in paragraph [0008]. Therefore, the combination of He - NADEAU-DOSTIE - Baeckler - Rudosky improves efficient use of resources. See Rudosky, paragraph [0124]. Regarding claim 20, He in view of NADEAU-DOSTIE and further in view of Baeckler teaches techniques of accessing memory circuits in claim 16. However, He - NADEAU-DOSTIE - Baeckler combination does not explicitly teach teaches The integrated circuit of claim 16, wherein the first configurable memory block circuit further comprises a multiplexer circuit configurable to provide a write control signal from a second configurable memory block circuit or the write pointer to a third configurable memory block circuit On the other hand, Rudosky which also relates to techniques of accessing memory circuits teaches The integrated circuit of claim 16, wherein the first configurable memory block circuit further comprises a multiplexer circuit configurable to provide a write control signal from a second configurable memory block circuit or the write pointer to a third configurable memory block circuit. (See Fig 9, paragraph [0339], illustrates a configurable element 270 which includes multiplexer 383 and 384 to control input signals) Both He, NADEAU-DOSTIE, Baeckler and Rudosky relate to techniques of accessing memory circuits (see He, abstract, and see NADEAU-DOSTIE, abstract, and see Baeckler, abstract, and see Rudosky, abstract, regarding bad block management for memory devices). Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine He - NADEAU-DOSTIE - Baeckler combination with Rudosky by incorporating techniques of accessing memory circuits using amount of buffer spaces, as taught by Rudosky; to illustrate a configurable element 270 which includes multiplexer 383 and 384 to control input signals. The combined system of He - NADEAU-DOSTIE - Baeckler – Rudosky allows some amount of configurability to be added to correct for design errors and other defects after the IC has been fabricated, or to allow modification of inputs and outputs, such as for configurable I/O and configurable data path widths as mentioned in paragraph [0008]. Therefore, the combination of He - NADEAU-DOSTIE - Baeckler - Rudosky improves efficient use of resources. See Rudosky, paragraph [0124]. Response to Arguments 07-37 Applicant’s arguments filed on 04/28/2026 have been fully considered but they are not persuasive. Applicant’s first argument is claim 1 mapping by primary and secondary references in page 6 pf the response: independent claim 1 has been amended to include a memory block circuit chain including at least a first memory block circuit and a second memory block circuit, the first memory block circuit having a write data input port coupled directly to a write data output port of the second memory block circuit. Each of the other claims, by amendment or dependence, includes a corresponding limitation. This limitation is not found in He, and nothing is found in Baeckler, Dropps, and/or that could be combined to add it In summary, applicant argued that primary reference KIM does not teach amended limitations of claim 1. The amendment necessitates adding another secondary reference NADEAU-DOSTIE in this regard. For further clarification examiner cites portion from NADEAU-DOSTIE. Also, for applicant’s understanding examiner would like to explain the teachings of NADEAU-DOSTIE and examiner’s interpretation in more detail here. See Fig 3 and 10, paragraph [0088], NADEAU-DOSTIE teaches flip-flop 730 which is associated with memory may be interposed after its corresponding multiplexer 353, 351 in the daisy chain . In other words, memory blocks can be in daisy chain using flip-flop to interpose in between. See Fig 3 and 10, paragraph [0088], NADEAU-DOSTIE teaches flip-flop 730 which maybe interposed in daisy chain between memory circuits accepts at its input D the signal from output Q of the lowest order flip-flop 700. In other words, memory logic circuits may have input port coupled to output port of second memory circuit. The cited portions clearly teach memory blocks can be in daisy chain using flip-flop to interpose in between and memory logic circuits may have input port coupled to output port of second memory circuit. Thus, the rejection of amended claims 1 and 9 is maintained. Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUBIR K CHOWDHURY whose telephone number is (703)756-1207. The examiner can normally be reached Monday-Friday 8:30 - 5:00 CST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571)-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /S.K.C./Examiner, Art Unit 2132 /HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132 Application/Control Number: 18/085,819 Page 2 Art Unit: 2132 Application/Control Number: 18/085,819 Page 3 Art Unit: 2132
Prosecution Insights