DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The office action is responding to the amendments filed on 05/01/2026. Claims 1, 8 and 15 have been amended.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 8 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over O'Shea et al. [US 8,645,623 B1] in view of Mital et al. [US 2013/0091330 A1].
Claim 1 is rejected over O'Shea and Mital.
O'Shea teaches “An apparatus comprising: packet processing circuitry to process a network packet, the packet processing circuitry including:” as “The packet switch network passes both user data and messages, the user data passing through the data pipe and the messages being generated and received by the message engine.” [Col 1, lines 63-66]
“memory access circuitry, the memory access circuitry to:” as “ a DSA transfer is used for a CPU within a storage processor (SP) to indirectly access a local/remote memory in any SP on the packet switching network.” [Col 2, lines 53-56]
“collect evicted data in multiple data fields in a line, the multiple data fields to match data fields in a memory line in an external memory, the evicted data written to the multiple data fields at different times; and” as “Bit 63 of the primary or secondary address in FIG. 4H is the `context enable` which ensures that the setup directed to a particular context was fully assembled by the program (i.e., software) running on the CPU before it was evicted.” [Col 14, lines 62-65]
“perform a single read-modify-write operation to update the memory line in the external memory with the evicted data stored in the line;” as “an atomic read-modify-write operation modifies the read data and writes the modified data back into the same memory location from which it was originally read.” [Col 17, lines 58-60]
O'Shea does not explicitly teach wherein: the evicted data comprises object data to be used by the packet processing circuitry in one or more network packet processing operations.
However, Mital teaches “wherein: the evicted data comprises object data to be used by the packet processing circuitry in one or more network packet processing operations.” as “at step 520, older data is evicted from system cache 400 in order to write the received packet data, process 500 proceeds to step 526.” [¶0048] (It is implied, the older data is previously loaded packet data) and “Network processors are generally used for analyzing and processing packet data for routing and switching packets in a variety of applications” [¶0004]
O'Shea and Mital are analogous arts because they teach data storage system and cache management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of O'Shea and Mital before him/her, to modify the teachings of O'Shea to include the teachings of Mital with the motivation of allow network processor 100 to process a wide variety of data and control messages more efficiently than with a fixed pipeline or non-pipelined architecture. [Mital, ¶0020]
Claim 8 recites a method with the same limitations as claim 1 and rejected over O'Shea and Mital under the same rationale of rejection of claim 1.
Claim 15 recites a system with the same limitations as claim 1 and antic rejected over O'Shea and Mital under the same rationale of rejection of claim 1.
Claim(s) 2, 9 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over O'Shea et al. [US 8,645,623 B1] in view of Mital et al. [US 2013/0091330 A1] and in further view of Mevergnies et al. [US 2007/0277001 A1].
Claim 2 is rejected over O'Shea, Mital and Mevergnies.
The combination of O'Shea and Mital does not explicitly teach wherein the line and the memory line have N bytes, N is an integer multiple of 4 and each of the data fields in the line to store evicted data has N/4 bytes.
However, Mevergnies teaches “wherein the line and the memory line have N bytes, N is an integer multiple of 4 and each of the data fields in the line to store evicted data has N/4 bytes.” as “In box 234, the execution of another instruction of the second process causes a fourth block of data from the system memory to be loaded into a second line of the cache memory, causing the second block of data to be evicted, for example, due to the set-associative property of the cache memory.” [¶0018]
O'Shea, Mital and Mevergnies are analogous arts because they teach data storage system and cache management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of O'Shea, Mital and Mevergnies before him/her, to modify the teachings of combination of O'Shea and Mital to include the teachings of Mevergnies with the motivation of a single cache security logic element may be enabled for multiple processes running on different processors, so long as the processes share a common cache memory. [Mevergnies, ¶0027]
Claim 9 recites a method with the same limitation as claim 2 and rejected over O'Shea, Mital and Mevergnies under the same rationale of rejection of claim 2.
Claim 16 recites a system with the same limitation as claim 2 and rejected over O'Shea, Mital and Mevergnies under the same rationale of rejection of claim 2.
Claim(s) 6, 13 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over O'Shea et al. [US 8,645,623 B1] in view of Mital et al. [US 2013/0091330 A1] and in further view of Chen. [US 2023/0120806 A1].
Claim 6 is rejected over O'Shea, Mital and Chen.
The combination of O'Shea and Mital does not explicitly teach wherein the external memory is a dynamic random access memory.
However, Chen teaches “wherein the external memory is a dynamic random access memory.” as “the external memory 180 is a dynamic random access memory (DRAM).” [¶0021]
O'Shea, Mital and Chen are analogous arts because they teach data storage system and cache management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of O'Shea, Mital and Chen before him/her, to modify the teachings of combination of O'Shea and Mital to include the teachings of Chen with the motivation of data transmissions between the internal memory and the external memory are reduced and convolution operation efficiency is significantly enhanced. [Chen, ¶0008]
Claim 13 recites a method with the same limitation as claim 6 and rejected over O'Shea, Mital and Chen under the same rationale of rejection of claim 6.
Claim 20 recites a system with the same limitation as claim 6 and rejected over O'Shea, Mital and Chen under the same rationale of rejection of claim 6.
Claim(s) 7 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over O'Shea et al. [US 8,645,623 B1] in view of Mital et al. [US 2013/0091330 A1] in further view of Mevergnies et al. [US 2007/0277001 A1] and yet in further view of Chen. [US 2023/0120806 A1].
Claim 7 is rejected over O'Shea, Mital, Mevergnies and Chen.
The combination of O'Shea, Mital and Mevergnies does not explicitly teach wherein N is 64.
However, Chen teaches “wherein N is 64.” as “The operation above is performed in the number dimension N on each of the 64 pointwise convolution weights” [¶0032]
O'Shea, Mital, Mevergnies and Chen are analogous arts because they teach data storage system and cache management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of O'Shea, Mital, Mevergnies and Chen before him/her, to modify the teachings of combination of O'Shea, Mital and Mevergnies to include the teachings of Chen with the motivation of data transmissions between the internal memory and the external memory are reduced and convolution operation efficiency is significantly enhanced. [Chen, ¶0008]
Claim 14 recites a method with the same limitation as claim 7 and rejected over O'Shea, Mital, Mevergnies and Chen under the same rationale of rejection of claim 7.
Allowable Subject Matter
Claims 3, 10 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claims 3, 10 and 17 recite the following limitation: “wherein the evicted data is a counter.”
The prior arts of record do not appear to teach or fairly suggest that the evicted data is specifically is a counter value. Based on this rationale, claims 3, 10 and 17 are considered to contain allowable subject matter.
Claims 4-5, 11-12 and 18-19 are objected because they are dependent on already objected claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MASUD K KHAN whose telephone number is (571)270-0606. The examiner can normally be reached Monday-Friday (8am-5pm).
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/MASUD K KHAN/ Primary Examiner, Art Unit 2132
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