APPLICATION PROGRAMMING INTERFACE TO INDICATE STORAGE LOCATIONS

§101 §102 §103 §112

Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Examiner Notes Examiner cites particular columns and line numbers in the references as applied to the claims below for convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references cited in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. Response to Amendment The Amendment filed 1/29/2026 has been entered. Claims 1-20 remain pending in the present Office Action. The Amendments to the claims have been fully considered and are satisfactory to overcome all Objections set forth in the previous Office Action mailed 10/29/2025. The Amendments to the claims have been fully considered and are satisfactory to overcome the rejections of claims 1-20 under 35 U.S.C. 112(b) set forth in the previous Office Action mailed 10/29/2025. The Amendments to the claims have been fully considered and are satisfactory to overcome the rejections of claims 1-20 under 35 U.S.C. 101 set forth in the previous Office Action mailed 10/29/2025. Specification The use of the term Amazon Web Services, Google Cloud and Microsoft Azure, Fortran, Python, Java, and Bluetooth, which are trade names or marks used in commerce, has been noted in this application. The term should be accompanied by the generic terminology; furthermore the term should be capitalized wherever it appears or, where appropriate, include a proper symbol indicating use in commerce such as ™, SM , or ® following the term. Although the use of trade names and marks used in commerce (i.e., trademarks, service marks, certification marks, and collective marks) are permissible in patent applications, the proprietary nature of the marks should be respected and every effort made to prevent their use in any manner which might adversely affect their validity as commercial marks. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 1 recites the limitations “causes one or more storage locations of information to be mapped from a first tensor to a second tensor by modifying, in a data structure, an indication of a storage location for the second tensor based, at least in part, on an indication of a storage location for the first tensor”. In light of the Specification, the limitation “modifying, in a data structure, an indication of a storage location for the second tensor based, at least in part, on an indication of a storage location for the first tensor” appears to be describing replacing (“modifying”) an indication of a storage location (e.g., a memory address) for the second tensor in a tensor map (“a data structure”) with (“based, at least in part, on”) an indication of a storage location for the first tensor (see Specification [0081]). However, replacing an indication of a storage location for a second tensor with an indication of a storage location for a first tensor is causing one or more storage locations of information (e.g., the address of the other tensor involved in the tensor map) to be mapped in the direction from the second tensor to the first tensor, as the original tensor map indicated a mapping including an indication of a storage location for the second tensor, and after the claimed modification, the tensor map indicates a mapping including an indication of a storage location for the first tensor. Thus, “modifying in a data structure, an indication of a storage location for the second tensor based, at least in part, on an indication of a storage location for the first tensor” causes one or more storage locations of information to be mapped in the direction from the second tensor to the first tensor, which is the opposite direction of what is earlier recited in claim 1 (“causes one or more storage locations of information to be mapped from a first tensor to a second tensor”). Thus, it is unclear how the circuitry causes “one or more storage locations of information to be mapped from a first tensor to a second tensor” by “modifying, in a data structure, an indication of a storage location for the second tensor based, at least in part, on an indication of a storage location for the first tensor” as recited in claim 1, and the Specification fails to provide support for this particular combination of limitations. Claims 8 and 14 recite the same limitations, and are therefore rejected for the same reasons presented with respect to claim 1. Claims 2-7 depend from claim 1 and therefore inherit the same deficiencies of claim 1. Claims 9-13 depend from claim 8, and therefore inherit the same deficiencies of claim 8. Claims 15-20 depend from claim 14, and therefore inherit the same deficiencies of claim 8. The Applicant should point to specific teachings of the Specification which provide support for the combination of limitations identified or remove them from the claims. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitations “causes one or more storage locations of information to be mapped from a first tensor to a second tensor by modifying, in a data structure, an indication of a storage location for the second tensor based, at least in part, on an indication of a storage location for the first tensor”. In light of the Specification, the limitation “modifying, in a data structure, an indication of a storage location for the second tensor based, at least in part, on an indication of a storage location for the first tensor” appears to be describing replacing (“modifying”) an indication of a storage location (e.g., a memory address) for the second tensor in a tensor map (“a data structure”) with an indication of a storage location for the first tensor (see Specification [0081]). However, replacing an indication of a storage location for a second tensor with an indication of a storage location for a first tensor is causing one or more storage locations of information (e.g., the address of the other tensor involved in the tensor map) to be mapped in the direction from the second tensor to the first tensor, as the original tensor map before modification indicated a mapping including an indication of a storage location for the second tensor, and after the claimed modification, the tensor map indicates a mapping including an indication of a storage location for the first tensor. Thus, “modifying in a data structure, an indication of a storage location for the second tensor based, at least in part, on an indication of a storage location for the first tensor” causes one or more storage locations of information to be mapped in the direction from the second tensor to the first tensor, which is the opposite direction of what is earlier recited in claim 1 (“causes one or more storage locations of information to be mapped from a first tensor to a second tensor”). Thus, claim 1 is indefinite as it is unclear how the circuitry causes “one or more storage locations of information to be mapped from a first tensor to a second tensor” by “modifying, in a data structure, an indication of a storage location for the second tensor based, at least in part, on an indication of a storage location for the first tensor”. Claims 8 and 14 recite the same limitations, and are therefore rejected as being indefinite for the same reasons presented with respect to claim 1. Claims 2-7 depend from claim and therefore inherit the same deficiencies of claim 1. Claims 9-13 depend from claim 8, and therefore inherit the same deficiencies of claim 8. Claims 15-20 depend from claim 14, and therefore inherit the same deficiencies of claim 8. For clarity of the record, the Examiner has interpreted the combination of limitations to be reciting “causes one or more storage locations of information to be mapped from a second tensor to a first tensor by modifying, in a data structure, an indication of a storage location for the second tensor based, at least in part, on an indication of a storage location for the first tensor”. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 3-5, 8, 11-12, 14, 17 and 19-20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Liu et al. (U.S. Pub. No. 2021/0117806), hereinafter Liu. Regarding claim 1, Liu teaches One or more processors, comprising: circuitry (FIG 4C; [0100] – “a processor 432 that includes a program 434. The program includes tensor manipulation instructions. When executed, the program 434 requests tensor manipulation instruction circuits 436 to perform the requested tensor manipulation instructions. The tensor manipulation instructions include one or more of instructions for manipulating generic tensor raw data 306 and/or instructions for manipulating generic tensor descriptors 308.”; [0124] – “Suitable processors include, by way of example […] Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) circuits, any other type of integrated circuit (IC)”), wherein the circuitry, in response to an application programming interface (API) call ([0026] – “The individual operations are, in various implementations, performed by any of the following entities: […] hardware that performs the operations in response to an invocation such as an API call”; [0093] – “the operations are API functions that can be called by software. In some implementations, the operations are operations performed by a compiler at compile-time. In some implementations, the operations that act on the generic tensor descriptor are compile-time operations and the operations that act on the data itself are runtime operations. In various implementations, any of the operations are implemented as hardware instructions as part of an instruction set architecture or that is invoked in any technically feasible manner.”), causes one or more storage locations of information to be mapped from a first tensor to a second tensor ([0027] – “Some operations are operations that act not on the generic tensor raw data, itself, but instead on the generic tensor descriptor. Such operations include the following: slice, strided slice, reorder, unfold, merge, embed, pad, and move slicing window. As an example of these operations, the slice operator "slices out" a given portion of a tensor to make a new generic tensor descriptor. Specifically, a slice modifies a generic tensor descriptor by limiting the possible index values in one or more dimensions, but the slice does not operate on the tensor raw data. The range of possible indices index to which indexing is limited in the sliced tensor is called a "slicing window." The number of possible index values in the given dimension is called the "length of a slicing window" in that dimension. In the above example, one example slice limits the possible index values in the z dimension to 0 through 3 ( out of 0 through 7). A different example slice limits the possible index values in the x dimension to 0 and in the y dimension to 0 and 1.”; [0030] – “A generic tensor is described both by a generic tensor descriptor and generic tensor raw data. A generic tensor descriptor indicates the number of dimensions of the generic tensor, the lengths for each dimension, and a base address for the generic tensor raw data that the generic tensor descriptor is associated with. In addition, a generic tensor descriptor also provides a means to calculate the memory "offset" of a tensor raw data that is associated with a multi-index. Thus, a generic tensor descriptor indicates the manner in which a multi-index maps to generic tensor raw data as stored in memory. The generic tensor descriptor facilitates proper mapping of elements of a multi-index to elements of generic tensor raw data. […] With a generic tensor stored in memory, the point of origin corresponds to the base address of the generic tensor.”; [0033] – “The function g: X[Symbol font/0xAE]Y is referred to as the “address function” of the generic tensor T. The “generic tensor descriptor” of T is the implementation of the address function g: X[Symbol font/0xAE]Y. The address function maps the set of all tensor coordinates of a generic tensor T to the set of all memory addresses associated with the generic tensor T.” Operations performed in response to an API call may act on a generic tensor descriptor which includes a base address of the tensor raw data of a tensor (one storage location of information) and implements an address function which maps the tensor to the memory addresses (more storage locations) of the tensor raw data. [0038]-[0039] – “B is a generic tensor descriptor that maps tensor coordinate space W to memory space Y. More specifically, generic tensor descriptor B can be thought of as being constructed using generic tensor descriptor A, which maps coordinate space X to memory address space Y as g: X[Symbol font/0xAE]Y, and the function ƒ: W[Symbol font/0xAE]X that maps coordinate space W to X. The function g: X[Symbol font/0xAE]Y is the address function associated with the generic tensor descriptor A. The function (gοƒ): W[Symbol font/0xAE]Y is the address function associated with generic tensor descriptor B. The function ƒ: W[Symbol font/0xAE] X is referred to as a “transformation function” here, which transforms generic tensor descriptor A into B.”; [0080] – “A reorder (also called "permute") transformation operation changes the order of the dimensions of a generic tensor descriptor. […] A reorder operation creates a new generic tensor "TensorB" with a new order of dimensions, where, for example, z, y, and x are its first, second and third dimension. TensorB has lengths of Lz, Ly, and Lx, and strides of Sz, Sy, Sx on its first, second, and third dimension. "TensorA" and "TensorB" share the same tensor raw data in memory. An element of TensorA with multi-index of (Ix, Iy, Iz) has the same memory address as the element of TensorB with multi-index of (Iz, Iy, Ix).” Performing an operation on the generic tensor descriptor, e.g. slice or reorder, results in the tensor raw data (“information”) of a tensor represented by the original generic tensor descriptor (e.g. a second tensor), being mapped to a tensor according to the transformed/manipulated generic tensor descriptor (e.g. a first tensor). Thus, as best understood in light of the 112 rejections presented above, performing an operation on the generic tensor descriptor causes the storage locations of the raw tensor data to be mapped from the one tensor to another tensor, e.g. by changing the address function indicating how the storage locations of raw tensor data are mapped to the coordinate space of a tensor.) by modifying, in a data structure ([0027] – “Some operations are operations that act not on the generic tensor raw data, itself, but instead on the generic tensor descriptor. Such operations include the following: slice, […] Specifically, a slice modifies a generic tensor descriptor”; [0101] – “the generic tensor descriptors are stored at any appropriate location such as a memory”; [0120] – “The generic tensor descriptor is a construct that indicates how to obtain data elements of generic tensor raw data given an input multi-index.”), an indication of a storage location for the second tensor based, at least in part, on an indication of a storage location for the first tensor ([0033] – “The function g: X[Symbol font/0xAE]Y is referred to as the “address function” of the generic tensor T. The “generic tensor descriptor” of T is the implementation of the address function g: X[Symbol font/0xAE]Y. The address function maps the set of all tensor coordinates of a generic tensor T to the set of all memory addresses associated with the generic tensor T.”; [0038]-[0039] – “B is a generic tensor descriptor that maps tensor coordinate space W to memory space Y. More specifically, generic tensor descriptor B can be thought of as being constructed using generic tensor descriptor A, which maps coordinate space X to memory address space Y as g: X[Symbol font/0xAE]Y, and the function ƒ: W[Symbol font/0xAE]X that maps coordinate space W to X. The function g: X[Symbol font/0xAE]Y is the address function associated with the generic tensor descriptor A. The function (gοƒ): W[Symbol font/0xAE]Y is the address function associated with generic tensor descriptor B. The function ƒ: W[Symbol font/0xAE] X is referred to as a “transformation function” here, which transforms generic tensor descriptor A into B.”; [0047] – “any number of transformation functions can be chained and applied to an existing generic tensor descriptor to construct a series of new generic tensor descriptors. […] Since a generic tensor can be defined using tensor raw data and an address function, a series of generic tensors T1, …, Tk can be defined by combining these transformation functions with the address function g :   → x 0 → y for T0.”; [0078] – an example transformation function for a slice transformation is provided, which as described in [0027], modifies a generic tensor descriptor. The original tensor descriptor A (“a data structure” which includes an address function mapping from the coordinate space of original tensor A to the memory addresses of tensor raw data, i.e., “an indication of a storage location for the second tensor”) is modified to create a new address function for the generic tensor B (“an indication of a storage location for the first tensor”), which is the original address function combined with a transformation function f (a mapping of a second tensor A to a first tensor B).). Regarding claim 3, Liu teaches The one or more processors of claim 1, wherein data structure indicates a mapping of the first tensor to the second tensor ([0038]-[0039] – “B is a generic tensor descriptor that maps tensor coordinate space W to memory space Y. More specifically, generic tensor descriptor B can be thought of as being constructed using generic tensor descriptor A, which maps coordinate space X to memory address space Y as g: X[Symbol font/0xAE]Y, and the function ƒ: W[Symbol font/0xAE]X that maps coordinate space W to X. The function g: X[Symbol font/0xAE]Y is the address function associated with the generic tensor descriptor A. The function (gοƒ): W[Symbol font/0xAE]Y is the address function associated with generic tensor descriptor B. The function ƒ: W[Symbol font/0xAE] X is referred to as a “transformation function” here, which transforms generic tensor descriptor A into B.”; [0047] – “any number of transformation functions can be chained and applied to an existing generic tensor descriptor to construct a series of new generic tensor descriptors. […] Since a generic tensor can be defined using tensor raw data and an address function, a series of generic tensors T1, …, Tk can be defined by combining these transformation functions with the address function g :   → x 0 → y for T0.” The original tensor descriptor A (“a data structure” which includes an address function mapping from the coordinate space of original tensor A to the memory addresses of tensor raw data, i.e., “an indication of a storage location for the second tensor”) is modified to indicate a new address function for the generic tensor B (“an indication of a storage location for the first tensor”), which is based on the original address function combined with a transformation function ƒ: W[Symbol font/0xAE] X, where W is the coordinate space of tensor B (“the first tensor”) and X is the coordinate space of tensor A (“the second tensor”).). Regarding claim 4, Liu teaches The one or more processors of claim 1, wherein circuitry, in response to the API call, updates a mapping of a third tensor to the second tensor to a mapping of the first tensor to the second tensor ([0026]-[0027] – operations, e.g., operations on generic tensor descriptors, are performed in response to an API call; [0033] – “The address function maps the set of all tensor coordinates of a generic tensor T to the set of all memory addresses associated with the generic tensor T.”; [0047] – “any number of transformation functions can be chained an applied to an existing generic tensor descriptor to construct a series of new generic tensor descriptors. […] Since a generic tensor can be defined using tensor raw data and an address function, a series of generic tensors T1, …, Tk can be defined by combining these transformation functions with the address function g :   → x 0 → y for T0.”; [0051] – “Multiple transformations of any kind can be chained together and applied to any generic tensor descriptor to create a new generic tensor descriptor. The resulting generic tensor descriptor is associated with the same tensor raw data as the original tensor descriptor.” The address function of the original generic tensor descriptor is reused in defining any number of new tensors by combining the address function with any number of transformation functions. Thus, a first transformation could have been previously applied to the original generic tensor descriptor, causing a mapping of a third tensor to the second tensor, specifically to the raw tensor data of the second tensor, and a second transformation could be applied to the transformed generic tensor descriptor, causing a mapping of the first tensor (to the third tensor) to the second tensor, specifically to the raw tensor data of the second tensor.). Regarding claim 5, Liu further teaches The one or more processors of claim 1, wherein the circuitry, in response to the API call, reuses a mapping with a different set of tensors ([0033] – “The address function maps the set of all tensor coordinates of a generic tensor T to the set of all memory addresses associated with the generic tensor T.”; [0047] – “any number of transformation functions can be chained an applied to an existing generic tensor descriptor to construct a series of new generic tensor descriptors. […] Since a generic tensor can be defined using tensor raw data and an address function, a series of generic tensors T1, …, Tk can be defined by combining these transformation functions with the address function g :   → x 0 → y for T0.” The address function (a mapping) of the original generic tensor descriptor is reused in defining any number of new tensors by combining the address function with any number of transformation functions.). Regarding claim 8, Liu teaches A system, comprising: one or more processors (FIG. 1, processor 102) to implement the same functions of the circuits of the processor of claim 1. Thus, claim 8 is rejected as being anticipated by Liu for the same reasons presented with respect to claim 1. Claim 11 recites substantially the same limitations as claim 4. Thus, claim 11 is rejected as being anticipated by Liu for the same reasons presented with respect to claim 4. Claim 12 recites substantially the same limitations as claim 5. Thus, claim 12 is rejected as being anticipated by Liu for the same reasons presented with respect to claim 5. Claim 14 is directed to A method comprising the operations performs by the circuits of the processor of claim 1. Thus, claim 14 is rejected as being anticipated by Liu for the same reasons presented with respect to claim 1. Regarding claim 17, Liu teaches The method of claim 14, wherein the data structure comprises a tensor map, and modifying the indication of the storage location for the second tensor comprises updating the tensor map ([0027] – “Some operations are operations that act not on the generic tensor raw data, itself, but instead on the generic tensor descriptor. Such operations include the following: slice, strided slice, reorder, unfold, merge, embed, pad, and move slicing window. As an example of these operations, the slice operator "slices out" a given portion of a tensor to make a new generic tensor descriptor. Specifically, a slice modifies a generic tensor descriptor”; [0030] – “a generic tensor descriptor indicates the manner in which a multi-index maps to generic tensor raw data as stored in memory. The generic tensor descriptor facilitates proper mapping of elements of a multi-index to elements of generic tensor raw data. Indicating the generic tensor type also indicates the manner in which the multi-index of the generic tensor descriptor maps to the generic tensor raw data. […] With a generic tensor stored in memory, the point of origin corresponds to the base address of the generic tensor.”; [0033] – “The function g: X[Symbol font/0xAE]Y is referred to as the “address function” of the generic tensor T. The “generic tensor descriptor” of T is the implementation of the address function g: X[Symbol font/0xAE]Y. The address function maps the set of all tensor coordinates of a generic tensor T to the set of all memory addresses associated with the generic tensor T.”; [0038]-[0039] – “B is a generic tensor descriptor that maps tensor coordinate space W to memory space Y. More specifically, generic tensor descriptor B can be thought of as being constructed using generic tensor descriptor A, which maps coordinate space X to memory address space Y as g: X[Symbol font/0xAE]Y, and the function ƒ: W[Symbol font/0xAE]X that maps coordinate space W to X. The function g: X[Symbol font/0xAE]Y is the address function associated with the generic tensor descriptor A. The function (gοƒ): W[Symbol font/0xAE]Y is the address function associated with generic tensor descriptor B. The function ƒ: W[Symbol font/0xAE] X is referred to as a “transformation function” here, which transforms generic tensor descriptor A into B.”; [0047] – “any number of transformation functions can be chained and applied to an existing generic tensor descriptor to construct a series of new generic tensor descriptors. […] Since a generic tensor can be defined using tensor raw data and an address function, a series of generic tensors T1, …, Tk can be defined by combining these transformation functions with the address function g :   → x 0 → y for T0.”). Regarding claim 19, Liu teaches The method of claim 14, wherein the data structure stores information indicating how to transform the first tensor to obtain the second tensor ([0038]-[0039] – “B is a generic tensor descriptor that maps tensor coordinate space W to memory space Y. More specifically, generic tensor descriptor B can be thought of as being constructed using generic tensor descriptor A, which maps coordinate space X to memory address space Y as g: X[Symbol font/0xAE]Y, and the function ƒ: W[Symbol font/0xAE]X that maps coordinate space W to X. The function g: X[Symbol font/0xAE]Y is the address function associated with the generic tensor descriptor A. The function (gοƒ): W[Symbol font/0xAE]Y is the address function associated with generic tensor descriptor B. The function ƒ: W[Symbol font/0xAE] X is referred to as a “transformation function” here, which transforms generic tensor descriptor A into B.”; [0047] – “any number of transformation functions can be chained and applied to an existing generic tensor descriptor to construct a series of new generic tensor descriptors. […] Since a generic tensor can be defined using tensor raw data and an address function, a series of generic tensors T1, …, Tk can be defined by combining these transformation functions with the address function g :   → x 0 → y for T0.” The original tensor descriptor A (“a data structure” which includes an address function mapping from the coordinate space of original tensor A to the memory addresses of tensor raw data, i.e., “an indication of a storage location for the second tensor”) is modified to indicate a new address function for the generic tensor B (“an indication of a storage location for the first tensor”), which is based on the original address function combined with a transformation function ƒ: W[Symbol font/0xAE] X, where W is the coordinate space of tensor B (“the first tensor”) and X is the coordinate space of tensor A (“the second tensor”), where the transformation function is “information indicating how to transform the first tensor to obtain the second tensor”.). Regarding claim 20, Liu teaches A non-transitory computer-readable medium having stored thereon a set of instructions, which if performed by one or more processors, cause the one or more processors to at least perform the method ([0124] – “The various functional units illustrated in the figures and/or described herein […] are, in various implementations, implemented as […] a program, software, or firmware, stored in a non-transitory computer readable medium or in another medium, executable by a general purpose computer, a processor, or a processor core.”). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 2, 7, 9-10, 16, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Liu et al. (U.S. Pub. No. 2021/0334105), hereinafter referred to by the Applicant CAMBRICON. Regarding claim 2, Liu teaches The one or more processors of claim 1, wherein the circuitry, in response to the API call, [modifies], in the data structure, the indication of the storage location for the second tensor with the indication of the storage location for the first tensor ([0026]-[0027] – “performs the operations in response to an invocation such as an API call […] Some operations are operations that act not on the generic tensor raw data, itself, but instead on the generic tensor descriptor. Such operations include the following: slice, strided slice, reorder, unfold, merge, embed, pad, and move slicing window. As an example of these operations, the slice operator "slices out" a given portion of a tensor to make a new generic tensor descriptor. Specifically, a slice modifies a generic tensor descriptor”; [0038]-[0039] – “B is a generic tensor descriptor that maps tensor coordinate space W to memory space Y. More specifically, generic tensor descriptor B can be thought of as being constructed using generic tensor descriptor A, which maps coordinate space X to memory address space Y as g: X[Symbol font/0xAE]Y, and the function ƒ: W[Symbol font/0xAE]X that maps coordinate space W to X. The function g: X[Symbol font/0xAE]Y is the address function associated with the generic tensor descriptor A. The function (gοƒ): W[Symbol font/0xAE]Y is the address function associated with generic tensor descriptor B. The function ƒ: W[Symbol font/0xAE] X is referred to as a “transformation function” here, which transforms generic tensor descriptor A into B.”; [0047] – “any number of transformation functions can be chained and applied to an existing generic tensor descriptor to construct a series of new generic tensor descriptors. […] Since a generic tensor can be defined using tensor raw data and an address function, a series of generic tensors T1, …, Tk can be defined by combining these transformation functions with the address function g :   → x 0 → y for T0.”; [0078] – an example transformation function for a slice transformation is provided, which as described in [0027], modifies a generic tensor descriptor. The original tensor descriptor A (“a data structure” which includes an address function mapping from the coordinate space of original tensor A to the memory addresses of tensor raw data, i.e., “an indication of a storage location for the second tensor”) is modified to create a new address function for the generic tensor B (“an indication of a storage location for the first tensor”), which is the original address function combined with a transformation function f (a mapping of a second tensor A to a first tensor B).). Liu fails to expressly teach the circuitry replaces, in the data structure, the indication of the storage location. However, CAMBRICON teaches the circuitry replaces, in the data structure, an indication of a storage location of a tensor ([0048] – “the descriptor may include an identifier and content. The identifier of the descriptor may be used to distinguish the descriptor from other descriptors. For example, the identifier may be an index. The content of the descriptor may include at least one shape parameter (such as a size of each dimension of the tensor, etc.) representing the shape of the tensor data, and may also include at least one address parameter (such as a base address of a datum point) representing an address of the tensor data. The present disclosure does not limit the specific parameters included in the content of the descriptor. By using the descriptor to indicate the shape of tensor data, related information such as the relationship among a plurality of pieces of tensor data can be determined, so as to improve the access efficiency of tensor data”; [0089] – “the first processor may modify the existing descriptor rather than generating a new one. For example, the first processor may modify the descriptor of the tensor data to be synchronized to indicate the new address of the tensor data in the shared storage space.”). Liu and CAMBRICON are considered to be analogous art to the claimed invention because they are reasonably pertinent to the problem faced by the inventor of using a tensor map indicating one or more storage locations of tensors to efficiently access tensor data. Therefore, it would have been obvious to one of ordinary skill in the art to have modified the teachings of Liu, specifically the teachings of modifying, in a data structure (e.g., a tensor descriptor), an indication of a storage location for the second tensor with an indication of a storage location for the first tensor, to incorporate the teachings of CAMBRICON such that the modification involves replacing the indication of the storage location for the second tensor with the indication of a storage location for the first tensor in the data structure. Reusing a tensor descriptor, e.g. by replacing the indication of the storage location within the data structure instead of generating a new descriptor, would more efficiently utilize resources which store the generic tensor descriptors (see CAMBRICON: [0089] and [0091]). Regarding claim 7, Liu teaches The one or more processors of claim 1, wherein circuitry, in response to the API call, [modifies] the data structure ([0026]-[0027] – “performs the operations in response to an invocation such as an API call […] Some operations are operations that act not on the generic tensor raw data, itself, but instead on the generic tensor descriptor. Such operations include the following: slice, strided slice, reorder, unfold, merge, embed, pad, and move slicing window. As an example of these operations, the slice operator "slices out" a given portion of a tensor to make a new generic tensor descriptor. Specifically, a slice modifies a generic tensor descriptor”; [0088] – “The following operations act on the actual tensor raw data itself-that is, the following operations act on the data in generic tensor raw data”; [0092] – “For any of the above operations, the resulting tensor is written into any memory, including memories that are different than the memory from which the operand tensors originated”; [0120] – “The generic tensor descriptor is a construct that indicates how to obtain data elements of generic tensor raw data given an input multi-index.”). Liu fails to expressly teach the circuitry replaces a first memory address with a second memory address in the data structure. However, CAMBRICON teaches the circuitry replaces a first memory address with a second memory address in the data structure ([0048] – “the descriptor may include an identifier and content. The identifier of the descriptor may be used to distinguish the descriptor from other descriptors. For example, the identifier may be an index. The content of the descriptor may include at least one shape parameter (such as a size of each dimension of the tensor, etc.) representing the shape of the tensor data, and may also include at least one address parameter (such as a base address of a datum point) representing an address of the tensor data. The present disclosure does not limit the specific parameters included in the content of the descriptor. By using the descriptor to indicate the shape of tensor data, related information such as the relationship among a plurality of pieces of tensor data can be determined, so as to improve the access efficiency of tensor data”; [0089] – “the first processor may modify the existing descriptor rather than generating a new one. For example, the first processor may modify the descriptor of the tensor data to be synchronized to indicate the new address of the tensor data”). Liu and CAMBRICON are considered to be analogous art to the claimed invention because they are reasonably pertinent to the problem faced by the inventor of using a tensor map indicating one or more storage locations of tensors to efficiently access tensor data. Therefore, it would have been obvious to one of ordinary skill in the art to have modified the teachings of Liu, specifically the teachings of modifying, in a data structure (e.g., a tensor descriptor), an indication of a storage location for the second tensor with an indication of a storage location for the first tensor, to incorporate the teachings of CAMBRICON such that the modification involves replacing the indication of the storage location, e.g. a memory address, for the second tensor with the indication of a storage location for the first tensor in the data structure. Reusing a tensor descriptor, e.g. by replacing an indication of a memory address within the data structure instead of generating a new descriptor, would more efficiently utilize resources which store the generic tensor descriptors and access the tensor data (see CAMBRICON: [0048], [0089] and [0091]). Claim 9 recites substantially the same limitations as claim 2. Thus, claim 9 is rejected as being unpatentable over Liu in view of CAMBRICON for the same reasons presented with respect to claim 2. Regarding claim 10, Liu teaches The system of claim 8, wherein the one or more processors, in response to the API call, modify the data structure to [update] a first [indication of a storage location] of a third tensor with a [indication of a storage location] of the first tensor ([0026]-[0027] – operations, e.g., operations on generic tensor descriptors, are performed in response to an API call; [0033] – “The address function maps the set of all tensor coordinates of a generic tensor T to the set of all memory addresses associated with the generic tensor T.”; [0047] – “any number of transformation functions can be chained an applied to an existing generic tensor descriptor to construct a series of new generic tensor descriptors. […] Since a generic tensor can be defined using tensor raw data and an address function, a series of generic tensors T1, …, Tk can be defined by combining these transformation functions with the address function g :   → x 0 → y for T0.”; [0051] – “Multiple transformations of any kind can be chained together and applied to any generic tensor descriptor to create a new generic tensor descriptor. The resulting generic tensor descriptor is associated with the same tensor raw data as the original tensor descriptor.” The address function (an “indication of a storage location”) of the original generic tensor descriptor is reused in defining any number of new tensors by combining the address function with any number of transformation functions, e.g., to generate a new address function. Thus, a first transformation could have been previously applied to the original generic tensor descriptor, causing a mapping of a third tensor to the raw tensor data of the second tensor using the original address function combined with a first transformation function (“a first indication of a storage location of a third tensor”), and a second transformation could be applied to the transformed generic tensor descriptor, causing a mapping of the first tensor (to the third tensor) to the raw tensor data of the second tensor using the original address function combined with the first transformation function, and further combined with the second transformation function (“an indication of a storage location of the first tensor”).). Liu fails to expressly teach modifying the data structure to replaces a first memory address of a third tensor with a memory address of the first tensor. However, CAMBRICON teaches modifying the data structure to replaces a first memory address of a third tensor with a memory address of the first tensor ([0048] – “the descriptor may include an identifier and content. The identifier of the descriptor may be used to distinguish the descriptor from other descriptors. For example, the identifier may be an index. The content of the descriptor may include at least one shape parameter (such as a size of each dimension of the tensor, etc.) representing the shape of the tensor data, and may also include at least one address parameter (such as a base address of a datum point) representing an address of the tensor data. The present disclosure does not limit the specific parameters included in the content of the descriptor. By using the descriptor to indicate the shape of tensor data, related information such as the relationship among a plurality of pieces of tensor data can be determined, so as to improve the access efficiency of tensor data”; [0089] – “the first processor may modify the existing descriptor rather than generating a new one. For example, the first processor may modify the descriptor of the tensor data to be synchronized to indicate the new address of the tensor data in the shared storage space.” The tensor data stored in different memories/memory addresses could be considered different tensors, e.g. a first tensor at the new address and a third tensor at the original address.). Liu and CAMBRICON are considered to be analogous art to the claimed invention because they are reasonably pertinent to the problem faced by the inventor of using a tensor map indicating one or more storage locations of tensors to efficiently access tensor data. Therefore, it would have been obvious to one of ordinary skill in the art to have modified the teachings of Liu, specifically the teachings of modifying in a data structure (e.g., a tensor descriptor), an indication of a storage location of a third tensor with an indication of a storage location for the first tensor, to incorporate the teachings of CAMBRICON such that the modification involves replacing a memory address of the third tensor with a memory address of the first tensor in the data structure. Reusing a tensor descriptor, e.g. by replacing the memory addresses within the data structure instead of generating a new descriptor, would more efficiently utilize resources which store the generic tensor descriptors (see CAMBRICON: [0089] and [0091]). Claim 16 recites substantially the same limitations as claim 2. Thus, claim 16 is rejected as being unpatentable over Liu in view of CAMBRICON for the same reasons presented with respect to claim 2. Regarding claim 18, Liu teaches The method of claim 14, wherein causing the one or more storage locations to be mapped from the first tensor to the second tensor comprises [modifying] at least a portion of the indication of the storage location for the second tensor ([0026]-[0027] – “performs the operations in response to an invocation such as an API call […] Some operations are operations that act not on the generic tensor raw data, itself, but instead on the generic tensor descriptor. Such operations include the following: slice, strided slice, reorder, unfold, merge, embed, pad, and move slicing window. As an example of these operations, the slice operator "slices out" a given portion of a tensor to make a new generic tensor descriptor. Specifically, a slice modifies a generic tensor descriptor”; [0038]-[0039] – “B is a generic tensor descriptor that maps tensor coordinate space W to memory space Y. More specifically, generic tensor descriptor B can be thought of as being constructed using generic tensor descriptor A, which maps coordinate space X to memory address space Y as g: X[Symbol font/0xAE]Y, and the function ƒ: W[Symbol font/0xAE]X that maps coordinate space W to X. The function g: X[Symbol font/0xAE]Y is the address function associated with the generic tensor descriptor A. The function (gοƒ): W[Symbol font/0xAE]Y is the address function associated with generic tensor descriptor B. The function ƒ: W[Symbol font/0xAE] X is referred to as a “transformation function” here, which transforms generic tensor descriptor A into B.”; [0047] – “any number of transformation functions can be chained and applied to an existing generic tensor descriptor to construct a series of new generic tensor descriptors. […] Since a generic tensor can be defined using tensor raw data and an address function, a series of generic tensors T1, …, Tk can be defined by combining these transformation functions with the address function g :   → x 0 → y for T0.”; [0078] – an example transformation function for a slice transformation is provided, which as described in [0027], modifies a generic tensor descriptor; [0101] – the generic tensor descriptors are written in memory. The original tensor descriptor A (“a data structure” which includes an address function mapping from the coordinate space of original tensor A to the memory addresses of tensor raw data, i.e., “an indication of a storage location for the second tensor”) is modified to create a new address function for the generic tensor B (“an indication of a storage location for the first tensor”), which is the original address function combined with a transformation function f (a mapping of a second tensor A to a first tensor B).). Liu fails to expressly teach overwriting at least a portion of the indication of the storage location for the second tensor. However, CAMBRICON teaches overwriting at least a portion of the indication of the storage location for the second tensor ([0048] – “the descriptor may include an identifier and content. The identifier of the descriptor may be used to distinguish the descriptor from other descriptors. For example, the identifier may be an index. The content of the descriptor may include at least one shape parameter (such as a size of each dimension of the tensor, etc.) representing the shape of the tensor data, and may also include at least one address parameter (such as a base address of a datum point) representing an address of the tensor data. The present disclosure does not limit the specific parameters included in the content of the descriptor. By using the descriptor to indicate the shape of tensor data, related information such as the relationship among a plurality of pieces of tensor data can be determined, so as to improve the access efficiency of tensor data”; [0089] – “the first processor may modify the existing descriptor rather than generating a new one. For example, the first processor may modify the descriptor of the tensor data to be synchronized to indicate the new address of the tensor data in the shared storage space.”). Liu and CAMBRICON are considered to be analogous art to the claimed invention because they are reasonably pertinent to the problem faced by the inventor of using a tensor map indicating one or more storage locations of tensors to efficiently access tensor data. Therefore, it would have been obvious to one of ordinary skill in the art to have modified the teachings of Liu, specifically the teachings of modifying, in a data structure (e.g., a tensor descriptor), an indication of a storage location for the second tensor with an indication of a storage location for the first tensor, to incorporate the teachings of CAMBRICON such that the modification involves replacing the indication of the storage location for the second tensor with the indication of a storage location for the first tensor in the data structure. Reusing a tensor descriptor, e.g. by overwriting at least a portion of the indication of the storage location within the data structure instead of generating a new descriptor, would more efficiently utilize resources which store the generic tensor descriptors (see CAMBRICON: [0089] and [0091]). Claims 6, 13, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Cortuk (NPL Document: “C++ Pointers”). Regarding claim 6, Liu teaches The one or more processors of claim 1, wherein the circuitry, in response to the API call, receives as input […] a mapping between tensors is stored (FIG. 3 – tensor manipulator 304 receives a tensor manipulation request as input, i.e., the request for manipulation of a generic tensor descriptor, and necessarily the generic tensor descriptor to be manipulated, is indicated to the tensor manipulator 304; [0013] – “receiving a first request to perform a first operation on a generic tensor descriptor associated with the generic tensor”; [0026]-[0027] – “performs the operations in response to an invocation such as an API call […] Some operations are operations that act not on the generic tensor raw data, itself, but instead on the generic tensor descriptor. […] Specifically, a slice modifies a generic tensor descriptor”; [0030] – a generic tensor descriptor holds a plurality of data elements used for mapping elements of a tensor; [0101] – “the generic tensor descriptors are stored at any appropriate location such as a memory”; [0120] – “The generic tensor descriptor is a construct that indicates how to obtain data elements of generic tensor raw data given an input multi-index”). Liu does not expressly teach at least one indication of a storage location in which the data structure containing the mapping is stored. However, Cortuk teaches at least one indication of a storage location in which a data structure is stored (Pages 1-2 - “Pointers are extremely important, which allows us to access addresses and manipulate their contents. […] First of all, if we want to understand pointers, we must first know how data is stored on the computer. Each variable we create in our program is assigned a location in the computer’s memory. A computer memory location has an address and holds a content. […] A pointer is a variable that holds the address of another variable. That’s to say, unlike normal variable which stores a value(such as int, a double, a char), a pointer stores a memory address. It is known as a locator or indicator”; Page 8 – “Pointer is used with data structures”). Liu and Cortuk are considered to be analogous art to the claimed invention because they are reasonably pertinent to the problem faced by the inventor of efficiently accessing data, e.g., tensor data, stored in memory. Therefore, it would have been obvious to one of ordinary skill in the art to have modified the data structure containing the mapping (the “generic tensor descriptor”) to be updated that is stored in memory as taught by Liu such that a pointer indicating the memory location of the data structure is used to indicate the data structure as taught by Cortuk. Using pointers provides a plurality of benefits including enabling runtime-sized/resizable data structures, more efficient passing of the data structure, and more efficient use of and access to memory (see Cortuk: Pages 7-8). Regarding claim 13, Liu teaches The system of claim 8, wherein one or more processors, in response to the API call, indicate […] a mapping to be updated (FIG. 3 – tensor manipulator 304 receives a tensor manipulation request as input, i.e., the request for manipulation of a generic tensor descriptor, and necessarily the generic tensor descriptor to be manipulated, is indicated to the tensor manipulator 304; [0013] – “receiving a first request to perform a first operation on a generic tensor descriptor associated with the generic tensor”; [0026]-[0027] – “performs the operations in response to an invocation such as an API call […] Some operations are operations that act not on the generic tensor raw data, itself, but instead on the generic tensor descriptor. […] Specifically, a slice modifies a generic tensor descriptor”; [0030] – a generic tensor descriptor holds a plurality of data elements used for mapping elements of a tensor; [0101] – “the generic tensor descriptors are stored at any appropriate location such as a memory”; [0120] – “The generic tensor descriptor is a construct that indicates how to obtain data elements of generic tensor raw data given an input multi-index”). Liu does not expressly teach a memory location of the data structure containing the mapping is indicated. However, Cortuk teaches a memory location of a data structure is indicated (Page 2 - “A pointer is a variable that holds the address of another variable. That’s to say, unlike normal variable which stores a value(such as int, a double, a char), a pointer stores a memory address. It is known as a locator or indicator”; Page 8 – “Pointer is used with data structures”). Liu and Cortuk are considered to be analogous art to the claimed invention because they are reasonably pertinent to the problem faced by the inventor of efficiently accessing data, e.g., tensor data, stored in memory. Therefore, it would have been obvious to one of ordinary skill in the art to have modified the data structure containing the mapping (the “generic tensor descriptor”) to be updated that is stored in memory as taught by Liu such that a pointer indicating the memory location of the data structure is used to indicate the data structure as taught by Cortuk. Using pointers provides a plurality of benefits including enabling runtime-sized/resizable data structures, more efficient passing of the data structure, and more efficient use of and access to memory (see Cortuk: Pages 7-8). Regarding claim 15, Liu teaches The method of claim 14, wherein, in response to the API call, the method receives as input […] the data structure (FIG. 3 – tensor manipulator 304 receives a tensor manipulation request as input; [0013] – “receiving a first request to perform a first operation on a generic tensor descriptor associated with the generic tensor”; [0030] – a generic tensor descriptor holds a plurality of data elements; [0101] – “the generic tensor descriptors are stored at any appropriate location such as a memory”; [0120] – “The generic tensor descriptor is a construct that indicates how to obtain data elements of generic tensor raw data given an input multi-index”). Liu does not expressly teach a pointer to the data structure. However, Cortuk teaches a pointer to a data structure (Page 2 - “A pointer is a variable that holds the address of another variable. That’s to say, unlike normal variable which stores a value(such as int, a double, a char), a pointer stores a memory address.”; Page 8 – “Pointer is used with data structures”). Liu and Cortuk are considered to be analogous art to the claimed invention because they are reasonably pertinent to the problem faced by the inventor of efficiently accessing data, e.g., tensor data, stored in memory. Therefore, it would have been obvious to one of ordinary skill in the art to have modified the data structure taught by Liu such that a pointer to the data structure is used to indicate the data structure as taught by Cortuk. Using pointers provides a plurality of benefits including enabling runtime-sized/resizable data structures, and more efficient use of and access to memory (see Cortuk: Pages 7-8). Response to Arguments Applicant’s arguments, see pages 7-11 of the Remarks, filed 1/29/2026, with respect to the rejections of claims 1-20 under 35 U.S.C. 101 have been fully considered and are persuasive. The rejections of claims 1-20 under 35 U.S.C. 101 has been withdrawn. Specifically, at least claims 1, 8 and 15 have been amended such that no limitation recited is considered to be a mental process. Further, Applicant’s arguments with respect to Step 2A, Prong Two, see pages 9-10 of the Remarks are considered to be persuasive, as the claim limitations recited provide a technological improvement one of ordinary skill in the art would recognize in light of the Specification. Applicant's arguments, see pages 11-14 of the Remarks filed 1/29/2026, with respect to the rejection of claim 1 as being unpatentable over Liu in view Yu have been fully considered but they are not persuasive. Regarding Applicant’s arguments “Paragraph [0027] of Liu describes descriptor-based indexing and traversal of elements within a tensor, rather than mapping storage locations between distinct tensors” and “Instead, the API' s functions, described in the cited portions of Liu, alter how elements of a tensor are addressed or traversed in memory (e.g., via descriptor-defined indexing or transformations) within a single tensor's storage, rather than mapping storage locations of one tensor to storage locations of another tensor”: The claims do not recite “mapping storage locations of one tensor to storage locations of another tensor” as the Applicant is arguing. Regarding storage locations that are mapped, the claims recite the circuitry “causes one or more storage locations of information to be mapped from a first tensor to a second tensor” which requires only one storage location to be mapped and does not even require the one or more storage locations are storing tensors, only that they are storing “information”. Regarding the limitations added in the amendment, “modifying, in a data structure, an indication of a storage location for the second tensor based, at least in part, on an indication of a storage location for the first tensor”, this limitation does not require that the storage location for the second tensor is different/distinct from the storage location for the first tensor. At best, this limitation added in the amendment requires that an “indication of” a storage location for the second tensor may be different from an “indication of” a storage location of the first tensor, as the indication for the second tensor is modified based on the indication for the first tensor. Modifying a generic tensor descriptor which includes an address function (“an indication of a storage location” of a tensor) that maps the coordinate space of an original tensor to the storage locations of the data of the tensor, by combining a transformation function with the address function to generate a new generic tensor descriptor (comprising a new address function that is the combination of the original address function and the transformation function) indicating a new tensor that maps a different coordinate space (i.e., of the new tensor) to the storage locations of the data of the tensor, as taught by Liu (see [0030], [0032]-[0033], [0038]-[0041] and [0047]), is considered to be causing one or more storage locations to be mapped from a first tensor to a second tensor. A generic tensor as described in Liu is not just described by its raw data, but is also described by the generic tensor descriptor (see [0030]). An example modification of a generic tensor descriptor is a slice operation, which limits the number possible index values of a dimension of a tensor (see [0027]). For example, a slice operation on the generic tensor descriptor could reduce the possible index values in a z-dimension of a tensor from 0 through 7 to 0 through 3 (see Liu: [0027]). Thus, the original tensor would have a z-dimension of length 8, and the new tensor after the modification of the generic tensor descriptor would only have a z-dimension of length 4. Thus, the original tensor and new tensor after this modification of the generic tensor descriptor are distinct, at least because they have differing sizes. With respect to Liu, Applicant broadly alleges Liu fails to teach the circuitry, in response to an API call, "causes one or more storage locations of information to be mapped from a first tensor to a second tensor" by "modifying, in a data structure, an indication of a storage location for the second tensor based, at least in part, on an indication of a storage location for the first tensor" as now recited by the amended claims. Please refer to the rejection of claim 1 above in the section titled Claim Rejections - 35 USC § 102 regarding how Liu teaches the newly recited amendments. Applicant’s arguments regarding the use of Yu (see pages 13-14 of the Remarks) are moot, as Yu is not relied upon to teach any portion of amended claim 1. Specifically, Applicant’s amendments to claim 1 removed the limitations which Yu had been previously relied upon to teach. Applicant does not present any additional arguments with respect to claims 2-20. Accordingly, Examiner’s response with respect to claim 1 applies to claims 2-20 as well. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Liu et al. (U.S. Pub. No. 2022/0019439) teaches instructions to associated with a neural network include an operand identifying a tensor descriptor, wherein a descriptor storage space corresponding to the descriptor is determined according to an identifier of the descriptor, and content of the descriptor is modified in the storage space, where the content to be modified may be a shape of the corresponding tensor (see (see Abstract, [0056]-[0057], [0083], and [0125]-[0128]). Khatamifard et al. (U.S. Pub. No. 2023/0394276) teaches a task descriptor for a convolution operation of a neural network including pointers to data used in a task, such as an address of an input tensor in memory, and the pointer may be updated to indicate an address of an output tensor in memory ([0089]-[0091]). Kothamasu et al. (U.S. Pub. No. 2013/0290582) teaches an address swapping module receives an address per the system address map and generates a swapped address (see [0041]). Li et al. (U.S. Pub. No. 2022/0253488) teaches a tensor memory stores tensor data and objects, where a tensor is an object that includes data and a description of data such as the shape, where an original tensor object may be reused as the output tensor of a second operation to enable reuse of the memory backing the tensor (see [0032]). Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JENNIFER MARIE GUTMAN whose telephone number is (703)756-1572. The examiner can normally be reached M-F: 8:00 am - 4:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JENNIFER MARIE GUTMAN/Examiner, Art Unit 2194 /KEVIN L YOUNG/Supervisory Patent Examiner, Art Unit 2194