Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The instant detailed action is in response to Applicant's submission filed on 15 July 2026.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1,9,17,21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Applicant Admitted Prior Art (AAPA) in view of Kilmer (US PG PUB No. 2015/0179285) and Bland (US PG PUB No. 2010/0293410).
As per claim 1, AAPA discloses an apparatus, comprising:
a memory chip stack comprising memory chips separately having a first plurality of memory channels (see AAPA Specification FIG 2: 201 and [0015]),
However, AAPA does not expressly disclose but in the same field of endeavor Kilmer discloses
where, non-yielding ones of the memory channels separately included in the memory chips are to be disabled during operation of the memory chip stack (see Kilmer (Kilmer FIG 5: 518 and [0046]),
It would have been obvious before the effective filing date of the invention to further disable non-yielding ones of the memory channels as taught by Kilmer.
The suggestion/motivation for doing so would have been for the benefit of preventing errors due to defective connections (see Kilmer [0046]).
Therefore it would have been obvious before the effective filing date of the invention to disable non-yielding ones of the memory channels for the benefit of preventing errors to arrive at the invention as specified in the claims.
However, AAPA does not expressly disclose but in the same field of endeavor Bland discloses
wherein, the first plurality of memory channels have a second plurality of memory banks, where non-yielding ones of the memory banks within yielding ones of the memory channels are to be disabled during the operation of the memory chip stack (see Bland FIG 2: 206 and [0028] and [0035]) .
It would have been obvious before the effective filing date of the invention to disable the non-yielding banks as taught by Bland.
The suggestion/motivation for doing so would have been for the benefit of defect management (see Bland [0024]: “a defective DIMM of a particular channel in the computer memory subsystem (101); and disabling the defective DIMM, including enabling ODT for the defective DIMM without disabling any non-defective DIMMs.”).
Therefore it would have been obvious before the effective filing date of the invention to disable non-yielding ones of the banks as suggesting by Bland for the benefit of defect management to arrive at the invention as specified in the claims.
As per claim [9,17,21], AAPA discloses an apparatus, comprising:
a memory chip stack comprising memory chips separately having a first plurality of memory channels (see AAPA Specification FIG 2: 201 and [0015]),
a logic chip, the memory chip stack mounted to the logic chip (see AAPA Specification FIG 2: 202),
the logic chip comprising a decoder with interleaving circuitry, the interleaving circuitry to implement memory address interleaving (see AAPA Specification [0010]).
However, AAPA does not expressly disclose but in the same field of endeavor Kilmer discloses circuitry that does not map host addresses to non-yielding ones of the memory channels separately included in the memory chips,
where, non-yielding ones of the memory channels separately included in the memory chips are to be disabled during operation of the memory chip stack (see Kilmer (Kilmer FIG 5: 518 and [0046]),
It would have been obvious before the effective filing date of the invention to further disable non-yielding ones of the memory channels as taught by Kilmer.
The suggestion/motivation for doing so would have been for the benefit of preventing errors due to defective connections (see Kilmer [0046]).
Therefore it would have been obvious before the effective filing date of the invention to disable non-yielding ones of the memory channels for the benefit of preventing errors to arrive at the invention as specified in the claims.
However, AAPA does not expressly disclose but in the same field of endeavor Bland discloses circuitry that does not map host addresses to non-yielding ones of the memory banks,
wherein, the first plurality of memory channels have a second plurality of memory banks, where, non-yielding ones of the memory banks within yielding ones of the memory channels are to be disabled during the operation of the memory chip stack (see Bland FIG 2: 206 and [0028] and [0035]); and
It would have been obvious before the effective filing date of the invention to disable the non-yielding banks as taught by Bland.
The suggestion/motivation for doing so would have been for the benefit of defect management (see Bland [0024]: “a defective DIMM of a particular channel in the computer memory subsystem (101); and disabling the defective DIMM, including enabling ODT for the defective DIMM without disabling any non-defective DIMMs.”).
Therefore it would have been obvious before the effective filing date of the invention to disable non-yielding ones of the banks as suggesting by Bland for the benefit of defect management to arrive at the invention as specified in the claims.
Claim 1,5-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US PG PUB No. 2018/0137005) in view of Kilmer (US PG PUB No. 2015/0179285) and Bland (US PG PUB No. 2010/0293410).
As per claim 1, Wu discloses an apparatus, comprising:
a memory chip stack (see Wu [0097]: “As a multi-device memory , memory resources 760 can include multiple individual memory dies stacked vertically or in one or more vertical stacks” ) comprising memory chips separately having a first plurality of memory channels (see Wu [0089]: “Memory resources 760 can be organized as separate channels , ranks , and banks of memory”),
[Wu discloses the memory resources may be organized as separate channels (see Wu [0097]).]
However, Wu does not expressly disclose but in the same field of endeavor Kilmer discloses
where, non-yielding ones of the memory channels separately included in the memory chips are to be disabled during operation of the memory chip stack (see Kilmer (Kilmer FIG 5: 518 and [0046]),
It would have been obvious before the effective filing date of the invention to further disable non-yielding ones of the memory channels as taught by Kilmer.
The suggestion/motivation for doing so would have been for the benefit of preventing errors due to defective connections (see Kilmer [0046]).
Therefore it would have been obvious before the effective filing date of the invention to disable non-yielding ones of the memory channels for the benefit of preventing errors to arrive at the invention as specified in the claims.
However, Wu does not expressly disclose but in the same field of endeavor Bland discloses
wherein, the first plurality of memory channels have a second plurality of memory banks, where non-yielding ones of the memory banks within yielding ones of the memory channels are to be disabled during the operation of the memory chip stack (see Bland FIG 2: 206 and [0028] and [0035]) .
It would have been obvious before the effective filing date of the invention to disable the non-yielding banks as taught by Bland.
The suggestion/motivation for doing so would have been for the benefit of defect management (see Bland [0024]: “a defective DIMM of a particular channel in the computer memory subsystem (101); and disabling the defective DIMM, including enabling ODT for the defective DIMM without disabling any non-defective DIMMs.”).
Therefore it would have been obvious before the effective filing date of the invention to disable non-yielding ones of the banks as suggesting by Bland for the benefit of defect management to arrive at the invention as specified in the claims.
As per claim 4, the apparatus of claim 1
wherein all yielding ones of the memory channels separately included in the memory chips are to be enabled (see Bland FIG 2: 206).
As per claim 5, the apparatus of claim 4
wherein all yielding banks of the yielded memory channels separately included in the memory chips are to be enabled (see Bland FIG 2: 206).
As per claim 6, the apparatus of claim 1
wherein the plurality of memory channels separately included in the memory chips comprises at least 64 memory channels per memory chip (see Wu [0042]: “Different channel and bank configurations are possible.”)
As per claim 7, the apparatus of claim 6
wherein the plurality of memory channels separately included in the memory chips comprises at least 128 memory channels (see Wu [0042]: “Different channel and bank configurations are possible.”)
As per claim 8, the apparatus of claim 1
wherein at least some of the respective power and ground nodes of those of the memory channels on a same one of the memory chips are electrically isolated from one another (see Bland [0028]).
[Disabling selective parts requires isolating.]
Claim 9,12-17,20-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US PG PUB No. 2018/0137005) in view of Kilmer (US PG PUB No. 2015/0179285) Bland (US PG PUB No. 2010/0293410), and Hendry (US PG PUB No. 20110252180).
As per claim 9, an apparatus, comprising:
a memory chip stack (see Wu [0097]: “As a multi-device memory , memory resources 760 can include multiple individual memory dies stacked vertically or in one or more vertical stacks” ) comprising memory chips separately having a first plurality of memory channels (see Wu [0089]: “Memory resources 760 can be organized as separate channels , ranks , and banks of memory”),
[Wu discloses the memory resources may be organized as separate channels (see Wu [0097]).]
a logic chip, the memory chip stack mounted to the logic chip (see Wu FIG 2D: 240),
However, Wu does not expressly disclose but in the same field of endeavor Kilmer discloses
where, non-yielding ones of the memory channels separately included in the memory chips are to be disabled during operation of the memory chip stack (see Kilmer (Kilmer FIG 5: 518 and [0046]),
It would have been obvious before the effective filing date of the invention to further disable non-yielding ones of the memory channels as taught by Kilmer.
The suggestion/motivation for doing so would have been for the benefit of preventing errors due to defective connections (see Kilmer [0046]).
Therefore it would have been obvious before the effective filing date of the invention to disable non-yielding ones of the memory channels for the benefit of preventing errors to arrive at the invention as specified in the claims.
However, Wu does not expressly disclose but in the same field of endeavor Bland discloses
wherein, the first plurality of memory channels have a second plurality of memory banks, where, non-yielding ones of the memory banks within yielding ones of the memory channels are to be disabled during the operation of the memory chip stack (see Bland FIG 2: 206 and [0028] and [0035]); and
It would have been obvious before the effective filing date of the invention to disable the non-yielding banks as taught by Bland.
The suggestion/motivation for doing so would have been for the benefit of defect management (see Bland [0024]: “a defective DIMM of a particular channel in the computer memory subsystem (101); and disabling the defective DIMM, including enabling ODT for the defective DIMM without disabling any non-defective DIMMs.”).
Therefore it would have been obvious before the effective filing date of the invention to disable non-yielding ones of the banks as suggesting by Bland for the benefit of defect management to arrive at the invention as specified in the claims.
However, Wu does not expressly disclose but in the same field of endeavor Hendry discloses
the logic chip comprising a decoder with interleaving circuitry, the interleaving circuitry to implement memory address interleaving that does not map host addresses to the non-yielding ones of the memory channels and the non-yielding ones of the memory banks (see Hendry [0116]).
It would have been obvious before the effective filing date of the invention to modify Wu to further implement interleaving circuitry that dynamically maps as taught by Hendry.
The suggestion/motivation for doing so would have been for the benefit of improving power consumption (See Hendry [0005]).
Therefore it would have been obvious before the effective filing date of the invention to modify Wu to further implement interleaving circuitry with dynamic mapping for the benefit of improved power consumption to arrive at the invention as specified in the claims.
As per claim 12, the apparatus of claim 9
wherein all yielding ones of the memory channels separately included in the memory chips are to be enabled (see Bland FIG 2: 206).
As per claim 13, the apparatus of claim 12
wherein all yielding banks of the yielded memory channels separately included in the memory chips are to be enabled (see Bland FIG 2: 206).
As per claim 14, the apparatus of claim 9
wherein the plurality of memory channels separately included in the memory chips comprises at least 64 memory channels per memory chip (see Wu [0042]: “Different channel and bank configurations are possible.”)
As per claim 15, the apparatus of claim 14
wherein the plurality of memory channels separately included in the memory chips comprises at least 128 memory channels (see Wu [0042]: “Different channel and bank configurations are possible.”)
As per claim 16, the apparatus of claim 9
wherein at least some of the respective power and ground nodes of those of the memory channels on a same one of the memory chips are electrically isolated from one another (see Bland [0028]).
[Disabling selective parts requires isolating.]
As per claim 17, a computing system, comprising:
a memory chip stack (see Wu [0097]: “As a multi-device memory , memory resources 760 can include multiple individual memory dies stacked vertically or in one or more vertical stacks” ) comprising memory chips separately having a first plurality of memory channels (see Wu [0089]: “Memory resources 760 can be organized as separate channels , ranks , and banks of memory”),
[Wu discloses the memory resources may be organized as separate channels(see Wu [0097]).]
a logic chip, the memory chip stack mounted to the logic chip, (see Wu FIG 2D: 240), the logic chip comprising at least one of a general purpose processing core, a graphics processing core, a computational accelerator, a machine learning core, an inference engine core, an image processing core, and an infrastructure processing unit core (see e.g., Wu [0033]).
[The interconnect parts are taken as part of the logic chip.]
However, Wu does not expressly disclose but in the same field of endeavor Bland discloses
where, non-yielding ones of the memory channels separately included in the memory chips are to be disabled during operation of the memory chip stack (see Kilmer (Kilmer FIG 5: 518 and [0046]),
It would have been obvious before the effective filing date of the invention to further disable non-yielding ones of the memory channels as taught by Kilmer.
The suggestion/motivation for doing so would have been for the benefit of preventing errors due to defective connections (see Kilmer [0046]).
Therefore it would have been obvious before the effective filing date of the invention to disable non-yielding ones of the memory channels for the benefit of preventing errors to arrive at the invention as specified in the claims.
However, Wu does not expressly disclose but in the same field of endeavor Bland discloses
wherein, the first plurality of memory channels have a second plurality of memory banks, where, non-yielding ones of the memory banks within yielding ones of the memory channels are to be disabled during the operation of the memory chip stack (see Bland FIG 2: 206 and [0028] and [0035]); and
It would have been obvious before the effective filing date of the invention to disable the non-yielding banks as taught by Bland.
The suggestion/motivation for doing so would have been for the benefit of defect management (see Bland [0024]: “a defective DIMM of a particular channel in the computer memory subsystem (101); and disabling the defective DIMM, including enabling ODT for the defective DIMM without disabling any non-defective DIMMs.”).
Therefore it would have been obvious before the effective filing date of the invention to disable non-yielding ones of the banks as suggesting by Bland for the benefit of defect management to arrive at the invention as specified in the claims.
However, Wu does not expressly disclose but in the same field of endeavor Hendry discloses
the logic chip comprising a decoder with interleaving circuitry, the interleaving circuitry to implement memory address interleaving that does not map host addresses to the non-yielding ones of the memory channels and the non-yielding ones of the memory banks (see Hendry [0116]).
It would have been obvious before the effective filing date of the invention to modify Wu to further implement interleaving circuitry that dynamically maps active and inactive memory as taught by Hendry.
The suggestion/motivation for doing so would have been for the benefit of improving power consumption (See Hendry [0005]).
Therefore it would have been obvious before the effective filing date of the invention to modify Wu to further implement interleaving circuitry with dynamic mapping for the benefit of improved power consumption to arrive at the invention as specified in the claims.
As per claim 20, the computing system of claim 17
wherein all yielding ones of the memory channels separately included in the memory chips are to be enabled (see Bland FIG 2: 206).
As per claim 21, an apparatus, comprising:
a logic chip, a memory chip stack to be mounted to the logic chip (see Wu [0097]: “As a multi-device memory , memory resources 760 can include multiple individual memory dies stacked vertically or in one or more vertical stacks”),
the logic chip comprising at least one of a general purpose processing core, a graphics processing core, a computational accelerator, a machine learning core, an inference engine core, an image processing core, and an infrastructure processing unit core (see Wu [0033])
[The interconnect parts are taken as part of the logic chip.]
However, Wu does not expressly disclose circuitry to implement addressing but in the same field of endeavor Kilmer
that does not map host addresses to non-yielding ones of memory channels separately included in individual memory chips of the memory chip stack (see Kilmer (Kilmer FIG 5: 518 and [0046]),
It would have been obvious before the effective filing date of the invention to further disable non-yielding ones of the memory channels as taught by Kilmer.
The suggestion/motivation for doing so would have been for the benefit of preventing errors due to defective connections (see Kilmer [0046]).
Therefore it would have been obvious before the effective filing date of the invention to disable non-yielding ones of the memory channels for the benefit of preventing errors to arrive at the invention as specified in the claims.
However, Wu does not expressly disclose but in the same field of endeavor Bland discloses
nor to non-yielding memory banks of the yielding ones of the memory channels separately included in individual memory chips of the memory chip stack(see Bland FIG 2: 206 and [0028] and [0035]); and
It would have been obvious before the effective filing date of the invention to disable the non-yielding banks as taught by Bland.
The suggestion/motivation for doing so would have been for the benefit of defect management (see Bland [0024]: “a defective DIMM of a particular channel in the computer memory subsystem (101); and disabling the defective DIMM, including enabling ODT for the defective DIMM without disabling any non-defective DIMMs.”).
Therefore it would have been obvious before the effective filing date of the invention to disable non-yielding ones of the banks as suggesting by Bland for the benefit of defect management to arrive at the invention as specified in the claims.
However, Wu does not expressly disclose but in the same field of endeavor Hendry discloses
the logic chip comprising a decoder with interleaving circuitry, the interleaving circuitry to implement memory address interleaving that does not map host addresses to non-yielding ones of the memory chip stack's memory channels nor to non-yielding memory banks of yielding ones of the memory chip stack's memory channels (see Hendry [0116]).
It would have been obvious before the effective filing date of the invention to modify Wu to further implement interleaving circuitry that dynamically maps active and inactive memory as taught by Hendry.
The suggestion/motivation for doing so would have been for the benefit of improving power consumption (See Hendry [0005]).
Therefore it would have been obvious before the effective filing date of the invention to modify Wu to further implement interleaving circuitry with dynamic mapping for the benefit of improved power consumption to arrive at the invention as specified in the claims.
Claim 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable Wu (US PG PUB No. 2018/0137005) in view of Kilmer (US PG PUB No. 2015/0179285) and Bland (US PG PUB No. 2010/0293410) as applied to claims 1 above and further in view of Schmier (US PG PUB No. 20140244899).
As per claim 2, the apparatus of claim 1
However, Wu does not expressly disclose but in the same field of endeavor Schimer discloses
wherein yielding ones of the memory channels separately included in the memory chips are to be disabled so that there is a predetermined number of working memory channels separately included in memory chips (Schmier [0115]).
It would have been obvious before the effective filing date of the invention to disable predetermined number of working memory devices as taught by Schmier.
The suggestion/motivation for doing so would have been for the benefit of improving device lifetime (Schmier [0115]).
Therefore it would have been obvious before the effective filing date of the invention to modify Schmier to further disable predetermined number of working memory devices as taught by Schmier for the benefit of improving device life time to arrive at the invention as specified in the claims.
As per claim 3, the apparatus of claim 1
However, Wu does not expressly disclose but in the same field of endeavor Schmier discloses
wherein yielding ones of the memory banks are to be disabled so that there is a predetermined number of working memory banks in each of the memory channels (Schmier [0115]).
It would have been obvious before the effective filing date of the invention to disable predetermined number of working memory devices as taught by Schmier.
The suggestion/motivation for doing so would have been for the benefit of improving device lifetime (Schmier [0115]).
Therefore it would have been obvious before the effective filing date of the invention to modify Schmier to further disable predetermined number of working memory devices as taught by Schmier for the benefit of improving device life time to arrive at the invention as specified in the claims.
Claim 10-11,18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US PG PUB No. 2018/0137005) in view of Kilmer (US PG PUB No. 2015/0179285), Bland (US PG PUB No. 2010/0293410) and Hendry (US PG PUB No. 20110252180) as applied to claims 9 and 17 above and further in view of Schmier (US PG PUB No. 20140244899).
As per claim 10, the apparatus of claim 9
However, Wu does not expressly disclose but in the same field of endeavor Schmier discloses
wherein yielding ones of the memory channels separately included in the memory chips are to be disabled so that there is a predetermined number of working memory channels separately included in the memory chips (Schmier [0115]).
It would have been obvious before the effective filing date of the invention to disable predetermined number of working memory devices as taught by Schmier.
The suggestion/motivation for doing so would have been for the benefit of improving device lifetime (Schmier [0115]).
Therefore it would have been obvious before the effective filing date of the invention to modify Schmier to further disable predetermined number of working memory devices as taught by Schmier for the benefit of improving device life time to arrive at the invention as specified in the claims.
As per claim 11, the apparatus of claim 9
However, Wu does not expressly disclose but in the same field of endeavor Schmier discloses
wherein yielding ones of the memory banks are to be disabled so that there is a predetermined number of working memory banks in each of the memory channels (Schmier [0115]).
It would have been obvious before the effective filing date of the invention to disable predetermined number of working memory devices as taught by Schmier.
The suggestion/motivation for doing so would have been for the benefit of improving device lifetime (Schmier [0115]).
Therefore it would have been obvious before the effective filing date of the invention to modify Schmier to further disable predetermined number of working memory devices as taught by Schmier for the benefit of improving device life time to arrive at the invention as specified in the claims.
As per claim 18, the computing system of claim 17
However, Wu does not expressly disclose but in the same field of endeavor Schmier discloses
wherein yielding ones of the memory channels separately included in the memory chips are to be disabled so that there is a predetermined number of working memory channels on each of the memory chips (Schmier [0115]).
It would have been obvious before the effective filing date of the invention to disable predetermined number of working memory devices as taught by Schmier.
The suggestion/motivation for doing so would have been for the benefit of improving device lifetime (Schmier [0115]).
Therefore it would have been obvious before the effective filing date of the invention to modify Schmier to further disable predetermined number of working memory devices as taught by Schmier for the benefit of improving device life time to arrive at the invention as specified in the claims.
As per claim 19, the computing system of claim 17
However, Wu does not expressly disclose but in the same field of endeavor Schmier discloses
wherein yielding ones of the memory banks separately included in the memory chips are to be disabled so that there is a predetermined number of working memory banks in each of the memory channels separately included in the memory chips (Schmier [0115]).
It would have been obvious before the effective filing date of the invention to disable predetermined number of working memory devices as taught by Schmier.
The suggestion/motivation for doing so would have been for the benefit of improving device lifetime (Schmier [0115]).
Therefore it would have been obvious before the effective filing date of the invention to modify Schmier to further disable predetermined number of working memory devices as taught by Schmier for the benefit of improving device life time to arrive at the invention as specified in the claims.
RESPONSE TO ARGUMENTS
1st ARGUMENT:
On page 2 of the Office Action, paragraph [0059] of Wu was mentioned as disclosing two channels for a stack of memory chips. Although Wu describes two channels, these two channels are for the entire stack of chips. Wu's paragraph [0059] describes FIG. 3A. A marked up version of FIG. 3A is shown below and the red ovals highlight that the two channels are for the entire stack of memory chips. In other words, memory chips of Wu's described memory stack do not teach or describe "memory chips separately having a first plurality of memory channels" as emphasized above. Wu only describes and shows in FIG. 3A that memory chips in a memory chip stack share two channels.
Applicants submit that Bland does not teach or describe what is lacking in Wu's description as mentioned above. Therefore, Wu in view of Bland does not support a prima facie 35 U.S.C. § 103 rejection of claim 1. Claims 5-8 depend on claim 1. Thus, Applicants request that the 35 U.S.C. § 103 rejection of claims 1 and 5-8 be withdrawn.
Examiner notes Wu discloses configurations beyond FIG 3A and further discloses “[m]emory resources 760 can be organized as separate channels, ranks, and banks of memory (see Wu [0089])” where “memory resources 760 can include multiple individual memory dies stacked vertically or in one or more vertical stacks (see Wu [0097]).”
Examiner further notes, as per the Specification, “only two channels exist per memory chip in traditional stacked memory chip solution of Fig. 2 (see Specification FIG 2 and [0015]).” The subject matter Applicant is arguing appears to be admitted prior art.
Examiner maintains a person of ordinary skill in the art before the effective filing date of the invention would have found it obvious to map out non-yielding channels and non-yielding banks as taught by Kilmer and Bland for the benefit of defect management.
CONCLUSION
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
DIRECTION OF FUTURE CORRESPONDENCES
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/KALPIT PARIKH/
Primary Examiner, Art Unit 2137
KALPIT . PARIKH
Primary Examiner
Art Unit 2137
Prosecution Insights