DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (Claims 1-9 and 14-20) in the reply filed on 26MAY2026 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-9 and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over the applicant’s admitted prior art (APA). The applicant’s originally filed specification will herein be referred to as SPEC.
Consider Claim 1,
The applicant’s APA describes an apparatus, comprising:
a dual in-line memory module (DIMM) comprising i); ii); and, iii) below:
i) a memory chip (SPEC, e.g., Fig 1a(103);¶0006, memory chips.);
ii) a data buffer chip comprising write data pattern generation circuitry and comparison circuitry (SPEC, e.g., Fig 1a(104);¶0006, data buffer; ¶0017, data buffers include write data pattern generators; ¶0019, data buffers include internal comparison circuitry.), the data buffer chip to write data generated by the data pattern generation circuitry into the memory chip during training of a write data path that exists between the data buffer chip and the memory chip (SPEC, e.g., ¶0016-0018, write pattern into memory during write training.), the data buffer chip to read the written data during the training (SPEC, e.g., ¶0019, read the just written training data.), the comparison circuitry to compare the read data for errors during the training (SPEC, e.g., ¶0019, detect errors in read data.);
iii) training circuitry for the write data path, the training circuitry to, during the training, determine when a write command is to be sent to the data buffer chip to perform the write (SPEC, e.g., ¶0018, determine write in response to the command received from the RCD.), determine when a read command is to be sent to the data buffer chip to perform the read (SPEC, e.g., ¶0019, read data in response to the command received from the RCD.), and generate data buffer chip mis-comparison information resulting from the compare (SPEC, e.g., ¶0019, compare data and report errors to host.).
The applicant’s APA fails to describe wherein the training circuit receives data buffer chip mis-comparison information. However, the applicant describes the inventive concept as integrating the control circuitry into the RCD (SPEC, e.g., ¶0025). Essentially, the primary difference between the applicant’s claimed invention and the admitted prior art is migrating training control circuitry (i.e., SPEC:Fig 1a(107)) from the memory controller of the host (i.e., SPEC:Fig 1a(108)) to the RCD on the DIMM (i.e., SPEC:Fig 1a(106)). However, it would have been obvious to a person of ordinary skill in the art, prior to the effective filing date of the claimed invention, to move the training circuitry to the DIMM, resulting in the DIMM receiving the mis-comparison information, because relocating a known function to a known alternative location to produce a known result as a matter of convenience to the host (SPEC, e.g., ¶0001, engineers are seeking ways to reduce the complexity from the perspective of the host system.)
Consider Claim 2,
The modified APA further discloses a bus coupled between the data buffer chip and the training circuitry, the mis-comparison information sent by the data buffer to the training circuity over the bus (SPEC, e.g., Fig 1a(data bus);¶0019, transmit over data channel.).
Consider Claim 3,
The modified APA teaches the apparatus of claim 2, above, but fails to further detail wherein the bus is a BCOM bus. However, the prior art device disclosed by APA includes a data bus, BCOM bus, and I3C bus. It would have been obvious to a person of ordinary skill in the art, prior to the effective filing date of the claimed invention, to update the modified APA such that the bus is a BCOM bus as a simple substitution because it is one of a limited number of available buses (SPEC:Fig 1a) and, as a known JEDEC standard (SPEC, e.g., ¶0010), produces predictable results.
Consider Claim 4,
The modified APA teaches the apparatus of claim 2, above, but fails to further detail wherein the bus is an I3C bus. However, the prior art device disclosed by APA includes a data bus, BCOM bus, and I3C bus. It would have been obvious to a person of ordinary skill in the art, prior to the effective filing date of the claimed invention, to update the modified APA such that the bus is an I3C bus as a simple substitution because it is one of a limited number of available buses (SPEC:Fig 1a) and, as a known industry standard (SPEC, e.g., ¶0030), produces predictable results.
Consider Claim 5,
The modified APA further teaches wherein the data buffer chip is to transmit the write data with a strobe signal having a pre-programmed phase relationship with the write data per training iteration (SPEC, e.g., ¶0014, program the data buffer to impose the optimum phase difference.).
Consider Claim 6,
The modified APA further teaches wherein the phase relationship is determined by the training circuitry and programmed into the data buffer chip from the training circuitry (SPEC, e.g., ¶0014, discover optimum difference and program the data buffer.).
Consider Claim 7,
The modified APA further teaches wherein the training circuitry is to control multiple iterations of the training, wherein, different iterations are characterized by different phase relationships between write data written into the memory chip by the data buffer and a strobe signal sent to the memory chip by the data buffer chip (SPEC, e.g., ¶0015-0022, multiple iterations sweep through all MDQ and MDQS phase relationships.).
Consider Claim 8,
The modified APA further teaches wherein the training circuitry is to determine the phase relationships (SPEC, e.g., ¶0023, determine optimum phase relationships.).
Consider Claim 9,
The modified APA further teaches wherein the training circuitry is to determine reference voltages (SPEC, e.g., ¶0021, training determines appropriate VREF.).
Consider Claim 14,
The APA discloses a computing system, comprising:
a memory controller (SPEC, e.g., Fig 1b(108), memory controller.);
a main memory coupled to the memory controller, the main memory comprising a DIMM, the DIMM comprising i); ii); and, iii) below:
i) a memory chip (SPEC, e.g., Fig 1a(103);¶0006, memory chips.);
ii) a data buffer chip comprising write data pattern generation circuitry and comparison circuitry (SPEC, e.g., Fig 1a(104);¶0006, data buffer; ¶0017, data buffers include write data pattern generators; ¶0019, data buffers include internal comparison circuitry.),, the data buffer chip to write data generated by the data pattern generation circuitry into the memory chip during training of a write data path that exists between the data buffer chip and the memory chip (SPEC, e.g., ¶0016-0018, write pattern into memory during write training.), the data buffer chip to read the written data during the training (SPEC, e.g., ¶0019, read the just written training data.), the comparison circuitry to compare the read data for errors during the training (SPEC, e.g., ¶0019, detect errors in read data.);
iii) training circuitry for the write data path, the training circuitry to, during the training, generate a write command and send the write command to the data buffer chip to perform the write (SPEC, e.g., ¶0018, determine write in response to the command received from the RCD.), generate a read command and send the read command to the data buffer chip to perform the read (SPEC, e.g., ¶0019, read data in response to the command received from the RCD.), and generate data buffer chip mis-comparison information resulting from the compare (SPEC, e.g., ¶0019, compare data and report errors to host.).
The applicant’s APA fails to describe a plurality of processing cores, wherein the memory controller is coupled to the plurality of processor cores, or wherein the training circuit receives data buffer chip mis-comparison information. However, the applicant describes the inventive concept as integrating the control circuitry into the RCD (SPEC, e.g., ¶0025). Essentially, the primary disclosed difference between the applicant’s claimed invention and the admitted prior art is migrating training control circuitry (i.e., SPEC:Fig 1a(107)) from the memory controller of the host (i.e., SPEC:Fig 1a(108)) to the RCD on the DIMM (i.e., SPEC:Fig 1a(106)). However, it would have been obvious to a person of ordinary skill in the art, prior to the effective filing date of the claimed invention, to move the training circuitry to the DIMM, resulting in the DIMM receiving the mis-comparison information, because relocating a known function to a known alternative location to produce a known result as a matter of convenience to the host (SPEC, e.g., ¶0001, engineers are seeking ways to reduce the complexity from the perspective of the host system.).
The modified APA fails to disclose wherein the computing system includes a plurality of processing cores or wherein the memory controller is coupled to the processing cores. The examiner takes official notice of the fact that a memory controller coupled to a plurality of processing cores is ubiquitous in the art. It would have been obvious to include a plurality of processing cores coupled to the memory controller in the modified APA system because they ubiquitous in the art and provide necessary and required functions in nearly all computing systems.
Consider Claim 15,
The further modified APA additionally describes a bus coupled between the data buffer chip and the training circuitry, the mis-comparison information sent by the data buffer to the training circuitry chip over the bus (SPEC, e.g., Fig 1a(data bus);¶0019, transmit over data channel.).
Consider Claim 16,
The further modified APA additionally describes wherein the data buffer chip is to transmit the write data with a strobe signal having a pre-programmed phase relationship with the write data per training iteration (SPEC, e.g., ¶0014, program the data buffer to impose the optimum phase difference.).
Consider Claim 17,
The further modified APA additionally describes wherein the phase relationship is determined by the training circuitry and programmed into the data buffer chip by the training circuitry (SPEC, e.g., ¶0014, discover optimum difference and program the data buffer.).
Consider Claim 18,
The further modified APA additionally describes wherein the training circuitry is to control multiple iterations of the training, wherein, different iterations are characterized by different phase relationships between write data written into the memory chip by the data buffer and a strobe signal sent to the memory chip by the data buffer chip (SPEC, e.g., ¶0015-0022, multiple iterations sweep through all MDQ and MDQS phase relationships.).
Consider Claim 19,
The further modified APA additionally describes wherein the training circuitry is to determine the phase relationships (SPEC, e.g., ¶0023, determine optimum phase relationships.).
Consider Claim 20,
The further modified APA additionally describes wherein the training circuitry is to determine reference voltages (SPEC, e.g., ¶0021, training determines appropriate VREF.).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[A] Partsch et al. (US PGPub No. 2023/0298642 A1) – describes systems and methods for data write path training including timing training (see, e.g., Fig 6;¶0025).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Gary W Cygiel whose telephone number is (571)270-1170. The examiner can normally be reached Monday - Thursday 11am-3pm PST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan P Savla can be reached at (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Gary W. Cygiel/Primary Examiner, Art Unit 2137
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