DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1, the recitation of “the node” (line 5) lacks proper antecedent basis, thus, the metes and bounds of the claim cannot be readily determined renders the claim indefinite.
In claim 2, the recitation of “the second clock signal” (line 5) lacks proper antecedent basis, thus, the metes and bounds of the claim cannot be readily determined renders the claim indefinite.
Claims 3-16 are indefinite because of the technical deficiencies of claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-11, 15-16 and 23-24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mizuno (USP 6,304,124).
Regarding claim 1, Mizuno’s figure 3 shows An apparatus comprising: a first node (102); a second node (103); a first transistor (152; figure 4) and a second transistor (151, figure 4), the first and second transistors including a common gate coupled to the node (103) and a common terminal coupled to the second node (104); first additional transistors (108) coupled in parallel with each other between a terminal of the first transistor and a first supply node (106), the first additional transistors including gates; and second additional transistors (109) coupled in parallel with each other between a terminal of the second transistor and a second supply node (107), the second additional transistors including gates as called for in claim 1.
Regarding claim 2, Mizuno’s figure 7 further comprising a second stage (161) comprising: a third transistor and a fourth transistor (152, 151; figure 4), the third and fourth transistors including a common gate coupled to the second node (102, figure 3) and a common terminal coupled to couple to a third node (103; figure 3) to provide a third clock signal at the third node based on the second clock signal; third additional transistors (108; figure 3) coupled in parallel with each other between a terminal of the third transistor and the first supply node, the third additional transistors including gates to receive respective third voltages (111-11N); and fourth additional transistors (109; figure 3) coupled in parallel with each other between a terminal of the fourth transistor and the second supply node, the fourth additional transistors including gates to receive respective fourth voltages (121, 12N).
Regarding claim 3, Mizuno’s figure 4 shows first and second transistors have different transistor types.
Regarding claim 4, Mizuno’s figure 3 shows wherein the first additional transistors (108) have a first transistor type (P type), and the second additional transistors (109) have a second transistor type (N type).
Regarding claim 5, Mizuno’s figure 3 shows the first node (102) is to receive a first clock signal; the first and second transistors are to receive the first clock signal and to provide a second clock signal at the second node (103) based on the first clock signal; the gates of the first additional transistors are to receive respective first voltages at the gates (111-11N); and the gates of the second additional transistors are receive respective second voltages (121-12N).
Regarding claim 6, Mizuno’s figure 3 shows wherein at least two of the respective first voltages have unequal values (opposite logic levels).
Regarding claim 7, Mizuno’s figure 3 shows wherein the respective first voltages have an equal value (same logic levels).
Regarding claim 8, Mizuno’s figure 3 shows at least two of the respective second voltages have unequal values (opposite logic levels).
Regarding claim 9, Mizuno’s figure 3 shows wherein the respective second voltages have an equal value (same logic levels).
Regarding claim 10, Mizuno’s figure 3 show wherein at least one of the respective first voltages has a value unequal to at least one of the second voltages (opposite logic levels).
Regarding claim 11, Mizuno’s figure 7 further shows comprising an inverter (151, 152 of a subsequent stage) to provide an output clock signal based on the second clock signal.
Regarding claim 15, Mizuno’s circuit is capable of being included in a system-on-chip.
Regarding claim 16, Mizuno’s circuit is capable of being included in a system, and the system includes an antenna.
Regarding claim 23, Mizuno’s figure 3 shows a circuit comprising a method: providing a clock signal to a common gate (102) of a first transistor and a second transistor (152, 151; figure 4); providing first voltages to respective gates of first additional transistors (111-11N) coupled in parallel with each other between a terminal of the first transistor and a first supply node (106); and providing second voltages to respective gates of second additional transistors (121-12N) coupled in parallel with each other between a terminal of the second transistor and a second supply node (107) as called for in claim 23.
Regarding claim 24, Mizuno’s figure 7 further comprising: providing an additional clock signal from a common terminal of the first and second transistors to a common gate of a third transistor and a fourth transistor (second stage 161); providing third voltages to respective gates of third additional transistors (111-11N if the second stage) coupled in parallel with each other between a terminal of the third transistor and the first supply node; and providing fourth voltages to respective gates of fourth additional transistors (121-12N) coupled in parallel with each other between a terminal of the fourth transistor and the second supply node.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Heyne (US 2007/0273416) in view of Mizuno (USP 6,304,124).
Regarding claim 12, Heyne’s figure 2 show an apparatus comprising: a data path (13); a clock path to generate at least one of a clock signal and a strobe signal (10, 1, 11); and a driver (12) to receive data from the data path based on timing of the at least one of the clock signal and the strobe signal, the clock path including a clock signal adjustment circuit (4) but fails to show the clock signal adjustment circuit includes the first and second transistors, the first additional transistors, and the second additional transistors as called for in claim 1.
Mizuno’s figure 3 shows a clock signal adjustment circuit that is capable of providing high accuracy and less susceptible to noise comprising a first node (102); a second node (103); a first transistor (152; figure 4) and a second transistor (151, figure 4), the first and second transistors including a common gate coupled to the node (103) and a common terminal coupled to the second node (104); first additional transistors (108) coupled in parallel with each other between a terminal of the first transistor and a first supply node (106), the first additional transistors including gates; and second additional transistors (109) coupled in parallel with each other between a terminal of the second transistor and a second supply node (107), the second additional transistors including gates. Therefore, it would have been obvious to person skilled in the art before the effective filing of the invention to have Heyne’s clock adjustment circuit (4) replaced by Mizuno’s clock adjustment circuit for the purpose of providing high accuracy and less susceptible to noise as taught by Mizuno reference.
Regrading claim 13, Heyne’s figure 3 shows wherein the clock path includes at least one of a multi-phase clock generator to generate clock signals having different phases (5), duty- cycle correction circuitry (17), a strobe generator to generate the strobe signal (CLK0), and wherein the clock signal adjustment circuit is included in at least one of the multi- phase clock generator, the duty-cycle correction circuitry, and the strobe generator.
Regarding claim 14, Heyne’s figure 3 wherein the clock path includes phase-locked loop (9, capable of being a phase locked loop to generate the clock signal CLK) having an output coupled to an input of the multi-phase clock generator.
Allowable Subject Matter
Claims 17-22 are presently allowed.
Claim 25 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/TUAN T LAM/Primary Examiner, Art Unit 2842 1/5/2026