DETAILED ACTION
Claims 10-25 are pending.
Notice of Pre-AIA or AIA Status
This Office Action is sent in response to Applicant’s Communication received on 04/03/2026 for application number 18/086,882.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10, 14, 17, 18, 22 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Varma et al. (US 2013/0339777 A1) in view of Luo et al. (US 2017/0300398 A1).
Regarding claim 10, Varma teaches a method comprising:
receiving a current monitor value from a voltage regulator controller at a power management unit within a processor (“VR 130 can provide current measurement 134 to processor 110.” Par 0024 and “PCU (power control unit) 120 represents power management logic of processor 110.” Par 0028 and Figure 1);
receiving a measured output voltage (“The power supply connected to the processor can be carefully monitored for voltage,” par 0040);
generating an estimated current value based on the measured output voltage and a processor load line (“Using the stored values of power consumption … and the known voltage of operation, BIOS 118 can compute the expected value of electrical current that the processor actually consumed.” Par 0032) [the estimated (expected) current is calculated by combining measured voltage with stored workload and power (load line)];
generating a delta current value based on a difference between the estimated current value and the current monitor value (“The processor receives a current measurement from the voltage regulator and computes an offset based on the measured value and a stored expected value.” Par 0021) [the delta (offset) is calculated using VR’s current measurement and the expected current].
However, Varma does not explicitly teach comparing, by the power management unit, the delta current value to a current reporting accuracy threshold to determine whether the current monitor value as reported by the voltage regulator controller is accurate; and generating, by the power management unit, a current misreporting flag in response to a determination that the delta current value transgresses the current reporting accuracy threshold.
In the analogous art, Luo teaches comparing, by the power management unit, the delta current value to a current reporting accuracy threshold to determine whether the current monitor value as reported by the voltage regulator controller is accurate (“the Imon detection capabilities of the current sensing components in the voltage regulator 300 may be tested to determine the accuracy of Imon detection and reporting.” Par 0021 and “the monitored power reporting subsystem 304 is an Imon calibration subsystem that may be statically set (e.g., via the voltage regulator operation offset information) to meet Imon reporting accuracy requirements” par 0017) [the accuracy of the current detection (magnitude of error/delta current) is tested against the accuracy requirements (threshold) to determine if the current is within an acceptable range, e.g. 4-5%, see paragraph 3]; and
generating, by the power management unit, a current misreporting flag in response to a determination that the delta current value transgresses the current reporting accuracy threshold (“The first offset Imon offset component 316 a may then provide information describing the second offset Imon in the telemetry register 316 c.” par 0028 and “the Imon detection capabilities of the current sensing components in the voltage regulator 300 may be tested to determine the accuracy of Imon detection and reporting.” Par 0021 and “produce a second offset Imon that, when reported to the processing system 204, configured to optimize the operation of the processor(s)” par 0019 and paragraph 21 and Figure 4) [the generation of the second offset corresponds to a signal (flag) informing the system that the first current report was inaccurate].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Varma and Luo before him before the effective filing date of the claimed invention, to have modified Varma to incorporate the teachings of Luo to use a current reporting accuracy threshold to optimize voltage regulator efficiency across the operational load range. (Luo, paragraph 27)
Regarding claim 14, Varma and Luo teach the method of claim 10. Varma further teaches the method further including:
receiving a plurality of current values from the voltage regulator controller (“BIOS 118 can compute the expected value of electrical current that the processor actually consumed. In one embodiment, BIOS 118 uses several such readings to compute correction factors to be programmed.” Par 0032); and
generating a multiple current sample average based on the plurality of current values (“The actual correction factors can be computed using least-squares regression, best-fit analysis, two-point analysis, or other known mathematical techniques and heuristics.” Par 0035) [the aggregation of the readings into a corrected value corresponds to the multiple current sample average];
wherein the delta current value is based on a current difference between the estimated current value and the multiple current sample average (“The processor receives a current measurement from the voltage regulator and computes an offset based on the measured value and a stored expected value.” Par 0021) [the offset is the delta value, resulting from difference between actual readings and the estimated current (stored value)].
Claim 22 corresponds to claim 14 and is rejected accordingly.
Regarding claim 17, Varma and Luo teach the method of claim 10. Luo further teaches the method further including receiving the measured output voltage at the power management unit from a voltage output register within the voltage regulator controller (“the processors 204 a-204 c in the processing system 204 may then access the telemetry registers 316 c in the processor power reporting offset subsystems of their respective voltage regulators 300,” Par 0028 and “telemetry register 316 c may be provided by an SVID Imon telemetry register (e.g., 0x15) that a coupled to the processing system 204 via an SVID bus.” Par 0019 and Figure 3).
Claim 25 corresponds to claim 17 and is rejected accordingly
Regarding claim 18, Varma teaches a system comprising:
a voltage regulator circuit including a power stage and a voltage regulator controller (Figure 1, voltage regulator 130; Figure 9 bus controller units; Figures 5, 6, 10-13); and
a processor (Figure 1, processor 110) including a power management unit (Figure 1, power control unit 120).
The remainder of claim 18 corresponds to claim 1 and is rejected accordingly.
Claims 13 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Varma and Luo in view of Richards et al. (US 2016/0018833 A1).
Regarding claim 13, Varma and Luo teach the method of claim 11. However, Varma and Luo do not explicitly teach the method further including generating a power misreporting flag in response to a determination that the delta current value transgresses a current reporting threshold and the delta voltage value transgresses the voltage reporting threshold.
In the analogous art, Richards teaches the method further including generating a power misreporting flag in response to a determination that the delta current value transgresses a current reporting threshold and the delta voltage value transgresses the voltage reporting threshold (“For example, if the CPU voltage regulator 128 is over-reporting the voltage and current, the CPU 102 may decide to implement power capping algorithms based on a determination that the CPU 102 is approaching a temperature or power threshold, which results in reduced CPU 102 performance.” Par 0028 and Figures 2-6) [the over-reporting of both voltage and current (transgression of delta thresholds) causes the CPU to implement power capping, which results in corrective action (power misreporting flag) to reduce performance].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Varma, Luo and Richards before him before the effective filing date of the claimed invention, to have modified Varma and Luo to incorporate the teachings of Richards to include a power misreporting flag to allow the CPU to make optimal performance decisions, ensuring the voltage regulator values/measurements are correct. (Richards, paragraphs 28-29)
Claim 21 corresponds to claim 13 and is rejected accordingly.
Claims 11, 12, 15, 16, 19, 20, 23 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Varma and Luo in view of Morrell (US 2008/0291071 A1).
Regarding claim 11, Varma and Luo teach the method of claim 10. However, Varma and Luo do not explicitly teach generating an estimated voltage output based on the current monitor value; generating a delta voltage value based on a difference between the estimated voltage output and the measured output voltage; and generating a voltage misreporting flag in response to a determination that the delta current value transgresses a voltage reporting threshold.
In the analogous art, Morrell teaches generating an estimated voltage output based on the current monitor value (“The expected voltage may be obtained as a “table lookup” for a given VID value.” Par 0021) [the expected (estimated) voltage is generated from VID singal corresponding to the current monitor value because it is selected by the CPU according to the processing load placed upon it, see paragraph 21];
generating a delta voltage value based on a difference between the estimated voltage output and the measured output voltage (“a validation module compares the supplied voltage to a voltage expected in relation to the VID and computes a difference between the expected voltage and the supplied voltage.” Par 0008) [this shows calculation of a difference (delta) between estimated voltage and supplied (measured) voltage]; and
generating a voltage misreporting flag in response to a determination that the delta current value transgresses a voltage reporting threshold (“If the average of the errors recorded by the voltage error register 64 exceeds the threshold(s) or margin of error specified in the regulation thresholds database 66, such as +/−10%, then the signal 65 generated may include an alert. This alert may trigger or at least indicate the need for corrective action,” par 0030).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Varma, Luo and Morrell before him before the effective filing date of the claimed invention, to have modified Varma and Luo to incorporate the teachings of Morrell to generate a delta voltage value and check it against the voltage reporting threshold to ensure that the voltage provided by the system is within the margin of error and thus prevent loss of important data. (Morrell, paragraph 30)
Claim 19 corresponds to claim 11 and is rejected accordingly.
Regarding claim 12, Varma, Luo and Morrell teach the method of claim 11. Luo further teaches the method further including generating a voltage product of the current monitor value and a processor load line (“the output voltage positioning of the voltage regulator that relies on the reported Imon (e.g., Vout=VID−(LL*Imon)).” Par 0005) [LL represents the processor load line], wherein the estimated voltage output is based on a difference between an initial set voltage and the voltage product [the formula in paragraph 5 shows the estimated output voltage (Vout) as the difference between initial requested voltage (Vin) and previously generated voltage product].
Claim 20 corresponds to claim 12 and is rejected accordingly.
Regarding claim 15, Varma and Luo teach the method of claim 11. However, Varma and Luo do not explicitly teach receiving a plurality of voltage values; and generating a multiple voltage sample average based on the plurality of voltage values; wherein the delta voltage value is based on a voltage difference between the multiple voltage sample average and the measured output voltage.
In the analogous art, Morrell teaches receiving a plurality of voltage values (“The voltage monitoring system 10 includes an analog to digital (“A/D”) converter 20 for converting analog voltage readings to digital values, ” Par 0020); and
generating a multiple voltage sample average based on the plurality of voltage values (“The error between the expected voltage (as indicated by the VID) and the actual voltage (as indicated by the digital voltage value) are recorded and the error is averaged in step 114” par 0032) [multiple individual voltage error readings (delta voltage values) are aggregated and an average is calculated based on these];
wherein the delta voltage value is based on a voltage difference between the multiple voltage sample average and the measured output voltage (“The error between the expected voltage (as indicated by the VID) and the actual voltage (as indicated by the digital voltage value) are recorded and the error is averaged in step 114” par 0032) [the delta voltage is the difference calculated by comparing the expected voltage (which serve as reference/ initial value) against the actual measured voltage].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Varma, Luo and Morrell before him before the effective filing date of the claimed invention, to have modified Varma and Luo to incorporate the teachings of Morrell to generate a voltage sample average and a delta voltage value to enable reliable and accurate monitoring of voltage in variable voltage processors, enhancing the accuracy of power calculations and limits described in the Varma and Luo sources. (Morrell, paragraph 18)
Claim 23 corresponds to claim 15 and is rejected accordingly.
Regarding claim 16, Varma and Luo teach the method of claim 10. However, Varma and Luo do not explicitly teach the method further including: providing a differential voltage sense to a voltage regulator circuit from a voltage sensor within the processor; and generating the measured output voltage at the voltage sensor based on the differential voltage sense.
In the analogous art, Morrell teaches providing a differential voltage sense to a voltage regulator circuit from a voltage sensor within the processor (“The A/D conversion module 20 includes a receiver portion 22 for receiving an analog reading of the voltage generated by the VRM 12, an A/D converter core 24 for converting the analog voltage reading to a digital value,” par 0024) [the analog reading (differential voltage sense) is provided to the receiver (voltage regulator circuit) from the point where voltage is supplied t the CPU (voltage sensor within the processor)]; and
generating the measured output voltage at the voltage sensor based on the differential voltage sense (“the raw A/D reading is converted to voltage in step 110.” Par 0031 and Figure 4).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Varma, Luo and Morrell before him before the effective filing date of the claimed invention, to have modified Varma and Luo to incorporate the teachings of Morrell to generate a measured output voltage based on the differential voltage sense to compare to the actual volage of the system to make a determination whether evasion actions are required. (Morrell, paragraphs 31-32 and Figure 4)
Claim 24 corresponds to claim 16 and is rejected accordingly.
Response to Arguments
Applicant’s arguments with respect to claim(s) 10 and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
No additional arguments were presented as to the remaining claims. As such, the rejection is maintained.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AYMAN FATIMA whose telephone number is (571)270-0830. The examiner can normally be reached M to Fri between 8am and 4pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached on (571)270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AYMAN FATIMA/Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176
Prosecution Insights