DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
Receipt is acknowledged of a request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e) and a submission, filed on 04/13/2026.
Response to Arguments
Applicant’s arguments with respect to claim(s) rejected have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5,10-11,16-19,22 and 26-28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. 20220216283.
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Regarding claim 1, fig. 6A of Kim discloses a light emitting display device, comprising:
a substrate 100 divided into a display area DA and a non-display area NDA surrounding the display area, the display area including at least one pixel;
a pixel driving circuit layer (transistor layer) disposed on the substrate and including a driving transistor;
a planarization layer 209 covering the pixel driving circuit layer;
at least one anode electrode 221 provided on the planarization layer and arranged in the at least one pixel;
banks 215 disposed between the at least one anode electrode;
a light emitting layer 222 disposed on the at least one anode electrode and the banks;
a cathode electrode 223 disposed on the light emitting layer;
a capping layer 310 covering the cathode electrode;
an encapsulation layer 330 disposed on side surfaces and an upper surface of the capping layer;
an encapsulation substrate 40 disposed on the encapsulation layer and attached on the capping layer by the encapsulation layer; and
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a foreign matter blocking area (portion of IR1 as labeled by examiner above - par [0116]) disposed in the non-display area, the foreign matter blocking area extending around an outermost edge of the display area (fig. 5A) and comprising at least one hole (combine top hole of 223oh on top and bottom hole of 222oh - fig. 6B) where the light emitting layer and the cathode electrode are disconnected and in which the pixel driving circuit layer is covered by the encapsulation layer in the at least one hole,
wherein the foreign matter blocking area is disposed between respective opposing disconnected portions of the light emitting layer and the cathode electrode and does not overlap with the light emitting layer and the cathode electrode in a plan view (necessary the case from figs. 5-6).
Regarding claim 2, fig. 6B of Kim discloses further comprising a heat line (LA of AR1 – fig. 5B and par [0119]) disposed in the foreign matter blocking area IR1, wherein the at least one hole of the foreign matter blocking area includes a heat line hole (IR hole of 222oh) that disconnects in the light emitting layer in the foreign matter blocking area, wherein the heat line hole surrounds the display area, and the heat line (LA of AR1) is exposed through the heat line hole covered by the encapsulation layer.
Regarding claim 3, Kim discloses wherein the heat line is connected with a main heat line (portion of substrate below IR is main heat line which during substrate processing because the substrate is either heated up or cool down via substrate – as such is considered by examiner to main heat line) provided on a different layer from a layer (layer 100) where the heat line is provided.
Regarding claim 4, fig. 6A of Kim discloses further comprising a heat line pad (bottom surface of 100 is heat line pad which is pad for heating and cooling the substrate) connected with the main heat line provided in the non-display area.
Regarding claim 5, Kim discloses wherein the main heat line is provided on the substrate, in a floating state (the substrate is a floating state as state of the substrate float from one state to another state during processing steps).
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Regarding claim 10, fig. 6B of Kim discloses wherein the heat line includes at least two auxiliary heat lines (AR2 and another AR2) electrically connected with each other (as they are in direct contact with AR1 and AR2), and wherein the heat line hole includes auxiliary heat line holes (AR2 is a hole in between AR1s) corresponding to the auxiliary heat lines.
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Regarding claim 11, figs. 6A/B of Kim discloses wherein the auxiliary heat lines exposed through the auxiliary heat line holes are covered by the encapsulation layer.
Regarding claim 16, fig. 6A of A light emitting display device, comprising:
a substrate 100 divided into a display area AA and a non-display area NDA surrounding the display area, the display area including at least one pixel;
a pixel driving circuit layer (transistor layer) provided on the substrate and including a driving transistor;
a planarization layer 209 covering the pixel driving circuit layer;
at least one anode electrode 221 provided on the planarization layer and arranged in in the at least one pixel;
banks 215(s) disposed between the at least one anode electrode;
a light emitting layer (intermediate layer 222) disposed on the at least one anode electrode and the banks;
a cathode electrode 223 disposed on the light emitting layer;
a capping layer 310 covering the cathode electrode;
an encapsulation layer 330 provided on side surfaces and an upper surface of the capping layer;
an encapsulation substrate 40 attached to the capping layer through the encapsulation layer,
a foreign matter blocking area (portion of IR1 as labeled by examiner above - par [0116]) disposed in the non-display area, the foreign matter blocking area extending around an outermost edge (edge of 217 in fig. 6A) of the display area and comprising at least one hole (combine top hole of 223oh on top and bottom hole of 222oh - fig. 6B) where the light emitting layer and the cathode electrode are disconnected; and
an undercut area (area under right side and left side of 221) spaced apart from and extending alongside the foreign matter blocking area,
wherein a side surface of the light emitting layer provided in the undercut area is covered by the cathode electrode, and
wherein the foreign matter blocking area is disposed between respective opposing disconnected portions of the light emitting layer and the cathode electrode and does not overlap with the light emitting layer and the cathode electrode in a plan view (it is necessary the case).
Regarding claim 17, fig. 6A of Kim discloses wherein the undercut area is provided along the foreign matter blocking area in the display area.
Regarding claim 18, fig. 6A of Kim discloses wherein the undercut area is provided between the display area and the foreign matter blocking area.
Regarding claim 19, fig. 6A of Kim discloses wherein the undercut area includes at least one of a pixel driving circuit layer (TFT), a planarization layer.
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Regarding claim 22, fig. 6A of Kim discloses a light emitting display device, comprising:
a substrate 100 divided into a display area AA and a non-display area NDA surrounding the display areal the display area including at least one pixel;
a pixel driving circuit layer (transistor layer) provided on the substrate and including a driving transistor;
a planarization layer 209 covering the pixel driving circuit layer;
at least one anode electrode 221 provided on the planarization layer and respectively provided in the at least one pixel;
a light emitting layer 222 disposed on the at least one anode electrode;
a cathode electrode 223 disposed on the light emitting layer;
a foreign matter blocking area (portion of IR1 as labeled by examiner above - par [0116]) disposed in the non-display area, the foreign matter blocking area extending around an outermost edge of the display area and comprising at least one hole (combine top hole of 223oh on top and bottom hole of 222oh - fig. 6B) where the light emitting layer and the cathode electrode are disconnected; and
a pixel undercut area (area under 221 left and right) disposed between the pixels, the pixel undercut area spaced apart from and extending alongside the foreign matter blocking area,
wherein the foreign matter blocking area is disposed between respective opposing disconnected portions of the light emitting layer and the cathode electrode and does not overlap with the light emitting layer and the cathode electrode in a plan view.
Regarding claim 26, fig. 6A of Kim discloses further comprising: a capping layer 310 covering the cathode electrode; an encapsulation layer 330 provided on side surfaces and an upper surface of the capping layer; and an encapsulation substrate 40 attached on the capping layer through the encapsulation layer.
Regarding claim 27 (see rejection of claim 2 above), further comprising a heat line provided in the foreign matter blocking areas wherein the at least one hole includes a heat line hole that disconnects the light emitting layer in the foreign matter blocking area.
Regarding claim 28 (see rejection of claim 3 above), Kim discloses wherein the heat line is connected with a main heat line provided on a different layer from a layer where the heat line is provided.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST.
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/VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893
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