DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) rejected have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-4 and 27-28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 2 and 27 recites “a heat line hole provided in the light emitting layer provided in the foreign matter blocking area” is unclear and indefinite as to how the light emitting layer is provided in the foreign matter blocking area since claims 1 and 22 recite “wherein the foreign matter blocking area does not overlap with the light emitting layer and the cathode electrode” and therefore the light emitting layer cannot be provided in the foreign matter blocking area. As such the claim is unclear and indefinite.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 22 and 27-28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. 20200119304 (Choi).
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Regarding claim 22, figs. 1, 9-10 of Choi discloses a light emitting display device, comprising:
a substrate 101 divided into a display area and a non-display area NDA (fig. 1) surrounding the display area;
a pixel driving circuit layer (as labeled by examiner above) provided on the substrate and including a driving transistor;
a planarization layer 209 covering the pixel driving circuit layer;
at least one anode electrode 221 provided on the planarization layer and respectively provided in pixels;
a light emitting layer 222 disposed on the at least one anode electrode;
a cathode electrode 223 disposed on the light emitting layer;
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a foreign matter blocking area disposed in the non-display area, surrounding the display area and disposed in an area where the light emitting layer and the cathode electrode are disconnected; and
a pixel undercut area disposed between the pixels (see figs. 1-6 showing pixels configuration around said area) and disposed along the foreign matter blocking area,
wherein the foreign matter blocking area is disposed between respective opposing disconnected portions of the light emitting layer and the cathode electrode and does not overlap with the light emitting layer and the cathode electrode in a plan view.
Regarding claim 27, fig. 10 of Choi discloses further comprising a heat line (portion of 310 and 330 which produces heat to some degree) provided in the foreign matter blocking area and a heat line hole (region without the light emitting layer is a heat line hole) provided in the light emitting layer provided in the foreign matter blocking area.
Regarding claim 28, fig. 10 of Choi discloses wherein the heat line is connected with a main heat line 103 (which produces heat to some degree) provided on a different layer from a layer where the heat line is provided.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 10-11, 16-19 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Chung et al. 20200357871.
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Regarding claim 1, figs. 1, 9-10 of Choi discloses a light emitting display device, comprising:
a substrate 101 divided into a display area DA and a non-display area NDA surrounding the display area;
a pixel driving circuit layer (as labeled by examiner above) disposed on the substrate and including a driving transistor TFT;
a planarization layer 209 covering the pixel driving circuit layer;
at least one anode electrode 221 provided on the planarization layer in pixels;
banks 211 disposed between the at least one anode electrode;
a light emitting layer 222 disposed on the at least one anode electrode and the banks;
a cathode electrode 223 disposed on the light emitting layer;
a capping layer 230 covering the cathode electrode;
an encapsulation layer 300 disposed on side surfaces and an upper surface of the capping layer;
and
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a foreign matter blocking area (as labeled by examiner above) disposed in the non-display area where the light emitting layer and the cathode electrode are disconnected and the pixel driving circuit layer is covered by the encapsulation layer and the foreign matter blocking area surrounding the display area,
wherein the foreign matter blocking area is disposed between respective opposing disconnected portions of the light emitting layer and the cathode electrode and does not overlap with the light emitting layer and the cathode electrode in a plan view (this is necessary the case – see fig. 1).
Choi discloses an encapsulation substrate attached on the capping layer through the encapsulation layer.
However, fig. 2 of Chung discloses a light emitting display device, comprising:
a substrate 140 divided into a display area and a non-display area surrounding the display area;
a pixel driving circuit layer disposed on the substrate and including a driving transistor TFT;
a planarization layer 19 covering the pixel driving circuit layer;
at least one anode electrode provided on the planarization layer in pixels;
banks 21 disposed between the at least one anode electrode;
a light emitting layer disposed on the at least one anode electrode and the banks;
a cathode electrode disposed on the light emitting layer;
an encapsulation layer 30 on side surface of the cathode electrode;
an encapsulation substrate 150 attached on the cathode electrode through the encapsulation layer.
In view of such teaching, it would have been obvious to form device of Choi further comprising an encapsulation substrate attached on the capping layer through the encapsulation layer such as taught by Chung in order to form an upper sealing structure and prevents moisture from flowing into the organic light emitting unit from the outside.
Regarding claims 16 and 26, figs. 1, 9-10 of Choi discloses a light emitting display device, comprising:
a substrate divided into a display area and a non-display area surrounding the display area;
a pixel driving circuit layer provided on the substrate and including a driving transistor;
a planarization layer covering the pixel driving circuit layer;
at least one anode electrode provided on the planarization layer in pixels;
banks disposed between the at least one anode electrode;
a light emitting layer disposed on the at least one anode electrode and the banks;
a cathode electrode disposed on the light emitting layer;
a capping layer covering the cathode electrode;
an encapsulation layer provided on side surfaces and an upper surface of the capping layer;
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a foreign matter blocking area disposed in the non-display area where the light emitting layer and the cathode electrode are disconnected and surrounding the display area; and
an undercut area (as labeled by examiner above) provided along the foreign matter blocking area, wherein a side surface of the light emitting layer provided in the undercut area is covered by the cathode electrode, and
wherein the foreign matter blocking area is disposed between respective opposing disconnected portions of the light emitting layer and the cathode electrode and does not overlap with the light emitting layer and the cathode electrode in a plan view (this is necessary the case – see fig. 1).
Choi discloses an encapsulation substrate attached on the capping layer through the encapsulation layer.
However, fig. 2 of Chung discloses a light emitting display device, comprising:
a substrate 140 divided into a display area and a non-display area surrounding the display area;
a pixel driving circuit layer disposed on the substrate and including a driving transistor TFT;
a planarization layer 19 covering the pixel driving circuit layer;
at least one anode electrode provided on the planarization layer in pixels;
banks 21 disposed between the at least one anode electrode;
a light emitting layer disposed on the at least one anode electrode and the banks;
a cathode electrode disposed on the light emitting layer;
an encapsulation layer 30 on side surface of the cathode electrode;
an encapsulation substrate 150 attached on the cathode electrode through the encapsulation layer.
In view of such teaching, it would have been obvious to form device of Choi further comprising an encapsulation substrate attached on the capping layer through the encapsulation layer such as taught by Chung in order to form an upper sealing structure and prevents moisture from flowing into the organic light emitting unit from the outside.
Regarding claim 2, fig. 10 of Choi discloses further comprising a heat line (portion of 310 and 330 which produces heat to some degree) provided in the foreign matter blocking area and a heat line hole (region without the light emitting layer is a heat line hole) provided in the light emitting layer provided in the foreign matter blocking area.
wherein the heat line hole surrounds the display area, and the heat line is exposed through the heat line hole covered by the encapsulation layer (the region without the light emitting exposed the heat line).
Regarding claim 3, fig. 10 of Choi discloses wherein the heat line is connected with a main heat line 223 (in 222’) provided on a different layer from a layer where the heat line is provided.
Regarding claim 4, fig. 10 of Choi discloses further comprising a heat line pad 222a (in 222’) connected with the main heat line provided in the non-display area.
Regarding claim 5, fig. 10 of Choi discloses wherein the main heat line is provided on the substrate, in a floating state.
Regarding claim 10, fig. 10 of Choi discloses wherein the heat line includes at least two auxiliary heat lines (310 and 330) electrically connected with each other (310 and 330 are in direct contact and therefore electrically connected), and wherein the heat line hole includes auxiliary heat line holes (region occupied by 310/330) corresponding to the auxiliary heat lines.
Regarding claim 11, fig. 10 of Choi discloses wherein the auxiliary heat lines exposed through the auxiliary heat line holes are covered by the encapsulation layer (103 is a type of encapsulation layer).
Regarding claims 17-19, figs. 1, 9-10 of Choi discloses a light emitting display device, comprising:
a substrate divided into a display area and a non-display area surrounding the display area;
a pixel driving circuit layer provided on the substrate and including a driving transistor;
a planarization layer covering the pixel driving circuit layer;
at least one anode electrode provided on the planarization layer in pixels;
banks disposed between the at least one anode electrode;
a light emitting layer disposed on the at least one anode electrode and the banks;
a cathode electrode disposed on the light emitting layer;
a capping layer covering the cathode electrode;
an encapsulation layer provided on side surfaces and an upper surface of the capping layer;
a foreign matter blocking area disposed in the non-display area where the light emitting layer and the cathode electrode are disconnected and surrounding the display area; and
an undercut area (undercut of 211 in fig. 7 which include hole in 211 above 221 and around 221) provided along the foreign matter blocking area, wherein a side surface of the light emitting layer provided in the undercut area is covered by the cathode electrode, and
wherein the foreign matter blocking area is disposed between respective opposing disconnected portions of the light emitting layer and the cathode electrode and does not overlap with the light emitting layer and the cathode electrode in a plan view (this is necessary the case – see fig. 1);
wherein the undercut area is provided along the foreign matter blocking area in the display area;
wherein the undercut area is provided between the display area and the foreign matter blocking area;
wherein the undercut area includes at least one of a pixel driving circuit layer 211, a planarization layer 211, a bank (region of 211 forming the hole is a bank), an anode electrode 223 and a light emitting layer 222 is patterned.
Choi discloses an encapsulation substrate attached on the capping layer through the encapsulation layer.
However, fig. 2 of Chung discloses a light emitting display device, comprising:
a substrate 140 divided into a display area and a non-display area surrounding the display area;
a pixel driving circuit layer disposed on the substrate and including a driving transistor TFT;
a planarization layer 19 covering the pixel driving circuit layer;
at least one anode electrode provided on the planarization layer in pixels;
banks 21 disposed between the at least one anode electrode;
a light emitting layer disposed on the at least one anode electrode and the banks;
a cathode electrode disposed on the light emitting layer;
an encapsulation layer 30 on side surface of the cathode electrode;
an encapsulation substrate 150 attached on the cathode electrode through the encapsulation layer.
In view of such teaching, it would have been obvious to form device of Choi further comprising an encapsulation substrate attached on the capping layer through the encapsulation layer such as taught by Chung in order to form an upper sealing structure and prevents moisture from flowing into the organic light emitting unit from the outside.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893
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