Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to the Amendment filed on 01/06/2026. In the instant Amendment, claims 1, 3, 11, 13, 15, 19 and 20 were amended; claims 1, 11 and 20 are independent claims. Claims 1-20 are pending in this application.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/06/2026 has been entered.
Response to Arguments
Claim interpretation under 35 U.S.C. 112(f) has been maintained.
Applicant’s arguments with respect to claim(s) 1, 11 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments filed 01/06/2026 have been fully considered but they are not persuasive.
Applicant argues (on pages 7-8); that the cited prior art fails to explicitly disclose or suggest “detecting, by a probe filter, an access request using a first encryption key to a specific memory address; identifying, by the probe filter, a second encryption key that is associated with the specific memory address; detecting, by the probe filter, that the second encryption key mismatches the first encryption key; and evicting, by the probe filter in response to the mismatch, the second encryption key,” in regard to claim 1. Similar amendments were made to claims 11 and 20.
The Examiner respectfully disagrees with the applicant. Shanbhogue discloses detecting by a snoop filter an access request using an encryption key to a specific memory address (See Shanbhogue, [0040], [0061], [0155]; also see [0049], [0035]). Shanbhogue discloses identifying by the snoop filter a second encryption key that is associated with the specific memory address (See Shanbhogue, [0048], [0030], [0035]; also see [0124], [0155], [0049]). Shanbhogue discloses detecting by a snoop filter that the second encryption key mismatches the first encryption key (See Shanbhogue, [0030], [0035], [0124]; also see [0126], [0025]). Shanbhogue discloses invalidating [evicting] by the snoop filter in response to the mismatch the second encryption key (See Shanbhogue, [0029], [0030], [0124]; also see [0068], [0126], [0025], [0035]). Salisbury discloses an eviction buffer mechanism by which a snoop filter performs eviction in response to a mismatch (See Salisbury, [0071]-[0073]).
Applicant's arguments (page 10): Additionally, as to the dependent claims 2-10 and 12-19 the Applicant argues that the claims are dependent directly or indirectly from a respective one of claims of independent claims 1, 11 and 20 and are therefore distinguished from the cited art at least by virtue OR allowable at least based on of their additionally recited patentable subject matter.
The Examiner disagrees with the Applicant. The Examiner respectfully submits that dependent claims 2-10 and 12-19 are rejected at least based on the rationale and resource presented to the argument for their respective based claims, and the reference applied to the dependent claims 2-10 and 12-19.
Therefore, in view of the above reasons, the Examiner maintains the rejection with the cited prior art references.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: a detector that detects [] (Claims 11 & 20); a verifier that identifies [] (Claims 11 & 20) and an evictor that evicts [] (Claims 11, 13 & 20); probe filter being configured to evict [] (Claims 15 and 19); cache hierarchy is configured to [] (Claim 17).
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5, 9-11, 14-15, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Shanbhogue et al (“Shanbhogue,” US 20200202012) and further in view of Salisbury et al (“Salisbury,” US 20160062890).
Regarding claim 1, Shanbhogue discloses a method comprising:
detecting, by a probe filter, an access request using a first encryption key to a specific memory address; (Shanbhogue discloses detecting, by a probe filter [0030], an access request [0061], [0049] using a first encryption key [0155], [0035] to a specific memory address [0155], [0049])
identifying, by the probe filter, a second encryption key that is associated with the specific memory address; (Shanbhogue discloses identifying [0048], [0124], by the probe filter [0030], a second encryption key [0035] that is associated with the specific memory address [0155], [0049])
detecting, by the probe filter, that the second encryption key mismatches the first encryption key; (Shanbhogue discloses detecting, by the probe filter [0030], that the second encryption key [0035] mismatches the first encryption key [0124], [0126], [0025])
and evicting, by the probe filter in response to the mismatch, the second encryption key, (Shanbhogue discloses and invalidating [evicting] [0029], [0068] by the probe filter [0030] in response to the mismatch [0029]-[0030], the second encryption key [0124], [0126], [0025], [0035])
Shanbhogue fails to explicitly disclose and evicting, by the probe filter in response to the mismatch
However, in an analogous art, Salisbury discloses and evicting, by the probe filter in response to the mismatch, (Salisbury discloses [0071]-[0073] and evicting, by the snoop filter [probe filter] in response to the mismatch)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine teachings of Salisbury with method/system of Shanbhogue to include and evicting, by the probe filter in response to the mismatch. One would have been motivated to provide a snoop filter capable of performing coherency control operations for transactions received by the interconnect from devices and determining transactions to be serviced by the devices based on the coherency control operations (Salisbury, [0010]).
Regarding claim 3, Shanbhogue and Salisbury disclose the method of claim 1.
Shanbhogue further discloses wherein the probe filter implements a table to track which encryption keys are assigned to which specific memory addresses, and evicting the second encryption key includes evicting references to the second encryption key from the table, (Shanbhogue discloses wherein the probe filter [0030] implements a table [0115], [0067]-[0068], to track [0048] which encryption keys [0124], [0126], [0025], [0035] are assigned to which specific memory addresses [0070], [0126] and evicting [0029], [0068] the second encryption key [0124], [0126], [0025], [0035] includes evicting references [0029], [0068] to the second encryption key [0124], [0126], [0025], [0035]) from the table [0115], [0067]-[0068])
Regarding claim 5, Shanbhogue and Salisbury discloses the method of claim 1.
Shanbhogue further discloses wherein evicting the second encryption key maintains either data coherence or data integrity, (Shanbhogue describes wherein evicting [0029], [0068] the second encryption key [0124], [0126], [0025], [0035] maintains either data coherence [0078], [0048] or data integrity [0022])
Regarding claim 9, Shanbhogue and Salisbury disclose the method of claim 1.
Shanbhogue further discloses wherein evicting the second encryption key is performed by issuing an invalidating probe, (Shanghogue discloses wherein evicting [0029], [0068] the second encryption key [0124], [0126], [0025], [0035] is performed by issuing an invalidating probe [0030], [0124], [0126])
Regarding claim 10, Shanbhogue and Salisbury disclose the method of claim 9.
Shanbhogue further discloses wherein the invalidating probe [0030], [0124], [0126]) invalidates all references to the second encryption key within a cache hierarchy corresponding to the probe filter, (Shanbhogue discloses wherein the invalidating probe invalidates all references [0030], [0124], [0126] to the second encryption key [0124], [0126], [0025], [0035] within a cache hierarchy [0051], [0079] corresponding to the probe filter [0030])
Regarding claim 11, Shanbhogue discloses a probe fitter comprising:
a detector that detects, with a coherent fabric interconnect, an access request using a new encryption key to a specific memory address of a cache hierarchy; (Shanbhogue discloses a detector that detects, with a coherent fabric interconnect [0033], [0026], [0094], an access request [0061], [0049] using a new encryption key [0124], [0126], [0025], [0035] to a specific memory address [0155], [0049] of a cache hierarchy [0051], [0079])
an access rights table that maps memory locations to encryption keys; (Shanbhogue discloses an access rights table [0115], [0067]-[0068] that maps memory locations [0124], [0126], [0025], [0035] to encryption keys [0124], [0126], [0025], [0035])
a verifier that identifies, by referencing the access rights table, a stale encryption key that is associated with the specific memory address and detects that the stale encryption key mismatches the new encryption key; (Shanbhogue discloses a verifier that identifies [0039], by referencing the access rights table [0115], [0067]-[0068], a old [stale] encryption key [0124], [0126], [0025], [0035] that is associated with the specific memory address [0070], [0126] and detects that the old [stale] encryption key [0124], [0126], [0025], [0035] mismatches the new encryption key [0124], [0126], [0025])
and an evictor that evicts, in response to the mismatch, the stale encryption key from the cache hierarchy, (Shanbhogue discloses and an invalidator that invalidates [evictor that evicts] [0029], [0068], in response to the mismatch [0029]-[0030], the stale encryption key [0124], [0126], [0025], [0035] from the cache hierarchy [0051], [0079])
Shanbhogue fails to explicitly disclose and an evictor that evicts, in response to the mismatch from the cache hierarchy
However, in an analogous art, Salisbury discloses and an evictor that evicts, in response to the mismatch from the cache hierarchy, (Salisbury discloses [0071]-[0073] and evicting, by the snoop filter [probe filter] in response to the mismatch from the cache hierarchy)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine teachings of Salisbury with method/system of Shanbhogue to include and an evictor that evicts, in response to the mismatch from the cache hierarchy. One would have been motivated to provide a snoop filter capable of performing coherency control operations for transactions received by the interconnect from devices and determining transactions to be serviced by the devices based on the coherency control operations (Salisbury, [0010]).
Regarding claim 14, Shanbhogue and Salisbury disclose the probe filter of claim 11.
Shanbhogue further discloses wherein the probe filter is coupled to a memory controller that performs encryption or decrypting of data for the specific memory address, (Shanbhogue, [0038]-[0039], [0126], [0155] describes a snoop filter [probe filter] is coupled to a memory controller that performs encryption or decryption of data for the particular memory address)
Regarding claim 15, Shanbhogue and Salisbury disclose the probe filter of claim 11.
Shanbhogue further discloses wherein the probe filter being configured to evict the stale encryption key from the cache hierarchy maintains wither data coherence or data integrity, (Shanbhogue, [0028], [0068], [0132] describe wherein the snoop filter [probe filter] is configured to remove invalid [stale] encryption keys as described in [0064] & [0035] from the [0122], cache hierarchy; [0022], describes maintains data integrity; [0078] describes data coherence)
Regarding claim 19, Shanbhogue and Salisbury disclose the probe filter of claim 11.
Shanbhogue further discloses wherein the probe filter is configured to evict the references to the stale encryption key from the cache hierarchy at least in part by issuing an invalidating probe, (Shanbhogue, [0028], [0068], [0132] describe wherein the snoop filter [probe filter] is configured to remove invalid [stale] encryption keys as described in [0064] & [0035] from the [0122], [0079] cache hierarchy; [0063] describes issuing an invalidating probe)
Regarding claim 20, Yeo discloses a computer chip comprising:
a detector that detects, within a coherent fabric interconnect, an access request using a new encryption key to a specific memory address of a cache hierarchy; (Shanbhogue discloses a detector that detects, within a coherent fabric interconnect [0033], [0026], [0094], an access request [0061], [0049] using a new encryption key [0124], [0126], [0025], [0035] to a specific memory address [0155], [0049] of a cache hierarchy [0051], [0079])
an access rights table that maps memory locations to encryption keys; (Shanbhogue discloses an access rights table [0115], [0067]-[0068] that maps memory locations [0124], [0126], [0025], [0035] to encryption keys [0124], [0126], [0025], [0035])
a verifier that identifies, by referencing the access rights table, a stale encryption key that is associated with the specific memory address and detects that the stale encryption key mismatches the new encryption key; (Shanbhogue discloses a verifier that identifies [0039], by referencing the access rights table [0115], [0067]-[0068], a stale encryption key [0124], [0126], [0025], [0035] that is associated with the specific memory address [0070], [0126] and detects that the stale encryption key [0124], [0126], [0025], [0035] mismatches [0029]-[0030] the new encryption key [0124], [0126], [0025])
and an evictor that evicts, in response to the mismatch, the stale encryption key from the access rights table, (Shanbhogue discloses and an invalidator that invalidates [evictor that evicts] [0029], [0068], in response to the mismatch [0029]-[0030], the stale encryption key [0124], [0126], [0025], [0035] from the access rights table [0115], [0067]-[0068])
Shanbhogue fails to explicitly disclose and an evictor that evicts, in response to the mismatch.
However, in an analogous art, Salisbury discloses and an evictor that evicts, in response to the mismatch, (Salisbury discloses [0071]-[0073] and evicting, by the snoop filter [probe filter] in response to the mismatch)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine teachings of Salisbury with method/system of Shanbhogue to include and an evictor that evicts, in response to the mismatch. One would have been motivated to provide a snoop filter capable of performing coherency control operations for transactions received by the interconnect from devices and determining transactions to be serviced by the devices based on the coherency control operations (Salisbury, [0010]).
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Shanbhogue et al (“Shanbhogue,” US 20200202012) in view of Salisbury et al (“Salisbury,” US 20160062890) and further in view of Fel et al (“Fel,” US 20150220456).
Regarding claim 2, Shanbhogue and Salisbury disclose the method of claim 1.
Shanbhogue and Salisbury fail to explicitly disclose wherein data is stored within a cache hierarchy in an unencrypted state by decrypting the data prior to storage.
However, in an analogous art, Fel discloses wherein data is stored within a cache hierarchy in an unencrypted state by decrypting the data prior to storage (Fel, [0015]-[0016], [0024] and [0126] describe wherein information is stored within a cache hierarchy in an unencrypted state by decrypting the information prior to storing it in storage).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Fel with Shanbhogue and Salisbury to include wherein data is stored within a cache hierarchy in an unencrypted state by decrypting the data prior to storage. One would have been motivated to provide protection of program code intended to be executed by a microprocessor which makes program code less sensitive to attacks (Fel, [0002]).
Regarding claim 12, Shanbhogue and Salisbury disclose the probe filter of claim 11.
Shanbhogue and Salisbury fail to explicitly disclose wherein data is stored within the cache hierarchy in an unencrypted state.
However, in an analogous art, Fel discloses wherein data is stored within the cache hierarchy in an unencrypted state, (Fel, [0015]-[0016], [0024] & [0126] describe wherein information is stored within the cache hierarchy in an unencrypted state)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Fel with Shanbhogue and Salisbury to include wherein data is stored within the cache hierarchy in an unencrypted state. One would have been motivated to provide protection of program code intended to be executed by a microprocessor which makes program code less sensitive to attacks (Fel, [0002]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Shanbhogue et al (“Shanbhogue,” US 20200202012) in view of Salisbury et al (“Salisbury,” US 20160062890) and further in view of Altman et al (“Altman,” US 20150089245).
Regarding claim 4, Shanbhogue and Salisbury disclose the method of claim 1.
Shanbhogue and Salisbury fail to explicitly disclose wherein encrypting or decrypting an item of data is performed by a memory controller.
However, in an analogous art, Altman discloses wherein encrypting or decrypting an item of data is performed by a memory controller, (Altman, [0012], describes wherein encrypting an item of data is performed by a memory controller)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Altman with Shanbhogue and Salisbury to include wherein encrypting or decrypting an item of data is performed by a memory controller. One would have been motivated to provide secure use of persistent (non-volatile) memory to emulate volatile memory (Altman, [0001]).
Claims 6-7 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Shanbhogue et al (“Shanbhogue,” US 20200202012) in view of Salisbury et al (“Salisbury,” US 20160062890) and further in view of Roberts et al (“Roberts,” US 20230058668)
Regarding claim 6, Shanbhogue and Salisbury discloses the method of claim 1.
Shanbhogue and Salisbury fail to explicitly disclose wherein an attempt to access the specific memory address using an encryption key not currently associated with the specific memory address results in a cache miss.
However, in an analogous art, Roberts discloses wherein an attempt to access the specific memory address using an encryption key not currently associated with the specific memory address results in a cache miss, (Roberts, [0056], [0058], [0064] describes an attempt to access a particular memory address using an encryption key that is not currently associated with the particular memory address results in a cache miss)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Roberts with Shanbhogue and Salisbury to include wherein an attempt to access the specific memory address using an encryption key not currently associated with the specific memory address results in a cache miss. One would have been motivated to provide a selective cache line memory encryption (Roberts, [0091])
Regarding claim 7, Shanbhogue and Salisbury discloses the method of claim 6.
Shanbhogue and Salisbury fail to explicitly disclose wherein an attempt to access the specific memory address using an encryption key not currently associated with the specific memory address results in a cache miss without detection of a failed write operation.
However, in an analogous art, Roberts discloses wherein an attempt to access the specific memory address using an encryption key not currently associated with the specific memory address results in a cache miss without detection of a failed write operation, (Roberts, [0056], [0058], [0064] describes an attempt to access a particular memory address using an encryption key that is not currently associated with the particular memory address results in a cache miss without detection of a failed write)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Roberts with Shanbhogue and Salisbury to include wherein an attempt to access the specific memory address using an encryption key not currently associated with the specific memory address results in a cache miss without detection of a failed write operation. One would have been motivated to provide a selective cache line memory encryption (Roberts, [0091])
Regarding claim 16, Shanbhogue and Salisbury disclose the probe filter of claim 11.
Shanbhogue and Salisbury fail to explicitly disclose wherein the cache hierarchy is configured such that an attempt to access the specific memory address using an encryption key not currently associated with the specific memory address results in a cache miss.
However, in an analogous art, Roberts discloses wherein the cache hierarchy is configured such that an attempt to access the specific memory address using an encryption key not currently associated with the specific memory address results in a cache miss, (Roberts, [0079] memory hierarchy with lower level caches; [0056], [0058], [0064] describes an attempt to access a particular memory address using an encryption key that is not currently associated with the particular memory address results in a cache miss)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Roberts with Shanbhogue and Salisbury to include wherein the cache hierarchy is configured such that an attempt to access the specific memory address using an encryption key not currently associated with the specific memory address results in a cache miss. One would have been motivated to provide a selective cache line memory encryption (Roberts, [0091])
Regarding claim 17, Shanbhogue and Salisbury disclose the probe filter of claim 16.
Shanbhogue and Salisbury fail to explicitly disclose wherein the cache hierarchy is configured such that an attempt to access the specific memory address using an encryption key not currently associated with the specific memory address results in a cache miss without detection of a failed write operation.
However, in an analogous art, Roberts discloses wherein the cache hierarchy is configured such that an attempt to access the specific memory address using an encryption key not currently associated with the specific memory address results in a cache miss without detection of a failed write operation, (Roberts, [0079] memory hierarchy with lower level caches; [0056], [0058], [0064] describes an attempt to access a particular memory address using an encryption key that is not currently associated with the particular memory address results in a cache miss without detection of a failed write)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Roberts with Shanbhogue and Salisbury to include wherein the cache hierarchy is configured such that an attempt to access the specific memory address using an encryption key not currently associated with the specific memory address results in a cache miss without detection of a failed write operation. One would have been motivated to provide a selective cache line memory encryption (Roberts, [0091])
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Shanbhogue et al (“Shanbhogue,” US 20200202012) in view of Salisbury et al (“Salisbury,” US 20160062890) and further in view of Buendgen et al (“Buendgen,” US 20230040468).
Regarding claim 8, Shanbhogue and Salisbury disclose the method of claim 1.
Shanbhogue and Salisbury fail to explicitly disclose wherein usage of the first encryption key and the second encryption key facilitates achievement of confidential computing.
However, in an analogous art, Buendgen discloses wherein usage of the first encryption key and the second encryption key facilitates achievement of confidential computing, (Buendgen, [0054], describes the usage of encryption keys [first and second encryption keys] facilitates achievement of confidential computing)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Buendgen with Shanbhogue and Salisbury to include wherein usage of the first encryption key and the second encryption key facilitates achievement of confidential computing. One would have been motivated to provide a method for providing a system-specific secret to a computing system (Buendgen, [0001]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Shanbhogue et al (“Shanbhogue,” US 20200202012) in view of Salisbury et al (“Salisbury,” US 20160062890) and further in view of Shveykin et al (“Shveykin,” US 20180054302).
Regarding claim 13, Shanbhogue and Salisbury disclose the probe filter of claim 11.
Shanbhogue and Salisbury fail to explicitly disclose wherein the evictor is configured to evict the stale encryption key in the cache hierarchy by evicting all such references within the cache hierarchy.
However, in an analogous art, Shveykin discloses wherein the evictor is configured to evict the stale encryption key in the cache hierarchy by evicting all such references within the cache hierarchy, (Shveykin, [0033], [0036] describes revoking the expired [stale] encryption key in a cache hierarchy by revoking all such references within the cache hierarchy)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Shveykin with Shanbhogue and Salisbury to include wherein the evictor is configured to evict the stale encryption key in the cache hierarchy by evicting all such references within the cache hierarchy. One would have been motivated to provide a message service with distributed key caching for server-side encryption (Shveykin, [0012]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Shanbhogue et al (“Shanbhogue,” US 20200202012) in view of Salisbury et al (“Salisbury,” US 20160062890) and further in view of Kumar et al (“Kumar,” US 20210110049).
Regarding claim 18, Shanbhogue and Salisbury disclose the probe filter of claim 11.
Chabbra further discloses the coherent fabric interconnect (Chabbra, [0061] describes a coherent fabric interconnect)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chabbra with Shanbhogue and Salisbury to include the coherent fabric interconnect. One would have been motivated to provide a functionality to protect memory (Chabbra, [0001]).
Shanbhogue, Salisbury and Chabbra fail to explicitly disclose wherein usage of the new encryption key and the stale encryption key facilitates achievement of confidential computing with respect to the fabric interconnect.
However, in an analogous art, Kumar discloses wherein usage of the new encryption key and the stale encryption key facilitates achievement of confidential computing with respect to the fabric interconnect (Kumar, [0033], [0050], describes usage of the new encryption key and the expired [stale] encryption key that facilitates [0037] confidential computing with respect to the [0022], [0119] fabric interconnect)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kumar with Shanbhogue and Salisbury to include wherein usage of the new encryption key and the stale encryption key facilitates achievement of confidential computing with respect to the fabric interconnect. One would have been motivated to provide a method and system of storing both public and private data (Kumar, [0003]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES J WILCOX whose telephone number is (571)270-3774. The examiner can normally be reached M-F: 8 A.M. to 5 P.M..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Luu T. Pham can be reached on (571)270-5002. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES J WILCOX/Examiner, Art Unit 2439
/LUU T PHAM/Supervisory Patent Examiner, Art Unit 2439