DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 09/25/2025 has been entered. Claims 13, 15-20, 23-27 and 61-67 are currently pending. Applicant’s amendments have overcome the drawing objections, specification objections and some of the 35 USC 112 rejections previously set forth in the Non-Final Office Action mailed 07/08/2025.
Claim Objections
Claim 20 is objected to because of the following informalities:
Claim 20: “the first planar grid antenna and the second planar grid antenna are spaced apart and wherein the second planar grid antenna is more interior with respect to a surface of the 3-D integrated circuit then the first planar grid antenna” should read “the first planar grid antenna and the second planar grid antenna are spaced apart and wherein the second planar grid antenna is more interior with respect to a surface of the 3-D integrated circuit than the first planar grid antenna”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 20 and 61 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The specification does not support this limitation “the second planar grid antenna is more interior with respect to a surface of the 3-D integrated circuit then the first planar grid antenna”. Para [0081] only mentions the first and second grid antennas 702, 704 which are sensitive to vertically polarized and horizontally polarized signals respectively but the spec does not specify the location or orientation of the first and second grid antennas, in particular the second planar grid antenna 704 has be more interior to a surface of the 3-D integrated circuit than the first planar grid antenna 702.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13, 15-20, 23-27 and 61-67 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation "each combinable co-fabricated antenna element including at least one internally co-fabricated antenna element” in lines 4-5 which renders the claim indefinite. It is not clear how two combinable co-fabricated antenna elements, each of them including at least one internally co-fabricated antenna element could form a first and second planar grid antennas later on. Based on fig. 7, Examiner thinks each combinable co-fabricated antenna element should include at least four internally co-fabricated antenna elements (2 internally co-fabricated antenna elements for the first grid antenna 702 and 2 internally co-fabricated antenna elements for the second grid antenna 704).
Claim 13 recites the limitation "wherein each of the at least two integrated circuits of the stack of integrated circuits includes at least one surface having one or more bonding pads electrically connected to a corresponding internally co-fabricated antenna element of the at least one internally co-fabricated antenna elements within the integrated circuit” in lines 6-9 which renders the claim indefinite. The integrated circuit cannot include one bonding pad because each bonding pad will be connected to a corresponding internally co-fabricated antenna element and there are a plurality of internally co-fabricated antenna elements, at least four to form the first and second grid antennas. For the purpose of examination, Examiner interprets the claim as “having at least four or more bonding pads”.
Claim 13 recites the limitation " wherein the at least one internally co-fabricated antenna element of the at least two integrated circuits of the stack of integrated circuits are electrically coupled together by alignment and bonding of the one or more bonding pads of the at least two integrated circuits of the stack of integrated circuits, such that the at least two integrated circuits of the stack of integrated circuits comprise a set of electrically coupled integrated circuits” in lines 10-15 which renders the claim indefinite. It is not clear what these electrically coupled integrated circuits are. It is not clear if they are same to the at least two integrated circuits because the at least two integrated circuits are also electrically coupled together through the bonding pads recited previously. For the purpose of examination, Examiner interprets the claim as best understood.
Claim 13 recites the limitation "wherein the set of electrically coupled integrated circuits includes (1) a first plurality of internally co-fabricated antenna elements fabricated as a first planar grid antenna having a primarily first orientation, and (2) a second plurality of internally co-fabricated antenna elements fabricated as a second planar grid antenna having a primarily second orientation" in lines 16-20 which renders the claim indefinite. It is not clear what these internally co-fabricated antenna elements are. It is not clear how they relate to the at least one internally co-fabricated antenna element of each combinable co-fabricated antenna element/at least two integrated circuits previously recited.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. The omitted elements are: feeding or the electrical connection to make the polarization happen. The dual polarization cannot be obtained without the electrical connection 310 in fig. 3D, 3E that supplying polarization signals to the planar grid antennas.
Similar rejection would be applied to claims 20 and 61.
Claims 15-19, 23-27 and 62-67 inherit the indefiniteness of claims 13, 20 and 61 and are subsequently rejected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 13 and 15-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Karikalan et al, US-20240039141-A1 (hereinafter Karikalan).
Regarding claim 13, as best understood, Karikalan discloses the following:
a 3-D integrated circuit, the 3-D integrated circuit (305/505, figs. 3, 5) including a stack of integrated circuits (310a-310n),
wherein at least two integrated circuits of the stack of integrated circuits are combinable co-fabricated antenna elements (305/505), each combinable co-fabricated antenna element including at least one internally co-fabricated antenna element (515a-515b, 530a-530n, fig. 5),
wherein each of the at least two integrated circuits of the stack of integrated circuits includes at least one surface having one or more bonding pads electrically connected to a corresponding internally co-fabricated antenna element of the at least one internally co-fabricated antenna elements within the integrated circuit (para [0047]: each of the plurality of antenna array elements 330 is an internal conductive layer (e.g., metallization layer) of a respective TSV 325 and a conductive pad, wire, pillar, or other structure may be Cu—Cu bonded to the internal metallization layers of the respective individual TSVs, coupling the individual TSVs),
wherein the at least one internally co-fabricated antenna elements element of the at least two integrated circuits of the stack of integrated circuits are electrically coupled together by alignment and bonding of the one or more bonding pads of the at least two integrated circuits of the stack of integrated circuits (figs. 3, 5, para [0047]), such that the at least two integrated circuits of the stack of integrated circuits comprise a set of electrically coupled integrated circuits (figs. 3, 5, para [0047]),
wherein the set of electrically coupled integrated circuits includes (1) a first plurality of internally co-fabricated antenna elements (515a-515n) fabricated as a first planar grid antenna (510) having a primarily first orientation, and (2) a second plurality of internally co-fabricated antenna elements (530a-530n) fabricated as a second planar grid antenna having a primarily second orientation (525),
wherein the first orientation is different from the second orientation (fig. 5), and
wherein the first planar grid antenna and the second planar grid antenna are spaced apart from each other (fig. 5) in a dual polarization configuration (fig. 5: the first and second planar grid antenna 510, 525 have different orientation, therefore the polarization directions of them would be different, i.e. dual polarization).
Regarding claim 15, Karikalan discloses wherein at least one integrated circuit of the stack of integrated circuits (310a-310n, fig. 3) includes an active circuitry region (315, para [0049]: the transceiver circuit, or part of the transceiver circuit may be implemented as an RFIC. In some examples, an IP core 315 of a die layer 310a-310n may include all or part of an RFIC).
Regarding claim 16, Karikalan discloses wherein the active circuitry region includes an active layer containing multiple transistors (para [0031]: the active circuitry region 115/315 containing multiple transistors).
Regarding claim 17, Karikalan discloses wherein at least one integrated circuit of the stack of integrated circuits includes an active circuitry region (fig. 5 reproduced below) defining a plane extending perpendicular to the first planar grid antenna (510) and the second planar grid antenna (525).
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Regarding claim 18, Karikalan discloses wherein at least one integrated circuit of the stack of integrated circuits includes a radio frequency circuit (315, fig. 3, para [0049]), wherein the radio frequency circuit (315) is electrically coupled to at least one of the one or more combinable co-fabricated antenna elements (para [0038]: interconnects 220/320 connecting the radio frequency circuit 215/315 to the antenna elements 225/325).
Regarding claim 19, Karikalan discloses at least one integrated circuit of the stack of integrated circuits includes an embedded die package (315, fig. 3) electrically coupled to at least one of the one or more combinable co-fabricated radio frequency antenna elements (para [0038]: interconnects 220/320 connecting the embedded die package 215/315 to the antenna elements 225/325).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 20, 23-27 and 61-67 are rejected under 35 U.S.C. 103 as being unpatentable over Karikalan, US-20240039141-A1 in view of Pu et al, US-20200067188-A1 (hereinafter Pu).
Regarding claim 20, as best understood, Karikalan discloses the following:
a 3-D integrated circuit, the 3-D integrated circuit (305/505, figs. 3, 5) including a stack of integrated circuits (310a-310n),
wherein at least two integrated circuits of the stack of integrated circuits are combinable co-fabricated antenna elements (305/505), each combinable co-fabricated antenna element including at least one internally co-fabricated antenna element (515a-515b, 530a-530n, fig. 5),
wherein each of the at least two integrated circuits of the stack of integrated circuits includes at least one surface having one or more bonding pads electrically connected to a corresponding internally co-fabricated antenna element of the at least one internally co-fabricated antenna elements within the integrated circuit (para [0047]: each of the plurality of antenna array elements 330 is an internal conductive layer (e.g., metallization layer) of a respective TSV 325 and a conductive pad, wire, pillar, or other structure may be Cu—Cu bonded to the internal metallization layers of the respective individual TSVs, coupling the individual TSVs),
wherein the at least one internally co-fabricated antenna elements element of the at least two integrated circuits of the stack of integrated circuits are electrically coupled together by alignment and bonding of the one or more bonding pads of the at least two integrated circuits of the stack of integrated circuits (figs. 3, 5, para [0047]), such that the at least two integrated circuits of the stack of integrated circuits comprise a set of electrically coupled integrated circuits (figs. 3, 5, para [0047]),
wherein the set of electrically coupled integrated circuits includes (1) a first plurality of internally co-fabricated antenna elements (515a-515n) fabricated as a first planar grid antenna (510) having a primarily first orientation, and (2) a second plurality of internally co-fabricated antenna elements (530a-530n) fabricated as a second planar grid antenna (525) having a primarily second orientation, and
wherein the first planar grid antenna and the second planar grid antenna are spaced apart (fig. 5).
Karikalan does not disclose wherein the second planar grid antenna is more interior with respect to a surface of the 3-D integrated circuit then the first planar grid antenna.
Although Karikalan does not disclose wherein the first planar grid antenna is most sensitive to radio frequency signals having a vertical polarization and the second planar grid antenna is most sensitive to radio frequency signals having a horizontal polarization, Karikalan discloses the first planar grid antenna 510 may thus be configured to emit a wireless signal having the first radiation pattern 520 and the second planar grid antenna 525 may be configured to emit a wireless signal having a second radiation pattern 535 (fig. 5, para [0061]), one of ordinary skill in the art would know that they would have different polarization.
Pu suggests wherein the second planar grid antenna is more interior with respect to a surface of the 3-D integrated circuit then the first planar grid antenna (fig. 4, para [0046]), and
wherein the first planar grid antenna (224, figs. 3-4) is most sensitive to radio frequency signals having a vertical polarization (para [0042]) and the second planar grid antenna (222) is most sensitive to radio frequency signals having a horizontal polarization (para [0042]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the first and second planar grid antennas taught in Karikalan to be sensitive to vertical and horizontal polarization signals as suggested in Pu as claimed or the purpose of improving the antennas performance (Pu, para [0003]).
Regarding claim 23, Karikalan discloses wherein at least one integrated circuit of the stack of integrated circuits (310a-310n, fig. 3) includes an active circuitry region (315, para [0049]: the transceiver circuit, or part of the transceiver circuit may be implemented as an RFIC. In some examples, an IP core 315 of a die layer 310a-310n may include all or part of an RFIC).
Regarding claim 24, Karikalan discloses wherein the active circuitry region includes an active layer containing multiple transistors (para [0031]: the active circuitry region 115/315 containing multiple transistors).
Regarding claim 25, Karikalan discloses at least one integrated circuit of the stack of integrated circuits includes an active circuitry region (fig. 5 reproduced above) defining a plane extending perpendicular to the first planar grid antenna (510) and the second planar grid antenna (525).
Regarding claim 26, Karikalan discloses wherein at least one integrated circuit of the stack of integrated circuits includes a radio frequency circuit (315, fig. 3, para [0049]), wherein the radio frequency circuit (315) is electrically coupled to at least one of the one or more combinable co-fabricated antenna elements (para [0038]: interconnects 220/320 connecting the radio frequency circuit 215/315 to the antenna elements 225/325).
Regarding claim 27, Karikalan discloses wherein at least one integrated circuit of the stack of integrated circuits includes an embedded die package (315, fig. 3) electrically coupled to at least one of the one or more combinable co-fabricated radio frequency antenna elements (para [0038]: interconnects 220/320 connecting the embedded die package 215/315 to the antenna elements 225/325).
Regarding claim 61, as best understood, Karikalan discloses the following:
a 3-D integrated circuit, the 3-D integrated circuit (305/505, figs. 3, 5) including a stack of integrated circuits (310a-310n),
wherein at least two integrated circuits of the stack of integrated circuits are combinable co-fabricated radio frequency antenna elements (305/505), each combinable co- fabricated antenna element including at least one internally co-fabricated radio frequency antenna element (515a-515b, 530a-530n, fig. 5),
wherein each of the at least two integrated circuits of the stack of integrated circuits includes at least one surface having one or more bonding pads electrically connected to a corresponding internally co-fabricated radio frequency antenna element of the at least one internally co-fabricated radio frequency antenna elements within the integrated circuit (para [0047]: each of the plurality of antenna array elements 330 is an internal conductive layer (e.g., metallization layer) of a respective TSV 325 and a conductive pad, wire, pillar, or other structure may be Cu—Cu bonded to the internal metallization layers of the respective individual TSVs, coupling the individual TSVs),
wherein the at least one internally co-fabricated radio frequency antenna elements of at least two integrated circuits of the stack of integrated circuits are electrically coupled together by alignment and bonding of the one or more bonding pads of the at least two integrated circuits of the stack of integrated circuits (figs. 3, 5, para [0047]), such that the at least two integrated circuits of the stack of integrated circuits comprise a set of electrically coupled integrated circuits (figs. 3, 5, para [0047]),
wherein the set of electrically coupled integrated circuits includes (1) a first plurality of internally co-fabricated radio frequency antenna elements (515a-515n) extending in a first direction to form a first planar grid antenna (510), and (2) a second plurality of internally co-fabricated radio frequency antenna elements (530a-530n) extending in a second direction to form a second planar grid antenna (525),
wherein the first planar grid antenna and the second planar grid antenna are spaced apart (fig. 5) and wherein the first planar grid antenna is most sensitive to radio frequency signals having a first polarization and the second planar grid antenna is most sensitive to radio frequency signals having a second polarization (fig. 5: the first and second planar grid antenna 510, 525 have different orientation, therefore they would be sensitive to first and second polarized signals).
Karikalan does not disclose wherein the second planar grid antenna is more interior with respect to a surface of the 3-D integrated circuit then the first planar grid antenna.
Pu suggests wherein the second planar grid antenna is more interior with respect to a surface of the 3-D integrated circuit then the first planar grid antenna (fig. 4, para [0046]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide second planar grid antenna taught in Karikalan to be more interior with respect to a surface of the 3-D integrated circuit then the first planar grid antenna as suggested in Pu as claimed or the purpose of having a desired polarization signals radiating more powerful signal towards the outside environment depending on the requirement of the application.
Regarding claim 62, Karikalan discloses wherein at least one integrated circuit of the stack of integrated circuits (310a-310n, fig. 3) includes an active circuitry region (315, para [0049]: the transceiver circuit, or part of the transceiver circuit may be implemented as an RFIC. In some examples, an IP core 315 of a die layer 310a-310n may include all or part of an RFIC).
Regarding claim 63, Karikalan discloses wherein the active circuitry region includes an active layer containing multiple transistors (para [0031]: the active circuitry region 115/315 containing multiple transistors).
Regarding claim 64, Karikalan discloses wherein at least one integrated circuit of the stack of integrated circuits includes an active circuitry region (fig. 5 reproduced above) defining a plane extending perpendicular to the first planar grid antenna (510) and the second planar grid antenna (525).
Regarding claim 65, Karikalan discloses wherein at least one integrated circuit of the stack of integrated circuits includes a radio frequency circuit (315, fig. 3, para [0049]), wherein the radio frequency circuit (315) is electrically coupled to at least one of the one or more combinable co-fabricated antenna elements (para [0038]: interconnects 220/320 connecting the radio frequency circuit 215/315 to the antenna elements 225/325).
Regarding claim 66, Karikalan discloses wherein at least one integrated circuit of the stack of integrated circuits includes an embedded die package (315, fig. 3) electrically coupled to at least one of the one or more combinable co-fabricated radio frequency antenna elements (para [0038]: interconnects 220/320 connecting the embedded die package 215/315 to the antenna elements 225/325).
Regarding claim 67, Karikalan does not disclose wherein the first direction and the second direction define an approximately 900 angle.
Pu suggests wherein the first direction and the second direction define an approximately 900 angle (fig. 4: horizontal and vertical direction).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrange the first and second directions taught in Karikalan to be approximately 900 as suggested in Pu as claimed or the purpose of providing vertical and horizontal signals to the antenna elements in order to improve the antennas performance (Pu, para [0003]).
Response to Arguments
Applicant's arguments filed 09/25/2025 regarding the rejections of claim 13 have been fully considered but they are not persuasive.
Applicant argued that “Karikalan does not teach or suggest a configuration of a first planar grid antenna and a second planar grid antenna as now claimed in independent claim 13, which encompass the embodiment shown in FIG. 7 of the present application. Such a configuration increases isolation between polarizations.
Karikalan's FIG. 5 teaches a configuration of stacked IC die packages in which a first antenna array 510 formed on a first side wall 540a has a first radiation pattern 520, and a second antenna array 525 formed on a second side wall 540b has a second radiation pattern 535. However, as one of ordinary skill in the art would know, the distinct (apparently orthogonal) radiation patterns taught by Karikalan does not teach or suggest a dual polarization ability.
Karikalan does not appear to even mention polarized antenna configurations or fabricating first and second planar grid antennas spaced apart in a dual polarization configuration. Accordingly, Karikalan does not anticipate the invention as now claimed in claims 13 and 15-19.”
Examiner respectfully disagree because Karikalan's FIG. 5 teaches a configuration of stacked IC die packages having first grid antenna 510 having first radiating direction, second grid antenna 525 having second radiating direction, one of ordinary skill in the art would understand that the first and second grid antennas 510, 525 would have first and second polarization, i.e. dual polarization.
Applicant's arguments filed 09/25/2025 regarding the rejections of claims 20 and 61 have been fully considered but they are not persuasive.
Applicant argued that “Claims 20, 23-27, and 61-67 stand rejected under 35 U.S.C. 103 as being unpatentable over Karikalan, US-20240039141-Al in view of Pu et al., US-20200067188-Al. Applicant respectfully traverses this rejection with respect to the claims as currently presented.
As admitted in the Office Action, "Karikalan does not disclose wherein the first planar grid antenna is most sensitive to radio frequency signals having a vertical polarization and the second planar grid antenna is most sensitive to radio frequency signals having a horizontal polarization."
Further, Karikalan requires that the antenna elements be exposed at a side wall (see, e.g., paras. 0014, 0015, 0033, 0039).
In contrast, the present invention does not require such exposure, which adds a significant step in IC fabrication. For example, FIGS. 2A shows that a section of internally co-fabricated antenna elements 232 can be interior to another section 230, and thus would not be exposed even if the more exterior section 230 is exposed (which it need not be for the present invention). Similarly, FIG. 7 shows that a first grid antenna 702 is fabricated with primarily vertical members, and a second antenna 704 is fabricated with primarily horizonal members and spaced apart (i.e., behind or more interior) from the first grid antenna 702 and thus would not be exposed.
Pu teaches a single substrate that includes separate horizontally polarized antenna and a vertically polarized antenna around the periphery of the substrate (Pu para. 0042). However, Pu's single substrate design results in the same problem that the present invention addresses (see specification para. 0008): as an RFFE IC die decreases in size, it may no longer be feasible to locate an RFFE IC on the same substrate as the associated antenna elements - in essence, the RFFE IC areas do not scale much with frequency while the antenna element size and spacing do, so that the total X- Y area of the RFFE ICs exceeds the X-Y area of the array of antenna elements.
In contrast, the claimed 3-D integrated circuit can include "large" RFFE IC's while maintaining grid antennas of much greater size and types than is possible to achieve on a single substrate. Moreover, no extra grinding or material removal is required to exposed all of the antennas, since at least one grid antenna is more interior with respect to a surface of the 3-D integrated circuit then the other grid antenna.
Thus, Karikalan teaches that a 3-D stack with antenna elements must expose those elements on the sides of the stack, and Pu teaches separately polarized antennas on the periphery of a single substrate. The combination of Karikalan and Pu only points to building IC antenna structures on the exposed sides of a 3-D stack. Missing from that combination is any teaching or suggestion to fabricate "... the first planar grid antenna and the second planar grid antenna ... spaced apart and wherein the second planar grid antenna is more interior with respect to a surface of the 3-D integrated circuit then the first planar grid antenna".
Accordingly, the combination of Karikalan and Pu fails to teach or suggest the invention as now claimed, or the advantages of that invention.”
Examiner respectfully disagree because of the following reasons:
First, Karikalan also uses the internal antenna elements 225 inside of the stack of integrated circuits/die layers 210 to form the grid antenna (fig. 2). Moreover, the present invention also shows the exposure of the grid antenna array 306 in fig. 3A. Although Applicant mentioned in the arguments about the invention does not require the complexity of the fabrication, “the claimed 3-D integrated circuit can include "large" RFFE IC's while maintaining grid antennas of much greater size and types”, but they are not required in the claim. The prior art still reads on the limitations recited in the claim.
Second, the substrate in Pu is not a single substrate, it comprises a plurality of dielectric layers 112 and metal layers 114, fig. 2 which are stacked together to form the vertical and horizontal polarization antennas 222, 224 in fig. 4. Pu discloses wherein the second planar grid antenna 222 (fig. 4, para [0046]) is more interior with respect to a surface of the 3-D integrated circuit then the first planar grid antenna 224.
Citation of Pertinent Art
Xu et al, CN-114843763-A, fig. 1 – vertical and horizontal grid antennas
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH N HO whose telephone number is (571)272-4657. The examiner can normally be reached M-F 8:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dameon Levi can be reached at (571)272-2105. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAMEON E LEVI/Supervisory Patent Examiner, Art Unit 2845
/ANH N HO/Examiner, Art Unit 2845