Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 3-6, 8, 11-14, 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 19-22 and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and resolve the 101 below.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 17-24 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) do not fall within at least one of the four categories of patent eligible subject matter because they aren’t directed towards patent eligible subject matter.
The specification ¶899 states, “Such electronic devices store and communicate (internally and/or with other electronic devices over a network) code and data using computer machine readable media, such as non-transitory computer machine-readable storage media (e.g., magnetic disks; optical disks; random access memory; read only memory; flash memory devices; phase-change memory) and transitory computer machine-readable communication media (e.g., electrical, optical, acoustical or other form of propagated signals - such as carrier waves, infrared signals, digital signals, etc.).”
See MPEP 2106.03, “Non-limiting examples of claims that are not directed to any of the statutory categories include: […]
Transitory forms of signal transmission (often referred to as “signals per se”), such as a propagating electrical or electromagnetic signal or carrier wave; and.”
Since the claims are not directed towards patent eligible subject matter they are rejected under 101.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 7, 9, 10, 15, 17, 18, 23 are rejected under 35 U.S.C. 103 as being unpatentable over Kulkarni et al. (Fused BVH to Ray Trace Level of Detail Meshes).
Regarding claim 1 Kulkarni teaches a […]graphics processor comprising (See page 2, 2.2 Fusing Mesh Cut in the Base LOD BVH col. 2 first 3 lines, “The last thing we need to do is refit the AABBs in the Base LOD BVH. The AABBs computed for the Base LOD BVH do not always enclose the subtree fused.” Computing carried out by a processor.):
a ray generator to generate a ray to be traversed through a bounding volume hierarchy (BVH) including at least one multi-level-of-detail (multi LoD) node comprising a first child node associated with a first LoD and a second child node associated with a second LoD, wherein the first LoD comprises a relatively coarser LoD than the second LoD (See title, “Fused BVH to Ray Trace Level of Detail Meshes” See abstract, “The paper presents different strategies for fusing Bounding Volume Hierarchies (BVHs) of varying level of detail (LODs). Our method makes it possible to traverse BVHs of varying LODs in a cache friendly way for path tracing. Considering BVH of the finest level (we call it the Base LOD BVH), the method defines a strategy to fuse subtrees from BVH of other LODs to the Base LOD BVH. Our method proposes a heuristic to find such subtrees in non-Base LOD BVHs and an algorithm to find fusion or insertion points for these subtrees in the Base LOD BVH without much increasing the overall the volume of the Base LOD BVH and the number of nodes traversed as a result of this fusing.” See page 1 col. 2, 2.1 Finding a Mesh Cut, “We start by finding subtrees forming a cut in LOD 1 BVH at decent depth. For this purpose, we introduce a threshold 𝑇 as a number of child nodes. We start traversing LOD 1 BVH until we reach a node with the number of child nodes less than or equal to 𝑇 . We add such a node to a mesh cut and continue traversal till we have visited all the nodes as shown in Fig 2. If we want a finer mesh cut, we can set 𝑇 =1. This 𝑇 will result in a mesh cut with all the triangle primitives.”);
traversal hardware logic to traverse the ray through the BVH, wherein upon reaching the multi-LoD node, the traversal hardware logic is to determine whether to continue traversal with the first child node or the second child node based on a comparison […](See page 1 col. 2, 2.1 Finding a Mesh Cut, “We start by finding subtrees forming a cut in LOD 1 BVH at decent depth. For this purpose, we introduce a threshold 𝑇 as a number of child nodes. We start traversing LOD 1 BVH until we reach a node with the number of child nodes less than or equal to 𝑇 . We add such a node to a mesh cut and continue traversal till we have visited all the nodes as shown in Fig 2. If we want a finer mesh cut, we can set 𝑇 =1. This 𝑇 will result in a mesh cut with all the triangle primitives.” Also, page 3 col. 1, 2.5 Building Fused BVH with Many LOD Meshes, “We added single 32-bit data for each node in the Base LOD BVH to store this information. More specifically, our implementation stores up to 6 levels for an instance. We allocated 3, 5, and 24 bits to store level, terminal flag (1 bit per level), and root node index of the subtree from a mesh cut.”
the traversal hardware logic to continue traversing the ray through either the first child node or the second child node based on a result of the comparison (See abstract, and col. 2, FUSED BVH FOR LOD MESHES – the last line of the same page and col. 2) but doesn’t explicitly disclose a graphics processor comprising:
between an LoD node bitmask associated with the multi-LoD node and a per-ray bitmask associated with the ray
Kulkarni a graphics processor comprising (See page 3 col. 2, 3 CONCLUSIONS AND FUTUREWORK, “Also, we would like to investigate the efficient GPU implementation for fused BVH. The fused BVH is definitely appealing for the GPU where reduction in the memory overhead is a big win.” Page 2-4 upper left corner the icon says AMD GPUOpen.);
[…]between an LoD node bitmask associated with the multi-LoD node and a per-ray bitmask associated with the ray (See page 1 col. 2, 2.1 Finding a Mesh Cut, “We start by finding subtrees forming a cut in LOD 1 BVH at decent depth. For this purpose, we introduce a threshold 𝑇 as a number of child nodes. We start traversing LOD 1 BVH until we reach a node with the number of child nodes less than or equal to 𝑇 . We add such a node to a mesh cut and continue traversal till we have visited all the nodes as shown in Fig 2. If we want a finer mesh cut, we can set 𝑇 =1. This 𝑇 will result in a mesh cut with all the triangle primitives.” The examiner notes that the evaluation equal/less than to T is interpreted as a bitmask. That is, T is interpreted to be a bitmask. Also, page 3 col. 1, 2.5 Building Fused BVH with Many LOD Meshes, “We added single 32-bit data for each node in the Base LOD BVH to store this information. More specifically, our implementation stores up to 6 levels for an instance. We allocated 3, 5, and 24 bits to store level, terminal flag (1 bit per level), and root node index of the subtree from a mesh cut.” The bits are considered to be bitmasks as well.).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Kulkarni in view of Kulkarni as using a GPU is ideal due to the large scale parallel nature of ray tracing which requires billions of independent, repetitive intersection tests that GPUs are designed to handle efficiently. Furthermore a GPU provides thousands of cores to handle these rays simultaneously, whereas a CPU is limited in core number. Furthermore it would have been obvious to implement bitmasks for a comparison between and an LoD node as bitmaps as bitmasks are known techniques which can be used to improve similar device/methods ready for improvement to yield predicable results.
Regarding claim 2, Kulkarni teaches the graphics processor of claim 1 further (See page 3 col. 2, 3 CONCLUSIONS AND FUTUREWORK, “Also, we would like to investigate the efficient GPU implementation for fused BVH. The fused BVH is definitely appealing for the GPU where reduction in the memory overhead is a big win.” Page 2-4 upper left corner the icon says AMD GPUOpen.) comprising:
comparison logic to perform the comparison between the LoD node bitmask and the per-ray bitmask, wherein the comparison comprises at least one of: a greater than or equal to comparison, a less than or equal to comparison, a greater than comparison, a less than comparison, and an equal to comparison (See page 1 col. 2, 2.1 Finding a Mesh Cut, “We start by finding subtrees forming a cut in LOD 1 BVH at decent depth. For this purpose, we introduce a threshold 𝑇 as a number of child nodes. We start traversing LOD 1 BVH until we reach a node with the number of child nodes less than or equal to 𝑇 . We add such a node to a mesh cut and continue traversal till we have visited all the nodes as shown in Fig 2. If we want a finer mesh cut, we can set 𝑇 =1. This 𝑇 will result in a mesh cut with all the triangle primitives.” The examiner notes that the evaluation equal/less than to T is interpreted as a bitmask. That is, T is interpreted to be a bitmask. Also, page 3 col. 1, 2.5 Building Fused BVH with Many LOD Meshes, “We added single 32-bit data for each node in the Base LOD BVH to store this information. More specifically, our implementation stores up to 6 levels for an instance. We allocated 3, 5, and 24 bits to store level, terminal flag (1 bit per level), and root node index of the subtree from a mesh cut.” The bits are considered to be bitmasks as well. See MPEP 2173.05(h)).
Regarding claim 7, Kulkarni The graphics processor of claim 1 wherein the LoD node bitmask and the per-ray bitmask comprise values having a size of 8-bits, 16-bits, or 32- bits (See page 3 col. 1 2.5 Building Fused BVH with Many LOD Meshes “We added single 32-bit data for each node in the Base LOD BVH to store this information. More specifically, our implementation stores up to 6 levels for an instance. We allocated 3, 5, and 24 bits to store level, terminal flag (1 bit per level), and root node index of the subtree from a mesh cut.”.)
Claim 9 recites similar limitations to that of claim 1 and thus is rejected under similar rationale as detailed above.
Claim 10 recites similar limitations to that of claim 2 and thus is rejected under similar rationale as detailed above.
Claim 15 recites similar limitations to that of claim 7 and thus is rejected under similar rationale as detailed above.
Claim 17 recites similar limitations to that of claim 1 and thus is rejected under similar rationale as detailed above, but doesn’t explicitly disclose:
A machine-readable medium having program code stored thereon which, when executed by a machine, cause the machine to perform the operations of:
Kulkarni teaches a machine-readable medium (see abstract cache, a memory) having program (See abstract, the method are steps/program. Page 3 col. 1, 2.2 Fusing Mesh Cut in the Base LOD BVH, the method is describe steps, which are a program) stored thereon which (see abstract, cache which is a memory for storing a program/instructions), when executed by a machine, cause the machine to perform the operations of (See page 2, 2.2 Fusing Mesh Cut in the Base LOD BVH col. 2 first 3 lines, “The last thing we need to do is refit the AABBs in the Base LOD BVH. The AABBs computed for the Base LOD BVH do not always enclose the subtree fused.” Computing carried out by a processor.):
Claim 18 recites similar limitations to that of claim 2 and thus is rejected under similar rationale as detailed above.
Claim 23 recites similar limitations to that of claim 7 and thus is rejected under similar rationale as detailed above.
Conclusion
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/ROBERT J CRADDOCK/Primary Examiner, Art Unit 2618