DETAILED ACTION
This Office Action is in response to the Applicant Election filed on 04/08/2026.
Currently, claims 1-20 are pending in the application. Currently, claims 5 and 10 are withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I (Figs. 2F & 3H) in the reply filed on 04/08/2026 is acknowledged. Claims 5 and 10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-selected invention, there being no allowable generic or linking claim. Claims 1-4, 6-9, and 11-20 are examined in this Office action.
Claim Objections
Claims 2 and 7 are objected to because of the following informality:
In claims 2 and 7, “lower backbone portion distinct” should read “lower backbone portion”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by CHEN et al. (US Pub. No. 2023/0141523).
Regarding independent claim 1, Chen teaches an integrated circuit structure (Fig. 6B), comprising:
a backbone (Fig. 6B, 140Nd + 120d + 118CNd, ¶ [0126]) comprising a lower backbone portion (Fig. 6B, 120d + 118CNd, ¶ [0126]) distinct from an upper backbone portion (Fig. 6B,140Nd, ¶ [0126]);
a first vertical stack of nanowires (Fig. 6B, 108′-1, ¶ [0127] teaches channel structures. ¶ [0162] teaches that Chen’s channel structures can be nanowires) in lateral contact with a first side of the backbone (Fig. 6B, 108′-1 is in contact with a right side of 118CNd and 120d); and
a second vertical stack of nanowires (Fig. 6B, 108′-2, ¶ [0127] teaches channel structures. ¶ [0162] teaches that Chen’s channel structures can be nanowires) in lateral contact with a second side of the backbone (Fig. 6B, 108′-1 is in contact with a left side of 118CNd and 120d), the second side opposite the first side.
Regarding claim 2, Chen teaches the integrated circuit structure of claim 1, and Chen teaches that a seam (Fig. 6B, seam vertically in-between the bottom surface of 140Nd and the top surfaces of 120 and 118CNd, also see Figs. 2G-2H, ¶ [0056]) is vertically between the lower backbone portion (Fig. 6B, 120d + 118CNd, ¶ [0126]) and the upper backbone portion (Fig. 6B,140Nd, ¶ [0126]).
Regarding claim 3, Chen teaches the integrated circuit structure of claim 1, and Chen teaches that the lower backbone portion (Fig. 6B, 120d + 118CNd, ¶ [0126]) comprises silicon and oxygen (¶¶ [0043]-[0044] teaches that 120 and 118, corresponding to 120d and 118CNd in Fig. 6B, can include silicon and oxygen), and the upper backbone portion (Fig. 6B,140Nd, ¶ [0126]) comprises a metal and oxygen (¶ [0057] teaches that 140, corresponding to 140Nd in Fig. 6B, can include a metal and oxygen).
Regarding claim 4, Chen teaches the integrated circuit structure of claim 1, and Chen teaches that the first (Fig. 6B, 108′-1, ¶ [0127] teaches channel structures. ¶ [0162] teaches that Chen’s channel structures can be nanowires) and second vertical stacks of nanowires (Fig. 6B, 108′-2, ¶ [0127] teaches channel structures. ¶ [0162] teaches that Chen’s channel structures can be nanowires) are in lateral contact with the lower backbone portion (Fig. 6B, 120d + 118CNd, ¶ [0126]) but not with the upper backbone portion (Fig. 6B,140Nd, ¶ [0126]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-9 are rejected under 35 U.S.C. 103 as being obvious over CHEN et al. (US Pub. No. 2023/0141523) in view of LIN et al. (US Pub. No. 2024/0120338).
Regarding independent claim 6, Chen teaches an integrated circuit structure (Fig. 2O), comprising:
a first vertical stack of nanowires (Fig. 2O, 108 in contact with right side of 118, ¶ [0084] teaches semiconductor material layers 108 corresponding to Chen’s channel structures. ¶ [0162] teaches that Chen’s channel structures can be nanowires) in a first sub-fin structure (Fig. 2O, 104b below 108 in contact with right side of 118, ¶ [0036]);
a second vertical stack of nanowires (Fig. 2O, 108 in contact with left side of 118, ¶ [0084] teaches semiconductor material layers 108 corresponding to Chen’s channel structures. ¶ [0162] teaches that Chen’s channel structures can be nanowires) in a second sub-fin structure (Fig. 2O, 104b below 108 in contact with left side of 118, ¶ [0036]); and
a backbone (Fig. 2O, 140 + 120 + 118, ¶ [0056]), the backbone comprising a lower backbone portion (Fig. 2O, 120 + 118, ¶ [0056]) distinct from an upper backbone portion (Fig. 2O, 140, ¶ [0056]), wherein the first vertical stack of nanowires is in lateral contact with a first side of the backbone (Fig. 2O, layers 108 in contact with right side of 118), and the second vertical stack of nanowires (Fig. 2O, layers 108 in contact with left side of 118) is in lateral contact with a second side of the backbone, the second side opposite the first side.
However, Chen does not explicitly teach
an NMOS device including a first vertical stack of nanowires above a P-well in a first sub-fin structure;
a PMOS device including a second vertical stack of nanowires above an N-well in a second sub-fin structure; and
a backbone laterally between the NMOS device and the PMOS device.
However, Chen ¶ [0032] does teach that their semiconductor structure can include NFET, PFET, and CMOS transistors. It would be obvious to one of ordinary skill in the art that a CMOS transistor includes a PMOS transistor and an NMOS transistor (as evidence see ¶ [0015] of Lin).
Therefore, it would be obvious that Chen’s CMOS transistor would include an NMOS device that includes stacked semiconductor layers over an p-type region on one side of Chen’s backbone and a PMOS that includes stacked semiconductor layers over an n-type region on an opposite side of Chen’s backbone in a similar manner to Lin’s CMOS device (see Lin Fig. 12B, 50N + 50P + 56B, ¶¶ [0015] & [0020]).
Regarding claim 7, Chen in view of Lin teaches the integrated circuit structure of claim 6, and Chen teaches that a seam (Fig. 2O, seam vertically in-between the bottom surface of 140 and the top surfaces of 120 and 118, also see Figs. 2G-2H, ¶ [0056]) is vertically between the lower backbone portion (Fig. 2O, 120 + 118, ¶ [0056]) and the upper backbone portion (Fig. 2O, 140, ¶ [0056]).
Regarding claim 8, Chen in view of Lin teaches the integrated circuit structure of claim 6, and Chen teaches that the lower backbone portion (Fig. 2O, 120 + 118, ¶ [0056]) comprises silicon and oxygen (¶¶ [0043]-[0044] teaches that 120 and 118 can include silicon and oxygen), and the upper backbone portion (Fig. 2O, 140, ¶ [0056]) comprises a metal and oxygen (¶ [0057] teaches that 140 can include a metal and oxygen).
Regarding claim 9, Chen in view of Lin teaches the integrated circuit structure of claim 6, and Chen teaches that the first (Fig. 2O, 108 in contact with right side of 118, ¶ [0084] teaches semiconductor material layers 108 corresponding to Chen’s channel structures. ¶ [0162] teaches that Chen’s channel structures can be nanowires) and second vertical stacks (Fig. 2O, 108 in contact with left side of 118, ¶ [0084] teaches semiconductor material layers 108 corresponding to Chen’s channel structures. ¶ [0162] teaches that Chen’s channel structures can be nanowires) of nanowires are in lateral contact with the lower backbone portion (Fig. 2O, 120 + 118, ¶ [0056]) but not with the upper backbone portion (Fig. 2O, 140, ¶ [0056]).
Claims 11-15 are rejected under 35 U.S.C. 103 as being obvious over CHEN et al. (US Pub. No. 2023/0141523) in view of LILAK et al. (US Pub. No. 2021/0296315).
Regarding independent claim 11, Chen teaches an integrated circuit structure (Fig. 6B), comprising:
a backbone (Fig. 6B, 140Nd + 120d + 118CNd, ¶ [0126]) comprising a lower backbone portion (Fig. 6B, 120d + 118CNd, ¶ [0126]) distinct from an upper backbone portion (Fig. 6B,140Nd, ¶ [0126]);
a first vertical stack of nanowires (Fig. 6B, 108′-1, ¶ [0127] teaches channel structures. ¶ [0162] teaches that Chen’s channel structures can be nanowires) in lateral contact with a first side of the backbone (Fig. 6B, 108′-1 is in contact with a right side of 118CNd and 120d); and
a second vertical stack of nanowires (Fig. 6B, 108′-2, ¶ [0127] teaches channel structures. ¶ [0162] teaches that Chen’s channel structures can be nanowires) in lateral contact with a second side of the backbone (Fig. 6B, 108′-1 is in contact with a left side of 118CNd and 120d), the second side opposite the first side.
However, Chen does not explicitly teach a computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure (the Examiner notes that Chen ¶ [0032] does teach that their structure can be included in a processor).
However, Lilak is a pertinent art that teaches that a computing device (Fig. 21, 2100, ¶ [0144]), comprising:
a board (Fig. 21, 2102, ¶ [0144]); and
a component (Fig. 21, 2104, ¶ [0147]) coupled to the board, the component including an integrated circuit structure (¶ [0147] teaches that processor 2104 can include forksheet transistors).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Chen’s structure in Lilak’s processor coupled to a computing device because a processor is an obvious application of Chen’s semiconductor device (see Chen ¶ [0032]).
Regarding claim 12, Chen in view of Lilak teaches the computing device of claim 11, and Lilak teaches a memory (Fig. 21, DRAM, ¶ [0145]) coupled to the board (Fig. 21, 2102, ¶ [0144]).
Regarding claim 13, Chen in view of Lilak teaches the computing device of claim 11, and Lilak teaches a communication chip (Fig. 21, 2106, ¶ [0146]) coupled to the board (Fig. 21, 2102, ¶ [0144]).
Regarding claim 14, Chen in view of Lilak teaches the computing device of claim 11, and Lilak teaches a camera (¶ [0145] teaches that a camera can be coupled to the board) coupled to the board (Fig. 21, 2102, ¶ [0144]).
Regarding claim 15, Chen in view of Lilak teaches the computing device of claim 11, and Lilak teaches that the component is a packaged integrated circuit die (Fig. 21, 2104, teaches that their processor includes an packaged integrated circuit die).
Claims 16-20 are rejected under 35 U.S.C. 103 as being obvious over CHEN et al. (US Pub. No. 2023/0141523) in view of LIN et al. (US Pub. No. 2024/0120338) and further in view of LILAK et al. (US Pub. No. 2021/0296315).
Regarding independent claim 16, Chen teaches Chen teaches an integrated circuit structure (Fig. 2O), comprising:
a first vertical stack of nanowires (Fig. 2O, 108 in contact with right side of 118, ¶ [0084] teaches semiconductor material layers 108 corresponding to Chen’s channel structures. ¶ [0162] teaches that Chen’s channel structures can be nanowires) in a first sub-fin structure (Fig. 2O, 104b below 108 in contact with right side of 118, ¶ [0036]);
a second vertical stack of nanowires (Fig. 2O, 108 in contact with left side of 118, ¶ [0084] teaches semiconductor material layers 108 corresponding to Chen’s channel structures. ¶ [0162] teaches that Chen’s channel structures can be nanowires) in a second sub-fin structure (Fig. 2O, 104b below 108 in contact with left side of 118, ¶ [0036]); and
a backbone (Fig. 2O, 140 + 120 + 118, ¶ [0056]), the backbone comprising a lower backbone portion (Fig. 2O, 120 + 118, ¶ [0056]) distinct from an upper backbone portion (Fig. 2O, 140, ¶ [0056]), wherein the first vertical stack of nanowires is in lateral contact with a first side of the backbone (Fig. 2O, layers 108 in contact with right side of 118), and the second vertical stack of nanowires (Fig. 2O, layers 108 in contact with left side of 118) is in lateral contact with a second side of the backbone, the second side opposite the first side.
However, Chen does not explicitly teach
an NMOS device including a first vertical stack of nanowires above a P-well in a first sub-fin structure;
a PMOS device including a second vertical stack of nanowires above an N-well in a second sub-fin structure; and
a backbone laterally between the NMOS device and the PMOS device.
However, Chen ¶ [0032] does teach that their semiconductor structure can include NFET, PFET, and CMOS transistors. It would be obvious to one of ordinary skill in the art that a CMOS transistor includes a PMOS transistor and an NMOS transistor (see ¶ [0015] of Lin).
Therefore, it would be obvious that Chen’s CMOS transistor would include an NMOS device that includes stacked semiconductor layers over an p-type region on one side of Chen’s backbone and a PMOS that includes stacked semiconductor layers over an n-type region on an opposite side of Chen’s backbone in a similar manner to Lin’s CMOS device (see Lin Fig. 12B, 50N + 50P + 56B, ¶¶ [0015] & [0020]).
However, Chen in view of Lin does not explicitly teach a computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure (the Examiner notes that Chen ¶ [0032] does teach that their structure can be included in a processor).
However, Lilak is a pertinent art that teaches that a computing device (Fig. 21, 2100, ¶ [0144]), comprising:
a board (Fig. 21, 2102, ¶ [0144]); and
a component (Fig. 21, 2104, ¶ [0147]) coupled to the board, the component including an integrated circuit structure (¶ [0147] teaches that processor 2104 can include forksheet transistors).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Chen in view of Lin’s structure in Lilak’s processor coupled to a computing device because a processor is an obvious application of Chen’s semiconductor device (see Chen ¶ [0032]).
Regarding claim 17, Chen in view of Lin in view of Lilak teaches the computing device of claim 16, and Lilak teaches a memory (Fig. 21, DRAM, ¶ [0145]) coupled to the board (Fig. 21, 2102, ¶ [0144]).
Regarding claim 18, Chen in view of Lin in view of Lilak teaches the computing device of claim 16, and Lilak teaches a communication chip (Fig. 21, 2106, ¶ [0146]) coupled to the board (Fig. 21, 2102, ¶ [0144]).
Regarding claim 19, Chen in view of Lin in view of Lilak teaches the computing device of claim 16, and Lilak teaches a camera (¶ [0145] teaches that a camera can be coupled to the board) coupled to the board (Fig. 21, 2102, ¶ [0144]).
Regarding claim 20, Chen in view of Lin in view of Lilak teaches the computing device of claim 16, and Lilak teaches that the component is a packaged integrated circuit die (Fig. 21, 2104, teaches that their processor includes an packaged integrated circuit die).
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub No. 2023/0223442 by Chiang et al discloses a semiconductor device.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub No. 2024/0145595 by Fulford et al discloses a semiconductor device.
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/R.P.S./
Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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