DETAILED ACTION
Claims 6-8, 10, 21-28 are presented for examination.
The present application is being examined under the AIA (America Invents Act) First Inventor to File.
This Office Action is Non-Final.
Claims 6, 21 and 25 are independent claims. Claims 7-8, 10, 22-24, and 26-28 are dependent claims. Claims 1-5, 9 and 11-20 have been canceled.
This action is responsive to the following communication: the response filed on February 18, 2025.
Claim Rejections - 35 USC § 101
Claim rejections under 35 U.S.C. 101 have been withdrawn, in light of the amendment/remarks set forth on February 18, 2025 by Applicant(s).
Continuation Application
This application discloses and claims only subject matter disclosed in prior Application No. 16/457,184 and names an inventor or inventors named in the prior application. Accordingly, this application constitutes a continuation claiming benefit of the filing date of June 28, 2019 which is acknowledged.
However, Applicant has not complied with one or more conditions for receiving the benefit of an earlier filing date under 35 U.S.C. 119(e) and/or 120 as follows:
The later-filed application must be an application for a patent for an invention which is also disclosed in the prior application which benefit is sought. The disclosure of the invention in the parent application and in the later-filed application must be sufficient to comply with the requirements of 35 U.S.C. 112(a) or the first paragraph of pre-AIA 35 U.S.C. 112, except for the best mode requirement. See Transco Products, Inc. v. Performance Contracting, Inc., 38 F.3d 551,32 USPQ2d 1077 (Fed. Cir. 1994)
The disclosure of the prior-filed application Number 16/457,184 fails to provide adequate support or enablement in the manner provided by 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph for one or more claims of this instant application.
In particular, the priority application cited above does not disclose the expression directed to a processing circuitry/method/computer-readable medium that is responsible for “interface[ing] between the first instruction set and second instruction set” as currently recited by claim 6. Indeed, a key word search of for the above expressions fails to provide any results. Similarly, for the same reason provided above, the expressions directed to “associating a load interface with the IP block for facilitating interfacing between a first instruction set and a second instruction set associated with the IP block”, “a common interface operating with the push model and the pull model” and “providing common directives for interfacing between two or more of the first instruction set, the second instruction set or a third instruction set” as currently recited by claims 21, 25, 7, 22 and 26 also fail to provide adequate support or enablement.
Therefore, claims 6, 21, 25, 7, 22 and 26 of the instant application are not entitled to the benefit of the filing date of the priority application cited above, which means claims 6, 21, 25, 7, 22 and 26 are only entitled to the benefit of the filing date of December 26, 2022.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-8, 10 and 21-28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In particular, claims 6-8, 10 and 21-28 recite specific features, for example, “processing circuitry” that is configured to “interface[ing] between the first instruction set and second instruction set”, “associating a load interface with the IP block for facilitating interfacing between a first instruction set and a second instruction set associated with the IP block”, “common interface” and “common directives”. However, the Office submits these expressions are not referenced in the detailed description of the specification nor such features are illustrated by the figures for which the system on a chip claimed is directed.
Thereby, for a person having ordinary skill in the art, it would be unclear in determining the metes and bounds of the invention.
Indeed, courts have found that claims must "conform to the invention as set forth in the remainder of the specification and the terms and phrases used in the claims must find clear support or antecedent basis in the description so that the meaning of the terms in the claims may be ascertainable by reference to the description." 37 CFR 1.75(d)(1).
Notwithstanding, even when a claim may be clear on its face, may also be indefinite when a conflict or inconsistency between the claimed subject matter and the specification disclosure renders the scope of the claim uncertain as inconsistency with the specification disclosure or prior art teachings may make an otherwise definite claim take on an unreasonable degree of uncertainty. In re Moore, 439 F.2d 1232, 1235-36, 169 USPQ 236, 239 (CCPA 1971); In re Cohn, 438 F.2d 989, 169 USPQ 95 (CCPA 1971); In re Hammack
Therefore, “Applicant will be required to make appropriate amendment to the description to provide clear support or antecedent basis for the claim terms provided no new matter is introduced, or amend the claim.” In other words, in describing these features, claims must use a nomenclature that is consisting with the rest of the specification and drawings.
As per dependent claims, these claims do not cure the deficiencies presented above and are rejected for being dependent upon a rejected claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-8, 10, 21-28 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2016/0179161 (hereinafter, “Adler”) in view of U.S. Publication No. 2019/0278586 (hereinafter “Olarig”) and further view of U.S. Publication No. 2019/0243631 (hereinafter, “Sharma”).
As per claims 21, 25 Adler discloses a method comprising:
providing, by a computing device, for loading intellectual property (IP) blocks; and (¶ [0049] describes a “ SoC including multiple IP blocks” that can be initialized with BIOS based on configuration information stored in Base Address Registers (BARs). For example, IP blocks illustrated by Fig’s 1, 7 )
loading a firmware into an IP block (¶ [0049] describes an “ SoC including multiple IP blocks” that can be initialized with BIOS based on configuration information stored in Base Address Registers (BARs) ) and associating a load interface with the IP block for facilitating interfacing (address mapping ¶s [0050]-[0051] ) between a first instruction set and a second instruction set associated with the IP block (¶ [0052] states a “system fabric architecture can be defined for use in interconnecting blocks in an SoC. The fabric can provide a standardized interface to enable IP blocks to be shared across CPU, platform controller hub (PCH), and SoC products” . In other words, Adler discloses a shared standardized interface using addressing mapping for distinct hardware architectures. (Fig’s 1, 5-7) It would be apparent to POSITA that different hardware architectures process functions having different instruction sets. Indeed, ¶ [0062] states that “An IP block can also include one or more distinct devices, each device configured to support one or more respective functions”. Also ¶ [0094] which teaches multiple instruction set architecture hardware that have a “heterogeneous core environment” ¶ [0079]) wherein the IP block comprises a firmware load interface (Fig. 1 illustrates switch/bridge 120/controller hub for interfacing between devices 105,125, 110 and 130.Also, Fig 7 illustrates fabric devices for interfacing between IP blocks ) or a firmware dashboard including a system -facing interface.
Adler does not distinctly disclose where the expression directed to providing, by a computing device, for loading intellectual property (IP) blocks” is narrowly interpreted as loading the IP blocks with firmware updates.
However, Olarig discloses that. In particular, Olarig discloses the following:
providing, by a computing device, a model for loading intellectual property (IP) blocks; and (¶ [0020] states “writing the contents of the processor firmware buffer when an updated processor firmware image is present”. )
loading a firmware into an IP block (¶ [0020] states “writing the contents of the processor firmware buffer when an updated processor firmware image is present”. ) and associating a load interface with the IP block for facilitating interfacing between a first instruction set and a second instruction set associated with the IP block. (¶ [0024] states “flashing, by the firmware upgrade module, a processor firmware storage with the processor firmware image; and flashing, by the firmware upgrade module, a programmable logic of the FPGA with the RTL firmware image”. The Office submits for sake of clarification that the various hardware components are configured to operate for distinct functions, thus it follows that the instruction sets executed are distinct. For example, “For example, the RTL firmware may dictate the operation of the SSD controller. In various embodiments, the FPGA processor firmware may be configured to control the operation of the FPGAs multicore processor”. ¶ [0047]) wherein the IP block comprises a firmware load interface (Fig’s 1-2 illustrates various interfaces for loading firmware ) or a firmware dashboard including a system-facing interface.
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Adler and Olarig because both references are in the same field of endeavor. Olarig’s teaching of loading firmware updates would enhance Adler's system by allowing computer systems to expedite feature upgrades.
Adler as modified does not distinctly discloses a push model or pull model for loading firmware.
However, Sharma discloses a push model or pull model for loading firmware. (¶ [0013] )
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Adler as modified and Sharma because all references are in the same field of endeavor. Sharma’s teaching of pushing firmware updates would enhance Adler's as modified system by automatically expediting feature upgrades.
As per claim 6, Adler as modified discloses a system on a chip (SoC) comprising:
processing circuitry having a first instruction set; and (Adler: at least Fig. 1 illustrates processor 105 for executing processor instructions. Alternatively, any of the IPs for executing specific functions; Fig. 7 )
a first intellectual property (IP) block coupled to the processing circuitry, ( controller hub 115 interface illustrated by Fig 1 or Fabric device interface; Fig 7) ) the IP block comprising a first microcontroller (Adlerer; Fig 9, ¶ [0101]) having a second instruction set different from the first instruction set, (Adler: ¶ [0052] states a “system fabric architecture can be defined for use in interconnecting blocks in an SoC. The fabric can provide a standardized interface to enable IP blocks to be shared across CPU, platform controller hub (PCH), and SoC products” . In other words, Adler discloses a shared standardized interface using addressing mapping for distinct hardware architectures. (Fig’s 1, 5-7) It would be apparent to POSITA that different hardware architectures process functions having different instruction sets. Indeed, ¶ [0062] states that “An IP block can also include one or more distinct devices, each device configured to support one or more respective functions”. Also ¶ [0094] which teaches multiple instruction set architecture hardware.) wherein the IP block, as facilitated by the processor circuit, provides a push model or a pull model (Sharma; see rejection from other independent claims) to loads and load IP block firmware, ) wherein the IP block comprises a firmware load interface (Fig. 1 illustratesswitch/bridge 120/controller hub for interfacing between devices 105,125, 110 and 130.Also, Fig 7 illustrates fabric devices for interfacing between IP blocks ) or a firmware dashboard including a system -facing interface.
wherein the processing circuitry to load a firmware into the IP block and interface between the first instruction set and the second instruction set; wherein the processing circuitry is further to provide a load interface to the IP block (see rejection from other independent claims)
As per claims 22, 7, 26, Adler as modified discloses a method further comprising providing a common interface (Adler: Fig 1 controller hub or Fabric device illustrated by Fig 7 ) operating with the push model and the pull model (Sharma; ¶ [013] ) and further providing common directives or interfacing between two or more of the first instruction set, the second instruction set, or a third instruction set. (Adler: RTL files for determining configuration of elements, for example, “physical link paths”; ¶ [0099] Alternatively, information library 61 for address mapping; Fig 6) & ( (¶ [0024] states “flashing, by the firmware upgrade module, a processor firmware storage with the processor firmware image; and flashing, by the firmware upgrade module, a programmable logic of the FPGA with the RTL firmware image”. )
As per claims 23, 8, 27 Adler as modified discloses a method wherein the first IP block comprises one or more of an internal read-only memory (ROM), an internal random access memory (RAM), an internal static random access memory (SRAM), or an internal cryptography to verify the firmware. (Adler: Fig 1, ¶ [0088], [0024], [0095]) & (Olarig: ¶[0062])
As per claims 24, 10, 28, Adler as modified discloses a method wherein the computing device comprises processing circuitry coupled to a memory, the processing circuitry comprising one or more of application processing circuitry or a graphics processing circuitry. (Adler: Fig 1, ¶ [0088], [0024], [0095]) & (Olarig: ¶[0062])
Remarks
Applicant's arguments filed on February 18, 2026 have been fully considered but they are not persuasive to the extent that is applicable to the claims.
I. Continuation Application
During the previous Office Action, the Office noted that claims 6, 7, 21, 22,25 and 26, and 21 of the Continuation Application contains subject matter that is not supported by the Parent Application, thus the above claims are not fully entitled the benefit of and priority of the Parent Application. In that regard, the Office submitted specific reasons and rationales how the continuation application fails do so.
On the other hand, Applicant simply concludes that the Continuation Application is fully entitled to the benefit of priority of the Parent Application without providing any factual evidence on how the specific expressions recited by the Continuation Application are found in the Parent Application.
For at least this reason, the Office submits that the Continuation Application is not fully entitled to the benefit of priority of the Parent Application.
II. Rejections under 35 U.S.C. §112
Claims 6-8, 10 and 21-28 were rejected under 35 U.S.C. §112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventors regard as the invention.
In particular, the Office stated claims 6-8, 10 and 21-28 recite specific features, for example, “processing circuitry” that is configured to “interface[ing] between the first instruction set and second instruction set”, “associating a load interface with the IP block for facilitating interfacing between a first instruction set and a second instruction set associated with the IP block”, “common interface” and “common directives” that are not referenced in the detailed description of the specification nor such features are illustrated by the figures for which the system on a chip claimed is directed. Therefore, under 37 CFR 1.75(d)(1), the above claims do not "conform to the invention as set forth in the remainder of the specification and the terms and phrases used in the claims must find clear support or antecedent basis in the description so that the meaning of the terms in the claims may be ascertainable by reference to the description".
Applicant asserts that the specification does describe the “push/pull mode flows in terms of writing/reading the loader/verifier registers”, concluding that the specification clearly provides antecedent basis.
The Office submits that while the specification may provide antecedent basis for push/pull mode flows in terms of writing/reading the loader/verifier registers, Applicant remarks fail to show where and how does the specification support the specific features raised by the Office Action as required under 35 U.S.C. §112.
For at least this reason, the Office submits that the claims 6-8, 10 and 21-28 do not comply under 35 U.S.C. §112.
III. Rejections under 35 U.S.C. §103
Applicant's arguments under U.S.C. §103 are directed to the newly added subject matter. For that reason, the new ground(s) of rejection are described above.
Conclusion
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AUREL PRIFTI whose telephone number is (571)270-1743. The examiner can normally be reached on M-F 8 a.m.- 6 p.m..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kim Ngoc Huynh can be reached on 571-272-4147. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AUREL PRIFTI/Primary Examiner, Art Unit 2175
Aurel Prifti
Primary Examiner
Art Unit 2175
Tel. (571) 270-1743
Fax (571) 270-2743
aurel.prifti@uspto.gov