DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6-7, 9-10, 15-16 and 18-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sekiguchi (US 2017/0019113).
With respect to claim 1,
Figure 2 of Sekiguchi discloses a system comprising:
an adaptive clock gate enable circuit (10) to generate a clock gate enable signal (FCNT);
a clock gate control logic circuit (FS) to generate an adaptive clock enable signal (ENC) based at least in part on the clock gate enable signal (FCNT); and
an enable logic gate (GB) to generate a gated clock signal (GCLK) based at least in part on the adaptive clock enable signal (ENC) and a clock signal (DCLK), the gated clock signal to be received by an intellectual property (IP) circuit to selectively disable one or more IP circuit flip-flops (see Figure 3 and Paragraph 54).
With respect to claim 6,
Sekiguchi further teaches wherein the enable logic gate includes an AND logic gate (see Figures 2 and 3) to:
receive the adaptive clock enable signal (ENC) and the clock signal (DCLK); and
generate the gated clock signal (GCLK), the gated clock signal including a gated clock logical ON value when both the adaptive clock enable signal and the clock signal include a gated clock logical high signal level (Paragraph 59).
With respect to claim 7,
Sekiguchi further teaches a clock frequency control unit circuit (20), the adaptive clock gate enable circuit (10) coupled to the clock frequency control unit circuit (see Figure 2);
wherein the adaptive clock gate enable circuit (10) is to generate the clock gate enable signal based at least in part on an IP variable clock frequency value (Paragraph 49).
With respect to claim 9,
Sekiguchi further teaches a clock gate synchronizer (ENGEN) coupled to the clock gate control logic circuit (FS), the clock gate synchronizer to synchronize the clock gate enable signal with the clock signal (Paragraph 57).
With respect to claim 10,
Figure 2 of Sekiguchi discloses a method comprising:
generating a clock gate enable signal (FCNT) at an adaptive clock gate enable circuit (10);
generating an adaptive clock enable signal (ENC) at clock gate control logic circuit (FS) based at least in part on the clock gate enable signal (FCNT); and
generating a gated clock signal (GCLK) at an enable logic gate (GB) based at least in part on the adaptive clock enable signal (ENC) and a clock signal (DCLK), the gated clock signal to be received by an intellectual property (IP) circuit to selectively disable one or more IP circuit flip-flops (see Figure 3 and Paragraph 54).
With respect to claim 15,
Sekiguchi further teaches wherein the enable logic gate includes an AND logic gate (see Figures 2 and 3) to:
receive the adaptive clock enable signal (ENC) and the clock signal (DCLK); and
generate the gated clock signal (GCLK), the gated clock signal including a gated clock logical ON value when both the adaptive clock enable signal and the clock signal include a gated clock logical high signal level (Paragraph 59).
With respect to claim 16,
Sekiguchi further teaches wherein: the adaptive clock gate enable circuit (10) is coupled to a clock frequency control unit circuit (20); and
the adaptive clock gate enable circuit (10) is to generate the clock gate enable signal based at least in part on an IP variable clock frequency value (Paragraph 49).
With respect to claim 18,
Sekiguchi further teaches further including synchronizing, at a clock gate synchronizer (ENGEN) coupled to the clock gate control logic circuit (FS), the clock gate enable signal with the clock signal (Paragraph 57).
With respect to claim 19,
Figure 2 of Sekiguchi discloses a system comprising:
a clock frequency control unit circuit (10) to generate a clock gate enable signal (FCNT) based at least in part on an IP variable clock frequency value;
a clock gate control logic circuit (FS) coupled to the clock frequency control unit circuit (10), the clock gate control logic circuit to generate an adaptive clock enable signal (ENC) based at least in part on the clock gate enable signal (FCNT); and
an enable logic gate (GB) coupled to the clock gate control logic circuit (FS), the enable logic gate to generate a gated clock signal (GCLK) based at least in part on the adaptive clock enable signal (ENC), the gated clock signal (GCLK) to be received by an intellectual property (IP) circuit to selectively disable one or more IP circuit flip- flops (see Figure 3 and Paragraph 54).
Allowable Subject Matter
Claims 2-5, 8, 11-14, 17 and 20-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jany Richardson whose telephone number is (571)270-5074. The examiner can normally be reached Monday - Friday, 7:00am to 3:00pm.
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/JANY RICHARDSON/ Primary Examiner, Art Unit 2844