DETAILED ACTION
This office action is in response to the amendment filed on 05/07/2026. Claims 1-25 are pending, of which claims 1, 6, 12, 18 are amended by the current amendment.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, 11-17 are rejected under 35 U.S.C. 102(a)(1) and/or (a)(2) as being anticipated by Tang et al. (US Patent or PG Pub. No. 20090224731, hereinafter ‘731).
Claim 1, ‘731 teaches an apparatus (e.g., when phase number being 2, see Fig. 1-15) comprising:
a voltage regulator circuit (e.g., the first phase power regulator comprising 40, 60, 50) to generate a regulated voltage output at a voltage output node (e.g., the voltage regulator output voltage applied to 80, see [0060], Fig. 1), the regulated voltage output associated with a regulated current level (e.g., see Fig. 12-13); and a supplemental current source circuit (e.g., the circuit comprising 42, 62) to generate a supplemental current (e.g., the corresponding current passing 42 and 62) at the voltage output node when the regulated current level has exceeded a current level threshold (e.g., the respective threshold, see Fig. 2-5, , Fig. 8, 14A, 14B, 15), the supplemental current source circuit including a current path from an input voltage node to the voltage output node (e.g., the corresponding current passing 42 and 62 from Vin to load 80, see Fig. 1), the current path bypassing the voltage regulator circuit (e.g., the current path of 42 and 62 by passing the current pass of 40 and 60, see Fig. 1).
Claim 2, ‘731 teaches the limitations of claim 1 as discussed above. It further teaches that the supplemental current source circuit including: a variable current source (e.g., the remaining phases of the multiphase power regulator) coupled to the voltage output node; and a current control circuit to: receive the regulated current level (e.g., 705, see [0059], Fig. 7); determine the regulated current level has exceeded the current level threshold (e.g., see Fig. 7, 14A, 14B, 15); and cause the variable current source to generate the supplemental current at the voltage output node (e.g., see Fig. 7, 14A, 14B, 15).
Claim 3, ‘731 teaches the limitations of claim 2 as discussed above. It further teaches that wherein the supplemental current source circuit includes a parallel current source circuit (e.g., the remaining phases of the multiphase power regulator), the parallel current source circuit including an alternate current path to apply the supplemental current to the voltage output node (e.g., the corresponding output of the remaining phases of the multiphase power regulator, see Fig. 1-15).
Claim 4, ‘731 teaches the limitations of claim 1 as discussed above. It further teaches that the voltage regulator circuit further to reduce the regulated current level in response to the supplemental current at the voltage output node (e.g., the phase drop, see [0053][0071][0072], Fig. 14-15).
Claim 5, ‘731 teaches the limitations of claim 4 as discussed above. It further teaches that the voltage regulator circuit further to reduce the regulated current level to be substantially equal to a voltage regulator maximum efficiency current level (e.g., see Abstract, [0052][0053], Fig. 2-3).
Claim 6, ‘731 teaches the limitations of claim 2 as discussed above. It further teaches that wherein the current control circuit includes a digital control circuit (e.g., 10), the digital control circuit to cause the variable current source to increase the supplemental current at the voltage output node such that a supplemental current increase is substantially equal to a regulated current decrease (e.g., see Fig. 1).
Claim 7, ‘731 teaches the limitations of claim 6 as discussed above. It further teaches that the digital control circuit further to: receive the regulated current level from a current sensing circuit (e.g., the output of 11 and/or 704, see Fig. 1, 7); and identify a regulated current reduction in the regulated current level (e.g., when I_ave<I_dropN, see Fig. 4-6); wherein the supplemental current at the voltage output node is increased based on the regulated current reduction (e.g., when [0052], see Fig. 2-3 4-6).
Claim 11, ‘731 teaches the limitations of claim 1 as discussed above. It further teaches that the voltage regulator circuit including a control loop (e.g., the voltage control loop, see Fig. 1, 7) coupled to the voltage output node, a phase controller (e.g., 10, see Fig. 1, 7) coupled to the control loop, an inverter circuit (e.g., the corresponding buck circuit of the respective phase) coupled to the phase controller, and an inductor (e.g., the corresponding output inductor of the respective phase) coupled between the inverter circuit and the voltage output node (e.g., see Fig. 1).
For method claims 12-17, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore, the previous rejections based on the apparatus will not be repeated.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1,148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating
obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims under 35 U.S.C. 103(a), the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of 35 U.S.C. 103(c) and potential 35 U.S.C. 102(e), (f) or (g) prior art under 35 U.S.C. 103(a).
Claim 8 is rejected under 35 U.S.C. 103(a) as being unpatentable over Tang et al. (US Patent or PG Pub. No. 20090224731, hereinafter ‘731), in view of Tang (US Patent or PG Pub. No. 20180316255, hereinafter ‘255).
Claim 8, ‘731 teaches a voltage regulator circuit comprising the limitations of claim 1 as discussed above. ‘731 does not explicitly disclose that determining the current level threshold based on at least one of a maximum voltage regulator reliability current, a voltage regulator inductor saturation level, and a voltage regulator circuit temperature.
‘255 discloses a Multiphase Regulator With Thermal Adaptive Phase Add/Drop Control (e.g., see Fig. 1), and further teaches that determining the current level threshold based on at least the voltage regulator circuit temperature (e.g., see Abstract, Fig. 2-5).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date to modify ‘731 by including the Thermal Adaptive Phase Add/Drop Control as taught by ‘255 in order of being able to maximize the peak and average power demand, while also providing efficient light load operation, robust operation under peak load condition, and minimizing system cost (e.g., see [0007][0019]).
Claim 10 is rejected under 35 U.S.C. 103(a) as being unpatentable over Tang et al. (US Patent or PG Pub. No. 20090224731, hereinafter ‘731), in view of Chen et al. (US Patent or PG Pub. No. 20220166314, hereinafter ‘314).
Claim 10, ‘731 teaches a voltage regulator circuit comprising the limitations of claim 6 as discussed above. ‘731 does not explicitly disclose that wherein the voltage regulator circuit includes a switched capacitor voltage regulator.
‘314 discloses a multiphase converter further including switched-capacitor based multiphase converter (e.g., see Fig. 20b, 20c, 20d).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date to modify ‘731 by including the switched-capacitor based multiphase converter as taught by ‘314 in order of being able to leverage the state-of-the-art control techniques that have been developed for standard voltage regulation modules (VRMs). (e.g., see [0085]).
Claims 18-23 are rejected under 35 U.S.C. 103(a) as being unpatentable over Tang et al. (US Patent or PG Pub. No. 20090224731, hereinafter ‘731), in view of Luo et al. (US Patent or PG Pub. No. 20230402931, hereinafter ‘931).
Claim 18, ‘731 teaches a voltage regulator circuit comprising the limitations of claim 1 as discussed above. ‘731 does not explicitly disclose a system comprising: a memory unit; and a processing unit, the processing unit including: the voltage regulator circuit.
‘931 discloses an Information handling system (e.g., 400, see Fig. 4) comprising a memory unit (e.g., 420, 425); and a processing unit, the processing unit including voltage regulator circuit to power the processing unit (e.g., the processing unit of 400 comprising 402, 402, 495, see Fig. 4).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date to modify ‘731 by including the system as taught by ‘931 in order of being able to process the information the system received (e.g., see [0002][0021]-[0028], Fig. 4).
Claim 19, the combination of ‘731 and ‘931 teaches the limitations of claim 18 as discussed above. ‘731 further teaches that wherein the supplemental current source circuit includes a parallel current source circuit (e.g., the remaining phases of the multiphase power regulator), the parallel current source circuit including an alternate current path to apply the supplemental current to the voltage output node (e.g., the corresponding output of the remaining phases of the multiphase power regulator, see Fig. 1-15).
Claim 20, the combination of ‘731 and ‘931 teaches the limitations of claim 18 as discussed above. ‘731 further teaches that the voltage regulator circuit further to reduce the regulated current level in response to the supplemental current at the voltage output node (e.g., the phase drop, see [0053][0071][0072], Fig. 14-15).
Claim 21, the combination of ‘731 and ‘931 teaches the limitations of claim 20 as discussed above. ‘731 further teaches that the voltage regulator circuit further to reduce the regulated current level to be substantially equal to a voltage regulator maximum efficiency current level (e.g., see Abstract, [0052][0053], Fig. 2-3).
Claim 22, the combination of ‘731 and ‘931 teaches the limitations of claim 18 as discussed above. ‘731 further teaches that wherein the current control circuit includes a digital control circuit (e.g., 10), the digital control circuit to cause the variable current source to increase the supplemental current at the voltage output node such that a supplemental current increase is substantially equal to a regulated current decrease (e.g., see Fig. 1).
Claim 23, the combination of ‘731 and ‘931 teaches the limitations of claim 22 as discussed above. ‘731 further teaches that the digital control circuit further to: receive the regulated current level from a current sensing circuit (e.g., the output of 11 and/or 704, see Fig. 1, 7); and identify a regulated current reduction in the regulated current level (e.g., when I_ave<I_dropN, see Fig. 4-6); wherein the supplemental current at the voltage output node is increased based on the regulated current reduction (e.g., when [0052], see Fig. 2-3 4-6).
Claim 24 is rejected under 35 U.S.C. 103(a) as being unpatentable over Tang et al. (US Patent or PG Pub. No. 20090224731, hereinafter ‘731), in view of Luo et al. (US Patent or PG Pub. No. 20230402931, hereinafter ‘931), and further in view of Tang (US Patent or PG Pub. No. 20180316255, hereinafter ‘255).
Claim 24, the combination of ‘731 and ‘931 teaches a voltage regulator circuit comprising the limitations of claim 23 as discussed above. None of ‘731 nor ‘931 explicitly disclose that determining the current level threshold based on at least one of a maximum voltage regulator reliability current, a voltage regulator inductor saturation level, and a voltage regulator circuit temperature.
‘255 discloses a Multiphase Regulator With Thermal Adaptive Phase Add/Drop Control (e.g., see Fig. 1), and further teaches that determining the current level threshold based on at least the voltage regulator circuit temperature (e.g., see Abstract, Fig. 2-5).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date to modify ‘731 and ‘931 by including the Thermal Adaptive Phase Add/Drop Control as taught by ‘255 in order of being able to maximize the peak and average power demand, while also providing efficient light load operation, robust operation under peak load condition, and minimizing system cost (e.g., see [0007][0019]).
Allowable Subject Matter
Claims 9, 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matters:
For claim 9, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, … the digital control circuit further to: receive the regulated voltage output and an input voltage level; … determine the current level threshold based on …, the input voltage level, and voltage regulator resistance.
For claim 25, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, … the digital control circuit further to: receive the regulated voltage output and an input voltage level; … determine the current level threshold based on …, the input voltage level, and voltage regulator resistance.
Response to Arguments
Applicants’ arguments in the remarks filed on 02/26/2018 have been considered have been fully considered and please see the examiner's responses for the reasons as discussed below.
Applicants stated on pages 6-7 of the REMARKS:
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Examiner's Response:
Applicant's above arguments have been fully considered but they are not persuasive. Examiner would like to respectfully remind Applicant that the Applicant argued supplemental current path 140 is also part of the complete voltage regulator shown in Fig. 1, just as the supplemental current path for providing the supplemental current from the power input to the load 80 by the second phase circuit 42, 52, and 62 of the whole regulator of Fig. 1, which bypass the voltage regulator circuit comprising 40/50/60 as disclosed by ‘731.
In further response to applicant's argument that “… '731 therefore does not disclose a supplemental current source circuit that is structurally distinct from the voltage regulator circuit. …” Applicants are respectfully reminded that before the prior art can be applied, the Patent Office must consider the scope of the claims, and during examination, patent claims are to be given the "broadest reasonable interpretation" in light of the specification. MPEP § 2258(G); see also § 2111 (citing Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005)). Since Applicant did not limit the supplemental current path in the argued claims to any specific structure or functional details other that be able to providing a supplemental current from input source to the output and bypassing the voltage regulator circuit, or supplemental current path cannot be similar structure of the voltage regulator circuit, it is Examiner’s position that the prior art ‘271 anticipates the argued limitations as recited in the claims.
Therefore, for at least the reasons as discussed above, the grounds of the claim rejections based on ‘271 are maintained in the current office action, and the current office action is made FINAL.
Examiner's Note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUE ZHANG whose telephone number is (571)270-1263. The examiner can normally be reached on M-Th 7:30-5:00PM EST, Other F 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-2838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUE ZHANG/
Primary Examiner, Art Unit 2838
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