DETAILED ACTION This communication is in response to the application filed 12/27/22 in which claims 1-20 were presented for examination. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Allowable Subject Matter Claims 4 and 13-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Information Disclosure Statement The information disclosure statement (IDS) submitted on 12/28/22, 02/23/24, and 04/04/24 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claim s 7 and 18 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The term “ relatively long data retention ” in claim s 7 and 18 is a relative term which renders the claim indefinite. The term “ relatively ” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “ relatively short data retention ” in claim s 7 and 18 is a relative term which renders the claim indefinite. The term “ relatively ” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim 11 is rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Sengupta (US 2021/0304010 A1; published Sep. 30, 2021) . Regarding claim 11, Sengupta discloses [a] method of training a DNN model, the method comprising: a forward propagation step in which, while iterative training is performed for one or more layers of the DNN model, one or more activation nodes and a weight node perform an operation in each of the one or more layers; (Sengupta ¶ 16 (“ An artificial neural network (hereinafter, neural network) is typically implemented in a computing system, such as a neural network processor, to have an architecture based on biological neural networks, and to process input data in an analogous fashion as biological neural networks. A neural network typically includes a number of cascading neural network layers, with each layer including a set of weights. In an inference operation [forward propagation step] , a first neural network layer can receive an input data set, combine the input data with first weights of the first neural network layer (e.g., by multiplying the input data set with the weights and then summing the products, post-processing the sum, etc.) to generate first intermediate outputs, and propagate the first intermediate outputs to a second neural network layer, in a first forward propagation operation. The second neural network layer performs a second forward propagation operation by combining the first intermediate outputs with second weights of the second neural network layer to generate second intermediate outputs, and propagate the second intermediate outputs to a higher neural network layer. The forward propagation operations can start at the first neural network layer and end at the highest neural network layer. The forward propagation operation at each neural network layer can represent different stages of extraction and processing of information from the input data set. A decision can then be made based on the output data of the highest neural network layer. For example, each neural network layer can extract and/or process features from an image, and a decision of whether an object is in the image can be generated based on a result of processing the extracted features at the neural network layers. ”); Sengupta ¶ 19 (“ The training operation can be repeated for the same input data set for a number of iterations [iterative training] until a loss objective (e.g., a threshold first output error from the highest neural network layer) is achieved. ”); Sengupta ¶ 35 (“ Layer 207 may process pixel data representing different portions of image 104. For example, in the example of FIG. 2A, layer 207 may process the pixel data of image 204. Each processing node of layer 207 is assigned to receive a pixel value (e.g., x0, x1, x2, . . . xn ) corresponding to a predetermined pixel within image 104, and transmit one or more weights with the received pixel value to layer 209. In a case where prediction model 203 is a DNN, each processing node of layer 207 can be assigned a set of weights defined based on a matrix W1. Each processing node of layer 207 [e.g., weight node] can send the received pixel value and the assigned weights to each processing node of layer 209 [e.g., activation nodes] . In a case where prediction model 103 is a CNN, groups of the processing nodes of layer 207 may share a set of weights, and each group may send the set of weights and the pixel values received by the group of processing nodes to a single processing node of layer 209. Different neural network models may include different topologies (e.g., including a different number of layers, different connections between layers, etc.), and/or include a different set of weights for each layer. ”)) a back propagation step in which the one or more activation nodes and the weight node generate gradient data according to the operation in response to each forward propagation step; and (Sengupta ¶ 18 (“ The training output data, as well as target output data, can be input to a loss gradient operation to compute first output error gradients representing a partial derivative of the output errors (between the training output data and the target output data) with respect to the training output data. At the highest neural network layer, a first backward propagation operation can be performed, in which the first output error gradients can be combined with the intermediate outputs of the previous neural network layer (the second highest neural network layer) to generate first weight gradients for the highest neural network layer. The first weight gradients can represent a partial derivative of the output errors with respect to the weights of the highest neural network layer. The first weight gradients can be used to update the weights of the highest neural network layer to minimize the output errors. ”)) a step of updating, by the weight node, a final weight based on final gradient data in response to completion of operations of all the layers (Sengupta ¶ 19 (“ Moreover, the first output error gradients, received by the highest neural network layer, can be combined with the original weights of the highest neural network layer to obtain second output error gradients. In a second backward propagation operation, the second output error gradients can be propagated back to the previous layer to generate second weight gradients for updating the weights of the previous layer, and to generate third output error gradients to be propagated to the layer before the previous layer. The output error gradients can be propagated all the way to the first neural network layer in a sequence of backward propagation operations, and the weights of each layer can be updated based on the weight gradients generated for each layer. The training operation can be repeated for the same input data set for a number of iterations until a loss objective (e.g., a threshold first output error from the highest neural network layer) is achieved. ”)). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or non - obviousness. Claim s 1, 2, 5, 6, 8, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Reinhardt (US 2021/0042260 A1; published Feb. 11, 2021) in view of Choi (US 2020/0034697 A1; published Jan. 30, 2020) . Regarding claim 1 , Reinhardt discloses [a] deep neural network (DNN) accelerator system comprising: a plurality of accelerator nodes [ each including a plurality of NAND flash memories, a flash memory system (FMS) controller for controlling the plurality of NAND flash memories ] , and a tensor buffer; and (see Reinhardt ¶ 32 (“ As shown in high-level form in FIG. 1, the tensor-processing engine 108 includes one or more tensor register files 128 for storing tensor information (e.g., vectors, matrices, etc.). The tensor-processing engine 108 also includes one or more tensor operation hardware components (HCs) 130 [accelerator nodes] for performing operations in tensor-based form. The SPU 110 includes one or more scalar register files 132 for storing scalar information. The SPU 110 also includes one or more scalar operation hardware components (HCs) 134 for performing operations in scalar-based form. ”); Reinhardt ¶ 38 (“ Each tensor-processing unit includes one or more tensor register files (RFs) and one or more tensor operation hardware components (HCs). More specifically, the first tensor-processing unit 202 includes one or more tensor RFs 208 and one or more tensor operation HCs 210, the second tensor-processing unit 204 includes one or more tensor RFs 212 and one or more tensor operation HCs 214, and the third tensor-processing unit 206 includes one or more tensor RFs 216 and one or more tensor operation HCs 218. As set forth above, a tensor RF [tensor buffer] stores data in tensor form, e.g., as matrices or vectors. ”)). Reinhardt does not expressly disclose that the tensor operation hardware units are each including a plurality of NAND flash memories, a flash memory system (FMS) controller for controlling the plurality of NAND flash memories (but see Choi ¶ 31 (“ FIG. 1 is a block diagram of one embodiment of a memory system 100 connected to a host 120. Memory system 100 can implement the technology proposed herein, where the neural network inputs or other data are received from the host 120. Depending on the embodiment, the inputs can be received from the host 120 and then provided to the memory packages 104 for inferencing on the weights previously programmed into the memory arrays of the memory packages 104. ”); Choi ¶ 32 (“ Memory system 100 of FIG. 1 comprises a Controller 102 [flash memory system (FMS) controller] , non-volatile memory 104 for storing data, and local memory (e.g. DRAM/ReRAM) 106. Controller 102 comprises a Front End Processor (FEP) circuit 110 and one or more Back End Processor (BEP) circuits 112. ”); Choi ¶ 33 (“ In one embodiment, non-volatile memory 104 comprises a plurality of memory packages [ plurality of NAND flash memories] . Each memory package includes one or more memory die. Therefore, Controller 102 is connected to one or more non-volatile memory die. In one embodiment, each memory die in the memory packages 104 utilize NAND flash memory (including two dimensional NAND flash memory and/or three dimensional NAND flash memory) .”)). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Reinhardt to incorporate the teachings of Choi to use NAND flash memory strings for execution of the multiply-and-accumulate operations within the NAND memory as taught by Choi to implement the tensor operation hardware units taught by Reinhardt, at least because doing so would avoid repeated reading of weights connecting the different layers out of memory and thus reduce the computational intensity of neural networks. See Choi ¶ 2. Reinhardt further discloses a processor configured to generate an operation sequence of the plurality of accelerator nodes, (Reinhardt ¶ 30 (“ Control logic 122 supplies the instructions that govern the operation of the hardware accelerator 104. It does so based on a computer program 124 written by a human programmer. In one case, the instructions describe the operations associated with each layer or recurrent unit of a neural network, or other type of analysis engine. In one implementation, the control logic 122 represents a computing device that includes a central processing unit (CPU). Alternatively, or in addition, the control logic 122 represents a part of one or more other components of the computing system 102. For example, the control logic 122 may represent a component within the processing engines 106 and/or the VMM 112, etc. ”)) wherein a DNN model is trained in a data parallel manner using the plurality of accelerator nodes (Reinhardt ¶ 31 (“ An instruction decoder 126 maps the instructions of the computer program 124 to more primitive control commands that control the operation of different respective parts of the hardware accelerator. For example, assume that the tensor-processing engine 108 includes plural tile engines (not shown) that work in parallel to compute the product of a vector with a matrix. Further assume that computer program includes an instruction that describes this computation from a high-level perspective. Here, the instruction decoder 126 maps the high-level instruction into plural primitive control commands, each of which controls a different tile engine. The instruction decoder 126 performs the mapping between high-level instructions and low-level commands based on prescribed rules and based on one or more setup parameters. For instance, one or more setup parameters may instruct the tensor-processing engine 108 to use a specified degree of parallelism in processing input requests. ”)) . Regarding claim 2 , Reinhardt, in view of Choi, discloses the invention of claim 1 as discussed above. Reinhardt further discloses wherein the plurality of accelerator nodes operates as one or more activation nodes for performing a series of operations for DNN training or a weight node for managing weights (Reinhardt ¶ 26 (“ In some implementations, the hardware accelerator 104 represents a neural processing unit (NPU) that carries out operations associated with any type(s) of deep neural network (DNN), or other type(s) of neural network (that is, other than DNNs). Exemplary types of DNNs include convolutional neural networks (CNN), recurrent neural networks (RNNs), etc. An RNN can include long short-term memory (LSTM) units, gated recurrent units (GRUs), etc. More specifically, the computing system 102 uses the hardware accelerator 104 to expedite the application-phase operation of an already-trained DNN (where the term “application-phase” is meant to distinguish from the offline training of the DNN). ”)) . Regarding claim 5, Reinhardt, in view of Choi, discloses the invention of claim 1 as discussed above. Reinhardt further discloses wherein the FMS controller allocates blocks of the plurality of NAND flash memories based on a round-robin policy for incremental sequential writing (Reinhardt ¶ 36 (“ The tensor-processing engine 108 shown in FIG. 2 includes plural channels (channel 1, channel 2, . . . , channel C). FIG. 1 shows illustrative details of the first channel (channel 1). Other channels include the same components. Different implementations of the tensor-processing engine 108 can allocate work to different channels based on different environment-specific considerations. For instance, assume that the computer program 124 includes at least one loop that involves repeating the same series of operations. The instruction decoder 126 can allocate work associated with different iterations of the loop to different respective channels. This allows the tensor-processing engine 108 to perform work associated with the different iterations in parallel. ”)). Regarding claim 6, Reinhardt, in view of Choi, discloses the invention of claim 1 as discussed above. Reinhardt further discloses wherein the accelerator nodes position data in an independent storage area on an FMS providing different functions according to data characteristics (Reinhardt ¶ 39 (“ The first channel forms a pipeline in the sense that the output data from the first tensor-processing unit 202 serves as input data that feeds into the second tensor-processing unit 204. And the output data from the second tensor-processing unit 204 serves as input data that feeds into the third tensor-processing component 206. Each individual tensor-processing unit also organizes its tensor operation HCs in a pipeline. For example, consider the case in which the second tensor-processing unit 204 includes three tensor operation HC. The first tensor operation HC provides output data that serves as input data that feeds into the second tensor operation HC, and the second tensor operation HC provides output data that serves as input data that feeds into the third tensor operation HC. ”)). Regarding claim 8, Reinhardt, in view of Choi, discloses the invention of claim 1 as discussed above. Reinhardt further discloses wherein the tensor buffer serves as a staging area between a compute core for performing a DNN training operation and the plurality of NAND flash memories (Reinhardt ¶ 65 (“ The scalar register file (SRF) 404 includes a collection of write ports 416 having respective write addresses, and a collection of read ports 418 having respective read addresses. The vector-to-scalar interface 402 writes scalars to the write ports 416. The scalar-to-vector interface 406 retrieves one or more stored scalars from the SRF 404 from the read ports 418. ”)). Regarding claim 10, Reinhardt, in view of Choi, discloses the invention of claim 1 as discussed above. Reinhardt does not expressly disclose wherein a data path of the FMS is implemented to correspond to a physical hardware configuration (but see Choi ¶ 31 (“ FIG. 1 is a block diagram of one embodiment of a memory system 100 connected to a host 120. Memory system 100 can implement the technology proposed herein, where the neural network inputs or other data are received from the host 120. Depending on the embodiment, the inputs can be received from the host 120 and then provided to the memory packages 104 for inferencing on the weights previously programmed into the memory arrays of the memory packages 104. ”)). The rationale for combining Reinhardt with Choi is the same as set forth above. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Reinhardt and Choi as applied to claim 2 above, and further in view of Sengupta (US 2021/0304010 A1; published Sep. 30, 2021) . Regarding claim 3 , Reinhardt, in view of Choi, discloses the invention of claim 2 as discussed above. Although Reinhardt ¶ 26 teaches “ The computing system 102 can also use the hardware accelerator 104 to train a DNN or other type of neural network ,” Reinhardt does not expressly disclose wherein: a process of the DNN training includes a forward propagation step, a back propagation step, and a step of updating a final weight by the one or more activation nodes and the weight node; and the forward propagation step and the back propagation step are performed for each layer included in a DNN, and the step of updating the final weight is performed after operations for all layers included in the DNN are completed (but see Sengupta Abstract (“ Methods and systems for training a neural network are provided. In one example, an apparatus comprises a memory that stores instructions; and a hardware processor configured to execute the instructions to: control a neural network processor to perform a loss gradient operation to generate data gradients; after the loss gradient operation completes, control the neural network processor to perform a forward propagation operation to generate intermediate outputs; control the neural network processor to perform a backward propagation operation based on the data gradients and the intermediate outputs to generate weight gradients; receive the weight gradients from the neural network processor; and update weights of a neural network based on the weight gradients. ”)) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Reinhardt to incorporate the teachings of Sengupta to perform gradient descent training with updated weights at the end of a training iteration, at least because doing so would enable training a neural network to perform a certain computing task for an application. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Reinhardt and Choi as applied to claim 8 above, and further in view of Navon (US 2021/0248416 A1; published Aug. 12, 2021) . Regarding claim 9 , Reinhardt, in view of Choi, discloses the invention of claim 8 as discussed above. Although Reinhardt teaches that the tensor processing unit includes storage for tensor data, Reinhardt and Choi do not expressly disclose wherein the tensor buffer includes a double data rate (DDR) DRAM (but see Navon ¶ 20 (“ As noted above, deep learning may be accomplished by, or facilitated by, deep learning accelerators (DLAs), e.g., microprocessor devices designed to accelerate the generation of deep neural networks (DNNs) to implement deep learning. These networks may also be referred to as learning networks. In some examples, large amounts of machine learning training data are stored within a volatile memory, such as a dynamic random access memory (DRAM), for use by a deep learning machine learning processor, such as a central processing unit (CPU), graphics processing unit (GPU) or a tensor processing unit (TPU). The deep learning processor trains the DNN by repeatedly and iteratively obtaining training data from the volatile memory at very high rates and then processing the training data over various epochs. (The term epoch is discussed and defined below.) For example, many groups of data samples may be randomly (or uniformly) selected from a very large data set for processing by the deep learning processor (a method that may be referred to as “shuffling”). Alternatively, the selection of data samples (grouped into a “mini-batch”) may take into account an imbalance in data set labels (a method that may be referred to as “importance sampling” or “over/under sampling”). The selected samples are processed in one or more forward and backward passes through a neural network using a machine learning training procedure to train the DNN, such as to train an image recognition system to recognize faces. ”); Navon ¶ 43 (“ The working memory 410 may be any suitable memory, computing device, or system capable of storing data. For example, the memory 410 may be ordinary RAM, DRAM, double data rate (DDR) RAM (DDRAM), ….”)) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Reinhardt to incorporate the teachings of Navon to use DDRAM memory for storage of tensor input data, at least because DDRAM memory is volatile and is suited for repeatedly and iteratively obtaining training from the volatile memory at very high rates and then processing the training data over various epochs. See Navon ¶ 20. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Sengupta as applied to claim 11 above, and further in view of Choi . Regarding claim 12 , Sengupta discloses the invention of claim 11 as discussed above. Sengupta does not expressly disclose wherein: each of the one or more activation nodes and the weight node includes a plurality of NAND flash memories, an FMS controller for controlling the plurality of NAND flash memories, and a tensor buffer; and (but see Choi ¶ 31 (“ FIG. 1 is a block diagram of one embodiment of a memory system 100 connected to a host 120. Memory system 100 can implement the technology proposed herein, where the neural network inputs or other data are received from the host 120. Depending on the embodiment, the inputs can be received from the host 120 and then provided to the memory packages 104 for inferencing on the weights previously programmed into the memory arrays of the memory packages 104. ”); Choi ¶ 32 (“ Memory system 100 of FIG. 1 comprises a Controller 102 [flash memory system (FMS) controller] , non-volatile memory 104 for storing data, and local memory (e.g. DRAM/ReRAM) 106. Controller 102 comprises a Front End Processor (FEP) circuit 110 and one or more Back End Processor (BEP) circuits 112. ”); Choi ¶ 33 (“ In one embodiment, non-volatile memory 104 comprises a plurality of memory packages [plurality of NAND flash memories] . Each memory package includes one or more memory die. Therefore, Controller 102 is connected to one or more non-volatile memory die. In one embodiment, each memory die in the memory packages 104 utilize NAND flash memory (including two dimensional NAND flash memory and/or three dimensional NAND flash memory) .”)). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sengupta to incorporate the teachings of Choi to use NAND flash memory strings for execution of the multiply-and-accumulate operations within the NAND memory as taught by Choi to implement the tensor operation hardware units taught by Reinhardt, at least because doing so would avoid repeated reading of weights connecting the different layers out of memory and thus reduce the computational intensity of neural networks. See Choi ¶ 2. Sengupta further discloses a step of training the DNN model is started according to an operation sequence for training the DNN model (Sengupta ¶ 17 (“ The set of weights of the neural network can be generated and/or updated by a training operation to improve the likelihood of the neural network generating a correct decision. The training operation can be performed by the same computing system (e.g., a neural network processor) that performs the interference operation, or by a different system. An example training operation can use a gradient descent scheme. Specifically, as part of the training operation, the aforementioned forward propagation operations can be performed on a training input data set, using the set of weights at each neural network layer, to generate a training output data set at the highest level neural network layer. ”)) . Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Sengupta and Choi as applied to claim 12 above, and further in view of Reinhardt . Regarding claim 16 , Sengupta, in view of Choi, discloses the invention of claim 12 as discussed above. Sengupta does not expressly disclose wherein each FMS controller allocates blocks of the plurality of NAND flash memories based on a round-robin policy for incremental sequential writing (but see Reinhardt ¶ 36 (“ The tensor-processing engine 108 shown in FIG. 2 includes plural channels (channel 1, channel 2, . . . , channel C). FIG. 1 shows illustrative details of the first channel (channel 1). Other channels include the same components. Different implementations of the tensor-processing engine 108 can allocate work to different channels based on different environment-specific considerations. For instance, assume that the computer program 124 includes at least one loop that involves repeating the same series of operations. The instruction decoder 126 can allocate work associated with different iterations of the loop to different respective channels. This allows the tensor-processing engine 108 to perform work associated with the different iterations in parallel. ”)) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sengupta to incorporate the teachings of Reinhardt to allocate work to different channels according to different environment-specific considerations, at least because doing so would allow the tensor processing to be performed in parallel. Regarding claim 17 , Sengupta , in view of Choi, discloses the invention of claim 12 as discussed above. Sengupta does not expressly disclose wherein the one or more activation nodes and the weight node position data in an independent storage area on an FMS providing different functions according to data characteristics (but see Reinhardt ¶ 39 (“ The first channel forms a pipeline in the sense that the output data from the first tensor-processing unit 202 serves as input data that feeds into the second tensor-processing unit 204. And the output data from the second tensor-processing unit 204 serves as input data that feeds into the third tensor-processing component 206. Each individual tensor-processing unit also organizes its tensor operation HCs in a pipeline. For example, consider the case in which the second tensor-processing unit 204 includes three tensor operation HC. The first tensor operation HC provides output data that serves as input data that feeds into the second tensor operation HC, and the second tensor operation HC provides output data that serves as input data that feeds into the third tensor operation HC. ”)) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sengupta to incorporate the teachings of Reinhardt to allocate work to different channels according to different environment-specific considerations, at least because doing so would allow the tensor processing to be performed in parallel. Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Sengupta and Choi as applied to claim 12 above, and further in view of Navon . Regarding claim 19 , Sengupta, in view of Choi, discloses the invention of claim 12 as discussed above. Sengupta and Choi do not expressly disclose wherein the tensor buffer includes a DDR DRAM (but see Navon ¶ 20 (“ As noted above, deep learning may be accomplished by, or facilitated by, deep learning accelerators (DLAs), e.g., microprocessor devices designed to accelerate the generation of deep neural networks (DNNs) to implement deep learning. These networks may also be referred to as learning networks. In some examples, large amounts of machine learning training data are stored within a volatile memory, such as a dynamic random access memory (DRAM), for use by a deep learning machine learning processor, such as a central processing unit (CPU), graphics processing unit (GPU) or a tensor processing unit (TPU). The deep learning processor trains the DNN by repeatedly and iteratively obtaining training data from the volatile memory at very high rates and then processing the training data over various epochs. (The term epoch is discussed and defined below.) For example, many groups of data samples may be randomly (or uniformly) selected from a very large data set for processing by the deep learning processor (a method that may be referred to as “shuffling”). Alternatively, the selection of data samples (grouped into a “mini-batch”) may take into account an imbalance in data set labels (a method that may be referred to as “importance sampling” or “over/under sampling”). The selected samples are processed in one or more forward and backward passes through a neural network using a machine learning training procedure to train the DNN, such as to train an image recognition system to recognize faces. ”); Navon ¶ 43 (“ The working memory 410 may be any suitable memory, computing device, or system capable of storing data. For example, the memory 410 may be ordinary RAM, DRAM, double data rate (DDR) RAM (DDRAM), ….”)). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sengupta and Choi to incorporate the teachings of Navon to use DDRAM memory for storage of tensor input data, at least because DDRAM memory is volatile and is suited for repeatedly and iteratively obtaining training from the volatile memory at very high rates and then processing the training data over various epochs. See Navon ¶ 20. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Sengupta, Choi, Reinhardt, and Navon as variously applied to claim s 11-19 above, and further in view of Sengupta . Regarding claim 20 . Sengupta, in view of Choi and Reinhardt/Navon, discloses the invention of claims 11 to 19 as discussed above. Sengupta further discloses [a] computer-readable non-transitory recording medium storing a computer program including at least one instruction configured to execute, by a processor, the method of training the DNN model according to any one of claims 11 to 19 (Sengupta ¶ 120 (“ Storage devices, the DRAM 1030, and any other memory component in the host system 1000 are examples of computer-readable storage media. Computer-readable storage media are physical mediums that are capable of storing data in a format that can be read by a device such as the host processor 1072. Computer-readable storage media can be non-transitory. Non-transitory computer-readable media can retain the data stored thereon when no power is applied to the media. Examples of non-transitory computer-readable media include ROM devices, magnetic disks, magnetic tape, optical disks, flash devices, and solid state drives, among others. As used herein, computer-readable storage media does not include computer-readable communication media. ”)) . Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Lee, Sung-Tae, et al. "Operation scheme of multi-layer neural networks using NAND flash memory as high-density synaptic devices." IEEE Journal of the Electron Devices Society 7 (2019): 1085-1093. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT SHAHID KHAN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-0419 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F, 9-5 est . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Andrew Jung can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571)270-3779 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHAHID K KHAN/ Primary Examiner, Art Unit 2146