DETAILED ACTION
Application No. 18/089,171 filed on 12/27/2022 has been examined. In this Office Action, claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 11-15 are objected to because of the following informalities:
In claims 11-15, line 1, the term "the computer-readable storage medium" should be changed to – the non-transitory computer-readable storage medium --.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or
composition of matter, or any new and useful improvement thereof, may obtain a patent
therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Based upon consideration of all of the relevant factors with respect to the claims as a whole, claims 1-20 are determined to be directed to an abstract idea and not significantly more than the abstract idea itself. The rationale for this determination is explained below:
Claims 1, 10, 16:
At Step 1:
The claims are directed to "an apparatus" and “a non-transitory computer readable storage medium” and “a method” and thus directed to a statutory category.
At Step 2A, Prong One:
The claim recites the following limitations directed to an abstract idea:
The limitation of “determine, based on a length of an input key, whether to compute a hash value based on the input key or cause the accelerator device to compute the hash value based on the input key”, recites a mental process because human mind can determine whether to compute a hash value based on the input key by evaluation and judgement of data.
At Step 2A, Prong Two:
The claim recites the following additional elements:
-“ an accelerator device, a processor operable to execute one or more instructions, “a non-transitory computer readable storage medium, the computer readable storage medium including instructions that when executed by a processor,” which are all a high-level recitation of a generic computer components and represent mere instructions to apply the judicial exception on a computer as in MPEP 2106.05(f), which does not provide integration into a practical application and/or is Generally linking the use of the judicial exception to a particular technological environment or field of use by limiting it to a particular data source or type. See MPEP §2106.05(h) and Electric Power, 830 F.3d at 1354, 119 USPQ2d at 1742 (limiting application of abstract idea to power grid data). Therefore, the limitation does not recite any improvement to the technology.
-“ cause a hash table lookup to be performed in a hash table based on the hash value”, is insignificant extra-solution activity as mere data gathering such as ‘obtaining information’. See MPEP 2106.05(g).
Viewing the additional limitations together and the claim as a whole, nothing provides integration into a practical application.
At Step 2B:
The conclusions for the mere implementation using a computer are carried over and does not provide significantly more.
-“ cause a hash table lookup to be performed in a hash table based on the hash value” is WURC as evidenced by the court cases cited in MPEP 2106.05(d)(II) by at least "i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, ... buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network)" and "iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, ... Of P Techs., 788 F.3d at 1363."
Accordingly, at step 2B, these additional elements, both individually and in combination, do not amount to significantly more than the judicial exception. See MPEP § 2106.05. Therefore, the claim is not eligible subject matter under 35 U.S.C. 101.
The dependent claims 2-9, 11-15 and 17-20 have been fully considered as well, however, similar to the findings for claims above, these claims are similarly directed to the above-mentioned groupings of abstract ideas set forth in the 2019 PEG, without integrating it into a practical application and with, at most, a general purpose computer that serves to tie the idea to a particular technological environment, which does not add significantly more to the claims. The ordered combination of elements in the dependent claims (including the limitations inherited from the parent claim(s)) add nothing that is not already present as when the elements are taken individually. There is no indication that the combination of elements improves the functioning of a computer or improves any other technology. Their collective functions merely provide conventional computer implementation. Accordingly, the subject matter encompassed by the dependent claims fails to amount to significantly more than the abstract idea.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Fritz et al (US 2008/0052488 A1) in view of Chellapilla et al (US 2009/0070354 A1).
As per claim 1, Fritz teaches an apparatus, comprising: an accelerator device; and a processor operable to execute one or more instructions to cause the processor to: determine, based on a length of an input key, whether to compute a hash value based on the input key or cause the accelerator device to compute the hash value based on the input key ([0012], e.g., discloses wherein calculate a hash index based on the search key); and cause a hash table lookup to be performed in a hash table based on the hash value ([0014]-[0016], e.g., discloses wherein access the selected hash table entry at the calculated main memory address, compare the hash table entry that has been retrieved from the main memory with the search key in order to determine if there is match and in case of a match select the hash table entry).
Fritz does not explicitly teach determine, based on a length of an input key, whether to compute a hash value.
However, Chellapilla teaches determine, based on a length of an input key, whether to compute a hash value ([0031], e.g., discloses wherein the set of input strings is divided into buckets to allow minimal perfect hash values to be computed for large numbers of input strings, i.e., large numbers of input strings correspond to a length of an input key).
Thus, it would have been obvious to one of the ordinary skills in the art before the effective filing date of the claimed invention to apply the teachings of Chellapilla with the teachings of Fritz in order to efficiently enabling a system to compute hash values for large numbers of input strings (Chellapilla).
As per claim 2, wherein the processor determines to cause the accelerator device to compute the hash value, wherein the accelerator device computes the hash value based on the input key, the processor operable to execute one or more instructions to cause the processor to: receive, from the accelerator device, a plurality of results, determine that a first result of the plurality of results is associated with the input key, wherein the first result specifies a memory address of a returned key from the hash table and transmit, to the accelerator device, an instruction to cause the accelerator device to compare the input key and the returned key ([0039]-[0040], Fritz).
As per claim 3, wherein the instruction to cause the accelerator device to compare the input key and the returned key is to comprise a descriptor, the descriptor to specify a memory address of the input key, the memory address of the returned key, and an indication of the comparison ([0043], Fritz).
As per claim 4, wherein the accelerator device is to comprise circuitry configured to compare the input key and the returned key based on the memory address of the input key and the memory address of the returned key ([0039]-[0044], Fritz).
As per claim 5, the processor operable to execute one or more instructions to cause the processor to: receive, from the accelerator device based on the descriptor, a comparison result; and determine, based on the comparison result, whether there was a hit or a miss for the input key in the hash table ([0039]-[0044], Fritz).
As per claim 6, the processor operable to execute one or more instructions to cause the processor to: determine there was the hit for the input key in the hash table; receive, from the accelerator device, a second comparison result based on a comparison of the input key and a second returned key associated with a second result of the plurality of results; and refrain from processing the second comparison result based on the hit for the input key in the hash table ([0039]-[0044], Fritz).
As per claim 7, the instructions to cause the processor to cause the hash table lookup to be performed to comprise instructions to cause the processor to: determine, based on the length of the input key, whether to compare the input key and a returned key or cause the accelerator device to compare the input key and the returned key, wherein the returned key is associated with the hash value in the hash table ([0002], [0012]-[0016], Fritz).
As per claim 8, wherein the processor determines to cause the accelerator device to compute the hash value, wherein the accelerator device computes the hash value based on the input key, the processor operable to execute one or more instructions to cause the processor to: receive, from the accelerator device, a plurality of results associated with the hash value in the hash table, respective ones of the plurality of results associated with respective ones of a plurality of returned keys from the hash table; generate a batch descriptor comprising a plurality of descriptors, wherein a first descriptor of the plurality of descriptors is to comprise a flag; and transmit the batch descriptor to the accelerator device to cause the accelerator device to compare the input key to the respective returned key of the respective result (0039]-[0043], Fritz).
As per claim 9, the accelerator device to comprise circuitry configured to: determine, based on a second descriptor of the plurality of descriptors, that the returned key matches the input key; identify the flag in the first descriptor; and refrain from processing the first descriptor based on the determination that the returned key matches the input key and the identification of the flag (0039]-[0043], [0049], Fritz).
Regarding claims 10, 16, claims 10, 16 are rejected for substantially the same reason as claim 1 above.
Regarding claims 11-15, 17-20, claims 11-15, 17-20 are rejected for substantially the same reason as claims 2-9 above.
It is noted that any citation [[s]] to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the references should not be considered to be limiting in any wav. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. [[See, MPEP 2123]].
Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to
applicant's disclosure.
Stoimenov et al discloses US 20030135369 A1 Hash Function Based Transcription Database.
Yasuda discloses US 20220035737 A1 STORAGE APPARATUS, HIGH DIMENSIONAL GAUSSIAN FILTERING CIRCUIT, STEREO DEPTH CALCULATION CIRCUIT, AND INFORMATION PROCESSING APPARATUS
Satoh discloses US 6320522 B1 Encoding and Decoding Apparatus with Matching Length Detection Means for Symbol Strings.
Conclusion
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/Mohammad A Sana/Primary Examiner, Art Unit 2166