DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application. Claims 1 and 3-20 are currently amended; claim 2 is original.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). See the rejection under 35 U.S.C. 112 below.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “multiple input shift registers connected directly together in series and receiving the feedback bits, wherein a first input to the multiple input shift registers is provided from the multiple input exclusive-OR circuit to a first multiple input shift register of the multiple input shift registers, the first multiple input shift register providing a second input directly to a second multiple input shift register of the multiple input shift registers”. These limitations lacks written description support because the specification fails to disclose multiple input shift registers and multiple input shift registers connected directly together in series. Applicant cited paragraphs [0029, 0035-0036 and 0039] and Figures 2-5 as support for the amendments. However Figs. 2-3 merely discloses a linear feedback shift register (LFSR) 20/30 which is different from a multiple input shift register (MISR). As shown in Figs. 2-3, an LFSR merely provides a feedback signal to the flip-flops 30 but does not receive multiple inputs. Additionally, Figs. 4-5 discloses a single input shift register (SISR) which is also different from a MISR. As shown in Figs. 4-5, a SISR only receives a single input (i.e., the 1-bit data di(t) as an input), hence the name SISR. Therefore, Figs. 2-5 do not disclose a MISR let alone a plurality of MISRs. Furthermore, paragraphs [0029, 0035-0036 and 0039] also do not mention any MISR which reads
[0029] In one embodiment of the invention, the conditioning component is based on a single input shift register (SISR) circuit which significantly extends the capacity of a noise source. Assume that a noise source has N elements and generates N bits and sequentially sends each bit to the SISR component with M-bit output (M > N) and cyclically repeats each N bits to fit the output capacity. If M < N, the SISR component can be extended to the N-bit one to make M = N. For example, the SISR component can be extended by adding extra M-N flip-flops plus extra XOR elements corresponding to feedback polynomial with degree of M. This SISR component operates M clock cycles in order to provide the required number of output bits (M). In one embodiment of the invention, the performance overhead of M clock cycles can be significantly reduced by pre-computing each of M rounds.
[0035] The number of inputs of the feedback XOR gate depends on the number of K non-zero ai values. As a result, K values are taken from the outputs of at least two of the current states and XORed in order to get feedback bit f. Thus, after computations, the next state of LFSR 20 is Q(t+1) = {f, q0(t), q1(t), ..., qL-2(t)}, which represents a right-shift in bit data with a replacement bit (the feedback bit) being inserted for the starting bit value.
[0036] The block diagram of FIG. 2 can be implemented as shown in the circuit diagram of FIG. 3 where each flip flop 300, 301, ... 30L1 comprises a linear feedback shift register receiving a clock input to trigger bit shifting to the right, and with flip flop 300 receiving a feedback bit f from the output of a multiple input exclusive OR gate 32 to replace the bit value stored in flip flop 300.
[0039] This block diagram in FIG. 4 can be implemented on a gate level as shown in the circuit diagram of FIG. 5. In this embodiment, a feedback bit f is generated in a similar way as in LFSR circuit 30 but with additional (XOR) operation on the input bit di(t). The SISR circuit 50 can output from 1 to L bits from R(t) = {r0(t), r1(t), ..., rL-1(t)} = Q(t), but usually only one bit from R(t) is used as a conditioned single bit random value. In the circuit diagram of FIG. 5, flip flops 50o, 501, ... 50L-1 comprise a linear feedback shift register which receives a clock input to trigger bit shifting to the right, with flip flop 50o receiving a feedback bit f from the output of a multiple input exclusive OR gate 52 to replace the bit value stored in flip flop 5Oo, and each flip flop 50o, 501, ... 50L-1 outputting a sequence of random bits r0, r1, ... rL-1.
The MISR is disclosed in paragraph [0042] under embodiment 2 and shown in Fig. 7-8 which shows the MISR receiving multiple inputs (i.e., M-bit input), however, Fig. 8 only shows a single MISR instead of MISRs connected directly together in series. Therefore, the specification also fails to disclose a first MISR of the MISRs providing a second input directly to a second MISR of the MISRs. Claim 11 recites the same limitations as claim 1 and is rejected for the same reason. Claims 2-10 inherit the same deficiency as claim 1 by reason of dependence. Claims 12-20 inherit the same deficiency as claim 11 by reason of dependence. Claims 4-5, 7-8, 12, 14-15 and 17-18 recite instances of “multiple input shift registers” and are rejected for at least the same reason as claim 1. Claims 6-9 inherit the same deficiency as claim 5 by reason of dependence. Claim 8 inherit the same deficiency as claim 7 by reason of dependence. Claim 13 inherit the same deficiency as claim 12 by reason of dependence. Claims 16-19 inherit the same deficiency as claim 15 by reason of dependence. Claim 18 inherit the same deficiency as claim 17 by reason of dependence.
Allowable Subject Matter
Claims 1-20 would be allowable if rewritten to overcome the 35 U.S.C. 112(a) rejection discussed above.
The following is a statement of reasons for the indication of allowable subject matter:
None of the prior art references cited explicitly teach or suggest, in combination with other limitations of the claims, a random number generator comprising multiple input shift registers connected directly together in series and receiving the feedback bits, wherein a first input to the multiple input shift registers is provided from the multiple input exclusive-OR circuit to a first multiple input shift register of the multiple input shift registers, the first multiple input shift register providing a second input directly to a second multiple input shift register of the multiple input shift registers” as recited in claims 1 and 11. Furthermore, it is not obvious and there would be no motivation to modify Carlson to include multiple MISRs with any element 130A-130P of a first MISR directly providing an input to any element 130A-130B of a second MISR as required by claims 1 and 11.
Response to Arguments
In view of amendments made, the objection to claims 1-10, 14 and 18-20 has been withdrawn.
In view of amendments made, the 35 U.S.C. 103 rejection of claims 3-4 and 13-14 has been withdrawn.
Applicant’s arguments, see remarks page 8-14, filed09/08/2026, with respect to the 35 U.S.C. 102(a)(1) and (a)(2) rejection of claims 1-20 have been fully considered and are persuasive. The 35 U.S.C. 102(a)(1) and (a)(2) rejection of claims 1-20 has been withdrawn.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wang (US 11500616 B1) discloses a random number generator comprising a conditioning component comprising a XOR circuit and a linear feedback shift register (LFSR) arranged as a single input shift register (SISR) circuit as shown in Fig. 6 similar to Fig. 5 of the present application; and a noise source 302 configured to generate N sources of N noise bits as shown in Fig. 8.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlo Waje whose telephone number is (571)272-5767. The examiner can normally be reached 9:00-6:00 M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Carlo Waje/Examiner, Art Unit 2151 (571)272-5767
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