DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/27/2022 and 02/03/2023 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1-10, 14 and 18-20 are objected to under 37 C.F.R. 1.71(a) which requires “full, clear, concise, and exact terms” as to enable any person skilled in the art or science to which the invention or discovery appertains, or with which it is most nearly connected, to make and use the same. The following should be corrected.
A. In claim 1 line 8, “the N noise sources” should read “the N sources” instead for consistency of claim terminologies. Claims 2-10 inherit the same deficiency as claim 1 by reason of dependence.
B. In claim 4 line 3, “the output M bits” should read “the M random bits” instead for consistency of claim terminologies. Claim 14 recites a similar limitation and is objected to for the same reason.
C. In claim 8 line 2, “the M bits” should read “the M random bits” instead for consistency of claim terminologies. Claims 9-10 and 18-20 recite a similar limitation and are objected to for the same reason.
D. In claim 17 line 1, “providing …” should read “further comprising providing …” instead for better clarity. Claim 18 inherit the same deficiency as claim 17 by reason of dependence.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-4 and 13-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites “the internal state bits” in line 1. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this is interpreted to refer to the at least one internal state bit. Claim 13 recites a similar limitation and is rejected for the same reason.
Claim 4 recites “the feedback bit” in line 3. It is unclear which specific feedback bit if the feedback bits this is supposed to refer to or whether this is supposed to be interpreted to refer to the feedback bits. For purposes of examination, this is interpreted as the feedback bits. Claim 14 recites a similar limitation and is rejected for the same reason.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Carlson et al. (US 6954770 B1), hereinafter Carlson.
Regarding claim 1, Carlson teaches a random number generator comprising (Carlson Fig. 1 and col 2 lines 52-53; random number generator – RNG 100):
a noise source configured to generate N sources of N noise bits (Carlson Fig. 1 and col 2 lines 55-65; noise source (N sources) - set of one or more oscillators 105A-105N; Fig. 2 and col 3 lines 55-63; N noise bits – random bit output of each oscillator); and
a conditioning component comprising a multiple input exclusive-OR circuit generating feedback bits and a multiple input shift register receiving the feedback bits (Carlson Fig. 1 and col 3 lines 2-31; conditioning component – 120A-120M and 130 including 130A-130P; multiple input exclusive-OR circuit - 120A-120M; feedback bits – output of at least XOR gates 120A-120B or output of XOR gates 120A-120M; multiple input shift register – 130),
wherein the conditioning component is configured to process a sequence of the N noise bits from the N noise sources and output M random bits including the feedback bits (Carlson Fig. 1 and col 4 lines 42-49 “the output from each shift register element 130A-P … may be used as a random number by itself without inserting the same as a seed into a mixing function; M random bits - output from each shift register element 130A-P).
Regarding claim 2, Carlson teaches all the limitations of claim 1 as stated above. Further, Carlson teaches wherein the multiple input exclusive-OR circuit is configured to generate the feedback bits based on XORing a) at least one internal state bit with b) an input noise bit of the N noise bits (Carlson Fig. 1 and col 3 lines 4-9; one internal state bit – output of one shift register element; an input noise bit – output of one oscillator latched in a corresponding sampling device).
Regarding claim 3, Carlson teaches all the limitations of claim 2 as stated above. Further, Carlson teaches wherein the internal state bits are derived from a feedback polynomial (Carlson col 32-40 “a polynomial … with few terms is chosen in the design of the LFSR so that few feedback taps are used in the design of entropy generator 101 … after the output 140 of shift register element 130P is connected to the selected two-input gates to implement the polynomial, the sampling devices are connected to the two-input gates in an arbitrary manner”).
Regarding claim 4, Carlson teaches all the limitations of claim 1 as stated above. Further, Carlson teaches wherein the multiple input shift register is configured to shift data bits therein by one position right in order to add the feedback bit to a start of the output M bits (Carlson Fig. 1 and col 3 lines 48-49 “a fixed frequency clock 170 drives the shift register elements 130A-130P”).
Regarding claim 5, Carlson teaches all the limitations of claim 1 as stated above. Further, Carlson teaches wherein the multiple input shift register comprising a set of flip flops (Carlson col 3 lines 10-12 “LFSR 130 is comprised of a set of shift register elements 10 130A-130P. Each shift register element may be a flip-flop (e.g., a S-R, T, J-K, or D flip-flop)”).
Regarding claim 6, Carlson teaches all the limitations of claim 1 as stated above. Further, Carlson teaches wherein the multiple input exclusive-OR circuit comprises a set of multiple input exclusive-OR gates, with each of the multiple input exclusive-OR gates receiving a different noise bits and producing respective feedback bits (Carlson Fig. 1 and col 3 lines 1-9; set of multiple input exclusive-OR gates – at least 120A and 120M or 120A-120M; col 5 lines 1-12 “alternative embodiments may have the same number of sampling devices and gates, and every one of the gates 120A-M is connected to a different one of the sampling devices 110A-N … alternative embodiments may have a gate between every shift register element”).
Regarding claim 7, Carlson teaches all the limitations of claim 6 as stated above. Further, Carlson teaches wherein the respective feedback bits are provided to respective flip flops in the multiple input shift register (Carlson Fig. 1 and col 3 lines 23-25 “The output of each of the gates 120A-120M is coupled to the input of a different one of shift register elements 130A-P”; col 5 lines 11-12 “alternative embodiments may have a gate between every shift register element”).
Regarding claim 8, Carlson teaches all the limitations of claim 7 as stated above. Further, Carlson teaches wherein the respective flip flops in the multiple input shift register output the M bits (Carlson Fig. 1 and col 4 lines 42-49 “the output from each shift register element 130A-P … may be used as a random number by itself without inserting the same as a seed into a mixing function”).
Regarding claim 9, Carlson teaches all the limitations of claim 6 as stated above. Further, Carlson teaches wherein the set of multiple input exclusive-OR gates are configured to provide precomputation of the feedback bits prior to outputting the M bits (Carlson Fig. 1 and col 3 lines 23-25 “The output of each of the gates 120A-120M is coupled to the input of a different one of shift register elements 130A-P”).
Regarding claim 10, Carlson teaches all the limitations of claim 1 as stated above. Further, Carlson teaches wherein the conditioning component is configured to: output for the M bits a sequence of random bits r0, r1, . . . rM-1 (Carlson Fig. 1 and col 4 lines 42-49 “the output from each shift register element 130A-P … may be used as a random number by itself without inserting the same as a seed into a mixing function”).
Regarding claim 11, Carlson teaches a method for generating random numbers from N noise sources, comprising (Carlson Fig. 1 and col 2 lines 55-65; N noise sources - set of one or more oscillators 105A-105N; Fig. 2 and col 3 lines 55-63):
inputting N noise bits from the N noise sources into a conditioning component comprising a multiple input exclusive-OR circuit and a multiple input shift register (Carlson Fig. 1 and col 2 line 60 to col 3 line 31; conditioning component – 120A-120M and 130 including 130A-130P; multiple input exclusive-OR circuit - 120A-120M; multiple input shift register – 130; N noise bits – output of each oscillator latched in corresponding sampling device);
shifting values of bits in an initial state in the multiple input shift register to an adjacent bit position (Carlson Fig. 1 and col 3 lines 48-49);
generating feedback bits from the multiple input exclusive-OR circuit (Carlson Fig. 1 and col 3 lines 1-31; feedback bits - output of at least XOR gates 120A-120B or output of XOR gates 120A-120M);
inserting the feedback bits into bit positions (Carlson Fig. 1 and col 3 lines 23-24 “The output of each of the gates 120A-120M is coupled to the input of a different one of shift register elements 130A-P”); and
outputting M random bits including the feedback bits (Carlson Fig. 1 and col 4 lines 42-49 “the output from each shift register element 130A-P … may be used as a random number by itself without inserting the same as a seed into a mixing function; M random bits - output from each shift register element 130A-P).
Regarding claims 12-20, they recite substantially the same limitations as claims 2-10 respectively. Claims 2-10 analysis applies equally to claims 12-20 respectively.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Radja et al. (US 8209367 B2) discloses a random number generator comprising: a noise source configured to generate N sources of N noise bits; and a conditioning component comprising a multiple input exclusive- OR circuit generating feedback bits and a multiple input shift register receiving the feedback bits, wherein the conditioning component is configured to process a sequence of the N noise bits from the N noise sources and output M random bits including the feedback bits; wherein the multiple input exclusive-OR circuit is configured to generate the feedback bits based on XORing a) at least one internal state bit with b) an input noise bit of the N noise bits; wherein the internal state bits are derived from a feedback polynomial; wherein the multiple input shift register comprising a set of flip flops; wherein the multiple input exclusive-OR circuit comprises a set of multiple input exclusive-OR gates, with each of the multiple input exclusive-OR gates receiving a different noise bits and producing respective feedback bits; wherein the respective feedback bits are provided to respective flip flops in the multiple input shift register; wherein the respective flip flops in the multiple input shift register output the M bits, wherein the set of multiple input exclusive-OR gates are configured to provide precomputation of the feedback bits prior to outputting the M bits; and wherein the conditioning component is configured to: output for the M bits a sequence of random bits r0, r1, ... rM-1 (i.e., Radja et al. anticipates claims 1-3, 5-13 and 15-20). See Figs. 3-5 and col 4 line 1 to col 6 line 20. Further, claims 4 and 14 are obvious under 103 over Radja et al. in view of Carlson.
Jacobson et al. (US 20130073598 A1) discloses a random number generator comprising: a noise source configured to generate N sources of N noise bits; and a conditioning component comprising a multiple input exclusive- OR circuit generating feedback bits and a multiple input shift register receiving the feedback bits, wherein the conditioning component is configured to process a sequence of the N noise bits from the N noise sources and output M random bits including the feedback bits; wherein the multiple input exclusive-OR circuit is configured to generate the feedback bits based on XORing a) at least one internal state bit with b) an input noise bit of the N noise bits; wherein the internal state bits are derived from a feedback polynomial; and wherein the conditioning component is configured to: output for the M bits a sequence of random bits r0, r1, ... rM-1 (i.e., Jacobson et al. anticipates claims 1-3, 10-13 and 20). See Fig. 8B and paragraphs [0077-0080]). Further, claims 4-9 and 14-19 are obvious under 103 over Jacobson et al. in view of Carlson.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlo Waje whose telephone number is (571)272-5767. The examiner can normally be reached 9:00-6:00 M-F.
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/Carlo Waje/Examiner, Art Unit 2151 (571)272-5767
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