Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
1. This action is in response to the application filed 12/27/2022.
2. Claims 1-21 have been examined and are pending in the application.
Claim Rejections - 35 USC § 112
The following is a quotation of the second paragraph of 35 U.S.C. 112:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
3. Claims 6 and 15 are rejected under 35 U.S.C. 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention.
A. The following terms lack antecedent basis:
(i) the network (line 2 of claim 6). Correction is required.
B. The claim language in the following claims is not clearly understood: (i) As to claim 15, it is unclear whether “a network interface device” (lines 3-4) refers to “a network interface device” (line 3 of claim 13). Correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
4. Claims 1-21 are rejected under 35 U.S.C. 101 because they are directed to non-statutory subject matter.
Claims 1, 13 and 17 are rejected under 35 USC 101 because the claimed invention is directed to an abstract idea without significantly more. The claims disclose: to group one or more events into at least one group, enforce atomic processing of other events within a group of the at least one group, wherein the atomic processing comprises propagation of state changes to among events of the group, and perform parallel processing of events belonging to different groups. These steps describe the concept of a mental process, which corresponds to concepts identified as abstract ideas.
The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. The claims disclose additional limitations: a programmable event processing architecture comprising a plurality of programmable event processors, perform memory accesses separate from compute operations. These additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The additional elements when considered both individually and as an ordered combination do not amount to significantly more than the abstract idea.
As to claims 2-12, 14-16 and 18-21, these limitations are drawn to the same abstract idea as in the parent independent claims 1, 13 and 17. They do not include any additional elements that are sufficient to amount to significantly more than the judicial exception.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1, 3-13, 15-17 and 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Blott U.S Patent No. 9,519,486 in view of Das U.S Patent No. 7,509,653.
As to claim 1, Blott teaches an apparatus comprising:
a network interface device (a network interface 104, Fig. 1 and associated specifications) comprising:
a programmable event processing architecture comprising a plurality of programmable event processors (these atomic operations can be implemented in many different ways including through programmable resources, dedicated hardware blocks or through conventional microprocessors…, line 66 column 4 to line 3 column 5), wherein:
the plurality of programmable event processors are to perform memory accesses separate from compute operations (…the finding of available memory space in memory are provided in Figs. 8 and 9, which show the allocation of memory space. A hash (key I) value is generated at a step606, and a lookup in the hash table for hash (key I) is performed at a step608. It is then determined whether an item is already stored at the block610. If not, it is determined whether the available memory space is free at a block612. If the space is free, the address is added in the hash table at a block614, and the reference count is initialized and the item is marked as "recently used" at a block616…, lines 39-49 column 5),
and the plurality of programmable event processors are programmed to perform at least one transport protocol (…receives incoming requests through a network interface104. Basic network protocols are then processed in the network processing block102. Typically this would include a media access control (MAC) block, followed by UDP and TCP processing…, lines 29-34 column 4).
Blott does not teach grouping one or more events into at least one group, and to perform parallel processing of events belonging to different groups.
Das teaches an event processing system wherein the system group one or more events into at least one group, and to perform parallel processing of events belonging to different groups (…to partition incoming business events into multiple independent groups. Event queues 114 provide a direct delivery of each business object at the head of each event queue 220-224 to the MQ listeners 116 (see FIG. 1) within Interchange Server 102. Event partitioner 106 preserves the chronological order of ASBOs within each interdependent event group when delivering them to each of the event queues 220-224. This is required because events in the same group may be interdependent and consequently require maintenance of the relative sequence of issuance from application 104. Event sequencing implemented in interchange server 102 provides correct parallel processing of business events in BO mapping 118 and collaborator 122 by insuring that processed events coming out of BO mapping 118 preserves the exact chronological order of ASBOs with each interdependence event group. Maintaining this order of related events as they make their way through the Interchange Server 102 is extremely important for proper processing of the business events, for example updating to a customer's account balance must follow creation of the customer's account. The preferred embodiment maintains this event ordering, while enhancing the event sequencing technology by increasing the ability of the interchange server to process as many events in parallel as possible to utilize multiprocessing efficiency…, lines 37-61 column 4).
It would have been obvious before the effective filing date of the claimed invention to a person of ordinary skill in the art to have modified Blott reference to include the teachings of Das reference because by grouping events and performing parallel processing of events belonging to different groups, the system could process as many events in parallel as possible to utilize multiprocessing efficiency, as disclosed by Das.
As to claim 3, Blott as modified further teaches at least one circuitry to store packets accessed by at least one of the plurality of programmable event processors to parse and/or edit the packets (…A transaction protocol parser106 receives the input data by way of the network processing circuit102 and determines which of the atomic operations in the pipeline need to be enabled for each transaction…, lines 8-12 column 3).
As to claim 4, Blott as modified further teaches at least one memory to store protocol state for access by at least one of the plurality of programmable event processors to implement a transport protocol (…The atomic operations which need to be enabled, which could be considered the "state" of a transaction, is then encoded as meta-data accompanying the data through the pipeline…, lines 12-15 column 3).
As to claim 5, Blott as modified further teaches an arithmetic logic unit (ALU) core resource pool to update event data and protocol state (…Packets generated by the networking processing block are then passed to the transaction protocol parser106 which determines which of the atomic operations need to be activated as the packet flows through the processing pipeline. The processing blocks which need to be activated, which may be considered a processing transaction state, is then passed together with the packet through the pipeline. This could be in many forms, such as a side-band channel, a sub-channel, or a prepend to the packet. Each stage in the processing pipeline then examines relevant state bits to decide what processing (if any) to perform on a packet before passing it onto the next stage…, lines 34-46 column 4).
As to claim 6, Das further teaches a scheduler to arbitrate among connection queues to forward into the network and/or to an application (…Adapter agent 105 receives events from application 104 and creates ASBOs by querying the appropriate information from application 104. These ASBOs representing business events are then partitioned into independent groups utilizing event partitioner 106. Adapter agent 105 passes the partitioned business events to MQ server 107, in the form of ASBOs 112, for storage into allocated event queue within event queues 114. MQ server 107 presents the event queues 114 to a plurality of MQ listeners 116, which provide multiple threads for parallel processing by BO mapping 118. Each of the multiple listening threads in MQ listeners 116 handles business events coming from a uniquely associated event queue within event queues 114. Within Interchange Server 102, BO mapping 118 performs a conversion of the ASBOs into generic business objects (GBO) 115. The multi-processed GBOs 115 are then serialized by block 120 (published to collaboration) and sent to collaborator 122. Collaborator 122 executes a process called collaboration on received GBOs to perform specific business operations and other conversions of protocols, formats and commands to implement the interchange between the sourcing applications (104, 108, 109) and those applications (104, 108, 109) subscribing to Interchange Server 102 for access to such business events…, line 61 column 3 to line 16 column 4). Note the discussion of claim 1 above for the reason of combining references.
As to claim 7, Das further teaches a scheduler to schedule events to be processed based on time (…each of the business objects 202-214 is associated with a particular application (represented by "a.sub.i", where i is an integer number identifying a particular application), and has a relative time-based sequence of when the event object was issued by source application 104 (represented by the identifier "t.sub.j", where j is an integer number indicating a relative time). The use of time-based sequencing in FIG. 2 is only an example; it will be appreciated that other sequencing can be utilized to implement event sequencing. In the example shown, business object 212 is shown to be related to application a.sub.1 and occurring at a time t.sub.5; business object 210 is also related to application a.sub.1 and occurred at a time t.sub.4, prior to the time associated with business object 212. As seen in FIG. 2, event queues 114 are loaded with each of the independent event groups generated from lock table 300 by event partitioner 106 such that each business object in a given event group is sent to its corresponding event queue in event sequence…, lines 1-18 column 7). Note the discussion of claim 1 above for the reason of combining references.
As to claim 8, Blott as modified further teaches a memory interface to fetch protocol state to on-chip memory and evict protocol state from the on-chip memory (…It is then determined whether the item is stale at a block716. An item can be determined to be stale based upon an "expiry time". If the item is stale, the item is deleted to free up space at a block718, and an empty response is provided to the client at a block720. If the item is not stale, the item is marked as "recently used" at a block722. An updated item is then written back to the DRAM at a block724, and a response including a key and a value is provided to the client at a block726…, lines 8-17 column 6).
As to claim 9, Blott as modified further teaches a circuitry to route events between the plurality of programmable event processors to allow bypass of a programmable event processor and recirculation of events (…As the transaction flows through the pipeline, the basic operations are then selectively executed or bypassed depending on the meta-data…, lines 17-19 column 3).
As to claim 10, Blott as modified further teaches the programmable event processing architecture comprises one or more of. linear pipeline, linear pipeline with event recirculation support, linear pipeline with bypass support for a programmable event processor, and/or linear pipeline with forward and/or reverse arbitrated buses (…establishing a pipeline of processing blocks, wherein each processing block has a different function; coupling a data packet having data and meta-data to an input of the pipeline of processing blocks; and processing the data of the data packet using predetermined processing blocks based upon the meta-data…, lines 49-54 column 1).
As to claim 11, Blott as modified further teaches an event switch to route scheduling related events between the plurality of programmable event processors and at least one scheduler (…A transaction protocol parser106 receives the input data by way of the network processing circuit102 and determines which of the atomic operations in the pipeline need to be enabled for each transaction. The atomic operations which need to be enabled, which could be considered the "state" of a transaction, is then encoded as meta-data accompanying the data through the pipeline. The meta-data can also be used to convey intermediate results between the atomic processing blocks. As the transaction flows through the pipeline, the basic operations are then selectively executed or bypassed depending on the meta-data…, lines 8-19 column 3).
As to claim 12, Blott as modified further teaches the plurality of programmable event processors are programmed to perform at least one transport protocol based on an event graph description with defined nodes (…the transactions on a key-value store are broken down into basic or "atomic" operations. Each atomic operation is represented by a dedicated block of programmable resources or by a more programmable micro- processor. A sequence of atomic processing blocks is arranged to form a dataflow pipeline which maintains partial order between transactions…, line 62 column 2 to line 1 column 3).
As to claim 13, note the discussion of claim 1 above. Blott as modified further teaches the plurality of programmable event processors are to enforce atomic processing of other events within a group of the at least one group, wherein the atomic processing comprises propagation of state changes to among events of the group (…Packets generated by the networking processing block are then passed to the transaction protocol parser106 which determines which of the atomic operations need to be activated as the packet flows through the processing pipeline. The processing blocks which need to be activated, which may be considered a processing transaction state, is then passed together with the packet through the pipeline. This could be in many forms, such as a side-band channel, a sub-channel, or a prepend to the packet. Each stage in the processing pipeline then examines relevant state bits to decide what processing (if any) to perform on a packet before passing it onto the next stage…, lines 34-46 column 4).
As to claims 15-16, note the discussions of claims 12 and 7 above, respectively.
As to claim 17, note the discussion of claim above 13.
As to claims 19-20, note the discussions of claims 12 and 7 above, respectively.
As to claim 21, Blott as modified further teaches the transport layer protocols comprise two or more of: remote direct memory access (RDMA) over Converged Ethernet (RoCE), RoCEv2, scalable reliable datagram (SRD), Elastic Fabric Adapter (EFA), Distributed Universal Access (DUA) and Lightweight Transport Layer (LTL), High Precision Congestion Control (HPCC), improved RoCE NIC (IRN), Homa, NDP, and/or EQDS (…the data may be processed according to different protocols which may be proprietary protocols or public protocols which conform to data transmission standards…, lines 14-17 column 1).
6. Claims 2, 14 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Blott in view of Das, and further in view of Abdelmalek U.S Publication No. 2023/0344774.
As to claim 2, Blott as modified by Das does not teach a process interface to transmit and receive congestion control events and control plane events, wherein a processor is to perform congestion control and/or control plane software.
Abdelmalek teaches a system of plane congestion control service (paragraphs 0014-0018 page 2). It would have been obvious before the effective filing date of the claimed invention to a person of ordinary skill in the art to have modified Blott reference as modified by Das reference to include the teachings of Abdelmalek reference because by using a plane congestion control service, the system allows dynamic configuration of admission control information within networks, as disclosed by Abdelmalek.
As to claim 14, note the discussion of claim 2 above.
As to claim 18, note the discussion of claim 2 above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S Patent No. 10,645,155 discloses a scalable parallel messaging process in a CMS.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andy Ho whose telephone number is (571) 272-3762. A voice mail service is also available for this number. The examiner can normally be reached on Monday – Friday, 8:30 am – 5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Kevin Young can be reached on (571) 270-3180.
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/Andy Ho/
Primary Examiner
Art Unit 2194