DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 18-20 are objected to because of the following informalities:
[A] Claim 18:Line 3 – more operations to cause.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 8-10, and 13-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ramanujan et al. (US PGPub 2014/0304475 A1), hereinafter referred to as RAMANUJAN.
Consider Claim 1,
RAMANUJAN teaches an apparatus comprising:
a memory side cache to store a portion of data to be stored in a main memory (RAMANUJAN, e.g., Fig 1(121), near memory is memory side cache.); and
logic circuitry to determine whether to allocate a portion of the memory side cache for use by a device (RAMANUJAN, e.g., ¶0095, CPU may be a graphics processor (i.e., a device).), wherein a remaining portion of the memory side cache is to be used by a processor (RAMANUJAN, e.g., ¶0203, increase, decrease, or add region.),
wherein the allocated portion of the memory side cache is to be reallocated for use by the processor in response to a determination that the allocated portion of the memory side cache is no longer to be used by the device (RAMANUJAN, e.g., Fig 7B, deactivate portion; ¶0203, increase a first region by decreasing a second region.).
Consider Claim 2,
RAMANUJAN further teaches wherein all traffic directed to the main memory is to be transmitted through the memory side cache (RAMANUJAN, e.g., ¶0072, every write is directed initially to the cache; ¶0186, Table A, write-back mode.).
Consider Claim 3,
RAMANUJAN further describes wherein the logic circuitry is to determine whether to allocate the portion of the memory side cache based at least in part on a class of service associated with the device (RAMANUJAN, e.g., ¶0186, Table A, different modes (associated with different devices) have different cache use cases at least partially based on service class (¶0185, direct access mode for high performance computing).)
Consider Claim 8,
RAMANUJAN further teaches wherein the logic circuitry is to determine whether to allocate the portion of the memory side cache based at least in part on a status of a battery life mode (RAMANUJAN, e.g., ¶0006, power may be supplied by a battery; ¶0274. Detect power dropping below a threshold; ¶0214, deactivate portions of the cache in response to a power management policy. The allocation decision is based at least in part on the size of the active cache area remaining as a result of the power management policy.).
Consider Claim 9,
RAMANUJAN further teaches wherein the allocated portion of the memory side cache comprises one or more buffers (RAMANUJAN, e.g., ¶0069, may be a write buffer.).
Consider Claim 10,
RAMANUJAN further teaches wherein the logic circuitry is to determine whether to allocate the portion of the memory side cache based at least in part on buffer annotation information (RAMANUKAN, e.g., ¶0251, dynamically adjust cache size based on usage metrics. Usage metrics may be buffer annotation information.).
Consider Claim 13,
RAMANUJAN further teaches wherein the logic circuitry is to be coupled between the memory side cache and a main memory fabric (RAMANUJAN, e.g., Fig 5A, control logic circuitry is illustrated as being between the main memory and the cache.).
3Consider Claim 14,
RAMANUJAN further teaches wherein the determination that the allocated portion of the memory side cache is no longer to be used by the device is to be made based at least in part on a counter value or a timer (RAMANUJAN, e.g., ¶0251, dynamically adjust cache size based on usage metrics such as occupancy and miss rates; ¶0224, region occupancy counter; ¶0225, time interval measurement.).
Consider Claim 15,
RAMANUJAN further teaches wherein the device is to communicate with the memory side cache via a main memory fabric (RAMANUJAN, e.g., Fig 5A, illustrates device communication with MSC through MCA channels (i.e., fabric) to the main memory).
Consider Claim 16,
RAMANUJAN further teaches wherein a System on Chip comprises the logic circuitry, the memory side cache, and the device (RAMANUJAN, e.g., Fig 4A, processor/device includes MSC logic; ¶0063, near memory (i.e., MSC) may also be located on the processor die.).
Consider Claim 17,
RAMANUJAN further teaches wherein the device comprises one of: graphics logic, media logic, a Vision Processing Unit (VPU), Input/Output (IO) logic, and an Infrastructure Processing Unit (IPU) (RAMANUJAN, e.g., ¶0095-0096, graphics processor.).
Claims 18-20 are directed towards a non-transitory media including limitations which are substantially identical in scope to those of Claims 1-3 and are rejected for the same reasons.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 6, 7, 11, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over RAMANUJAN.
Consider Claim 6,
RAMANUJAN teaches the apparatus of claim 1, and further teaches memory to store data structures, wherein the data structures are to store information regarding per device resource size (RAMANUJAN, e.g., ¶0193, range register.) and per device resource utilization (RAMANUJAN, e.g., ¶0223-0225).
RAMANUJAN describes storing size information in a table, but details that the resource utilization metrics are stored elsewhere. However, it would have been obvious to a person of ordinary skill in the art, prior to the effective filing date of the claimed invention, to modify the system of RAMANUJAN as a matter of design choice because it combines structures such that all data is accessible through a single table.
Consider Claim 7,
The modified system of RAMANUJAN further teaches wherein the logic circuitry is to cause an update to the table after each allocation of the memory side cache (RAMANUJAN, e.g., ¶0203, update range register (in response to an allocation actions).).
Consider Claim 11,
RAMANUJAN teaches the apparatus of claim 10, above, and further teaches wherein the buffer annotation information is to be provided to the logic circuitry by the cache (RAMANUJAN, e.g., counter information is provided from the cache).
RAMANUJAN further describes that the cache control information may exist within the processor/device (RAMANUJAN, e.g., Fig 3:310), but fails to expressly describe wherein annotation information is to be provided to the logic circuitry by the device. In the system of RAMANUJAN, illustrated in Figure 3, the only two places the information may be is one of the memory and storage subsystem, or the processor. It would have been obvious to a person of ordinary skill in the art, prior to the effective filing date of the claimed invention, to modify the system of RAMANUJAN such that the data is stored on, and thus provided by, the device because it is one of only a limited number of options and provides the obvious benefit of eliminating higher latency memory accesses when accessing the annotation information.
Consider Claim 12,
RAMANUJAN teaches the apparatus of claim 10, above, and further teaches wherein the buffer annotation information is to be provided to the logic circuitry by the cache (RAMANUJAN, e.g., counter information is provided from the cache).
RAMANUJAN further describes that the cache control information may exist within the processor/device (RAMANUJAN, e.g., Fig 3:310) and further describes that cache control may be completely under software control (RAMANUJAN, e.g., ¶0185), but fails to expressly describe wherein annotation information is to be provided to the logic circuitry by the device. In the system of RAMANUJAN, illustrated in Figure 3, the only two places the information may be is one of the memory and storage subsystem, or the processor which includes software running on the processor. It would have been obvious to a person of ordinary skill in the art, prior to the effective filing date of the claimed invention, to modify the system of RAMANUJAN such that the data is stored on, and thus provided by, software (i.e., a driver) operating the device because it is one of only a limited number of options and provides the obvious benefit of eliminating higher latency memory accesses for software running on the processer when accessing the annotation information.
Allowable Subject Matter
Claims 4 and 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The examiner notes that Normalized Bandwidth Savings (NBS) is a concept explicitly defined in the applicant’s specification (see, e.g., ¶0043-0047).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Gary W Cygiel whose telephone number is (571)270-1170. The examiner can normally be reached Monday - Thursday 11am-3pm PST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan P Savla can be reached at (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Gary W. Cygiel/ Primary Examiner, Art Unit 2137
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