DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of group I, claims 1-8 and 16-20 , in the reply filed on 23 March 2026 is acknowledged. Claims 9-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 23 March 2026. Information Disclosure Statement Information disclosure statement filed 26 October 2023 has been fully considered. Claim Objections Claim 6 is objected to because of the following informalities: Claim 6 recites the limitation, “a second r buildup layer contacting the second surface buffer layer.” This appears to contain a typographical error and may be corrected as, “a second [[r ]]buildup layer contacting the second surface buffer layer.” Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim s 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by We et al. (US Patent Application Publication 2015/0257282, hereinafter We ‘282). With respect to claim 1 , We ‘282 teaches (FIG. 2A) a substrate for an electronic system as claimed , the substrate comprising: a glass core layer (200) ([0022]) including: a first surface (top surface) and a second surface (bottom surface) opposite the first surface ([0022]) ; and at least one through-glass via (TGV) (215 and 220) extending through the glass core layer (200) from the first surface to the second surface ([0022-0024]) , the TGV including: an opening filled with an electrically conductive material (220) ([0022]) ; and a via liner (215) including a sidewall material disposed on a sidewall of the opening between the glass of the glass core layer (200) and the electrically conductive material (220) , wherein the sidewall material includes carbon ([0023-0024]) . With respect to claim 2 , We ‘282 teaches wherein the sidewall material comprises parylene ([0024]) . With respect to claim 3 , We ‘282 teaches wherein a modulus of the sidewall material is in a range of 70-690 MegaPascals (MPa) ([0024]) . It is noted that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, claimed properties or functions are presumed to be inherent. In re Best , 195 USPQ 430, 433 (CCPA 1977). It has also been held that products of identical chemical composition cannot have mutually exclusive properties. A chemical composition and its properties are inseparable. Therefore, if the prior art teaches the identical chemical structure, the properties Applicant discloses and/or claims are necessarily present. In re Spada , 15 USQP2d 1655, 1658 (Fed. Cir. 1990). In this case, the sidewall material of We ‘282 would inherently have the property of a modulus in a range of 70-690 MegaPascals (MPa) because the sidewall material is made of parylene, which is the same as the sidewall material as disclosed. With respect to claim 4 , We ‘282 teaches including: a first surface buffer layer (215 formed on a top surface of glass core layer 200) of the sidewall material disposed on the first surface (top surface) of the glass core layer (200) ; a second surface buffer layer (215 formed on a bottom surface of glass core layer 200) of the sidewall material disposed on the second surface (bottom surface) of the glass core layer; and wherein the via liner (215) extends from the first surface buffer layer to the second surface buffer layer ([0023]) . With respect to claim 5 , We ‘282 teaches wherein the electrically conductive material (220) of the TGV (215 and 220) extends through the first surface buffer layer (215 formed on a top surface of glass core layer 200) , and a width of the electrically conductive material in the first surface buffer layer is the same as a width of the electrically conductive material within the TGV below the first surface buffer layer ([0022-0024]) . With respect to claim 6 , We ‘282 teaches including a first buildup layer (240) contacting the first surface buffer layer (215 formed on a top surface of glass core layer 200) and a second r buildup layer (250) contacting the second surface buffer layer (215 formed on a bottom surface of glass core layer 200) , wherein the first and second buildup layers include electrically conductive interconnect contacting the at least one TGV (215 and 220) ([0022]) . Claim s 16 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kawai (US Patent Application Publication 2018/0007792, hereinafter Kawai ‘792). With respect to claim 16 , Kawai ‘792 teaches (FIG. 16) an electronic system as claimed , the system comprising: a substrate (10, 50, 60, and 64) ([0066, 0103, 0113, 0131]) including: a glass core layer (10) including at least one through-glass via (TGV) (50 and 60) extending through the glass core layer, the TGV including an electrically conductive material (60) and a via liner (50) of a sidewall material disposed on a sidewall of TGV between the glass of the glass core layer and the electrically conductive material ([0066, 0103, 0113]) ; and a first buildup layer (64) on a first surface (top surface) of the glass core layer (10) and including electrically conductive interconnect ([0131]) ; and an integrated circuit (IC) die (70) attached to the first buildup layer (64) and having at least one bonding pad (72) ([0173]) ; and wherein the electrically conductive interconnect of the first buildup layer (64) electrically connects the at least one bonding pad (72) of the IC die (70) to the at least one TGV (50 and 60) . With respect to claim 19 , Kawai ‘792 teaches including a first surface buffer layer (50 formed on a top surface of glass core layer 10) of the sidewall material disposed on the first surface (top surface) of the glass core layer (10) and contacting the via liner (50) ([0066]) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over We ‘282 as applied to claim 6 above, and further in view of Ganesan et al. (US Patent Application Publication 2021/0035911, hereinafter Ganesan ‘911) . With respect to claim s 7 and 8 , We ‘282 teaches the device as described in claim 6 above with the exception of the additional limitations including a multi-die interconnect bridge (MIB) disposed in the first buildup layer, and the electrically conductive interconnect of the first buildup layer provides electrical continuity between the at least one TGV and the MIB ; and including: at least one bonding pad on a first surface of the substrate; and wherein the MIB and the electrically conductive interconnect of the first buildup layer provide electrical continuity between the at least one TGV and the at least one bonding pad. However, Ganesan ‘911 teaches (FIG. 1) a substrate including a multi-die interconnect bridge (MIB) (140) disposed in a first buildup layer (119) , and an electrically conductive interconnect of the first buildup layer provides electrical continuity between at least one TGV (121) and the MIB ; and including: at least one bonding pad (152) on a first surface of the substrate; and wherein the MIB and the electrically conductive interconnect of the first buildup layer provide electrical continuity between the at least one TGV and the at least one bonding pad ([0018, 0019, 0025]) in an arrangement that improves bridge pitch scaling, reduc es interconnect physical area on the dies, lower s assembly costs , and eliminat es the need for expensive silicon interposer ([0013]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the substrate of We ‘282 including a multi-die interconnect bridge (MIB) disposed in the first buildup layer, and the electrically conductive interconnect of the first buildup layer provides electrical continuity between the at least one TGV and the MIB ; and including: at least one bonding pad on a first surface of the substrate; and wherein the MIB and the electrically conductive interconnect of the first buildup layer provide electrical continuity between the at least one TGV and the at least one bonding pad as taught by Ganesan ‘911 in an arrangement that improves bridge pitch scaling, reduc es interconnect physical area on the dies, lower s assembly costs , and eliminat es the need for expensive silicon interposer . Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kawai ‘792 as applied to claim 16 above, and further in view of Patil et al. (US Patent Application Publication 2021/0272931, hereinafter Patel ‘931) . With respect to claim 17 , Kawai ‘792 teaches the device as described in claim 16 above, including the additional limitation including: a second buildup layer (64) on a second surface (lower surface) of the glass core layer (10) and including electrically conductive interconnect ([0131]). Thus, Kawai ‘792 is shown to teach all the features of the claim with the exception of at least one discrete passive component attached to the second buildup layer and electrically connected to the at least one TGV by the electrically conductive interconnect of the second buildup layer. However, Paten ‘931 teaches (FIG. 3) at least one discrete passive component (204) attached to a second buildup layer (240) and electrically connected to at least one via (222 formed in substrate 202) by an electrically conductive interconnect of the second buildup layer to provide elements like resistors or capacitors to the substrate ([0026-0027, 0030-0031]) Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the system of Kawai ‘792 including at least one discrete passive component attached to the second buildup layer and electrically connected to the at least one TGV by the electrically conductive interconnect of the second buildup layer as taught by Patil ‘931 to provide elements like resistors or capacitors to the substrate. Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Kawai ‘792 as applied to claim 16 above, and further in view of We ‘282. With respect to claim 18 , Kawai ‘792 teaches the device as described in claim 16 above with the exception of the additional limitation wherein a modulus of the sidewall material is in a range of 70-690 MegaPascals (MPa). However, We ‘282 teaches (FIG. 2A) parylene as a known material suitable for the intended use as a via liner (215) ([0024]). T he selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination. Sinclair & Carroll Co. v. Interchemical Corp. , 325 U.S. 327, 65 USPQ 297 (1945) and In re Leshin , 277 F.2d 197, 125 USPQ 416 (CCPA 1960). See MPEP 2144.07. Further, i t is noted that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, claimed properties or functions are presumed to be inherent. In re Best , 195 USPQ 430, 433 (CCPA 1977). It has also been held that products of identical chemical composition cannot have mutually exclusive properties. A chemical composition and its properties are inseparable. Therefore, if the prior art teaches the identical chemical structure, the properties Applicant discloses and/or claims are necessarily present. In re Spada , 15 USQP2d 1655, 1658 (Fed. Cir. 1990). In this case, the sidewall material of We ‘282 would inherently have the property of a modulus in a range of 70-690 MegaPascals (MPa) because the sidewall material is made of parylene, which is the same as the sidewall material as disclosed. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed a modulus of the sidewall material of Kawai ‘792 in a range of 70-690 MegaPascals (MPa) as taught by We ‘282 when using a known material suitable for the intended use as a via liner. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kawai ‘792 as applied to claim 16 above, and further in view of Ganesan ‘911 . With respect to claim 20 , Kawai ‘792 teaches the device as described in claim 16 above with the exception of the additional limitation including: a multi-die interconnect bridge (MIB) disposed in the first buildup layer; and wherein the MIB and the electrically conductive interconnect of the first buildup layer provide electrical continuity between the at least one TGV and the IC die. However, Ganesan ‘911 teaches (FIG. 1) a system including a multi-die interconnect bridge (MIB) (140) disposed in a first buildup layer (119) ; and wherein the MIB and an electrically conductive interconnect of the first buildup layer provide electrical continuity between at least one TGV (121) and an IC die (110 and 111) ([0018, 0019, 0025]) in an arrangement that improves bridge pitch scaling, reduc es interconnect physical area on the dies, lower s assembly costs , and eliminat es the need for expensive silicon interposer ([0013]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the system of Kawai ‘792 including: a multi-die interconnect bridge (MIB) disposed in the first buildup layer; and wherein the MIB and the electrically conductive interconnect of the first buildup layer provide electrical continuity between the at least one TGV and the IC die as taught by Ganesan ‘911 in an arrangement that improves bridge pitch scaling, reduc es interconnect physical area on the dies, lower s assembly costs , and eliminat es the need for expensive silicon interposer . Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure : Palmer et al. (US Patent Application Publication 2003/0038344); Farnworth et al. (US Patent Application Publication 2005/0150683); Pietambaram et al. (US Patent Application Publication 2023/0395467); Yang et al. (US Patent Application Publication 2024/0186264); and Duan et al. (US Patent Application Publication 2025/0006569) teach through-glass vias (TGVs). Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT Christopher M. Roland whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-1271 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday-Friday, 10:00AM-7:00PM Eastern . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Yara Green can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571)270-3035 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.M.R./ Examiner, Art Unit 2893 /YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893