DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS), submitted on 04/05/2024 12/28/2023, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to because: the unlabeled rectangular box(es) shown in the drawings, FIG. 2A:220,222,211A,211B, FIG. 2B, should be provided with descriptive text labels. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 10 is objected to because of the following: Line 3, there is an extra “v” before the line. Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 19 is rejected under 35 U.S.C. 101 because: Claim 19 is directed at a system and also a method, and hence, directed at two categories of patent eligible subject matter. Claim 19 needs to be directed to only one category of patent eligible subject matter. Claim 19 needs to be rewritten to be directed at a system.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, line 3, recites “using a device identifier”, which device is this referring to?
Claim 1, line 4, recites “unique device address”, which device is this referring to?
Claim 1, line 5: “encapsulating each of the plurality of packets” needs to be changed to: -- encapsulating each of the first plurality of packets --, for proper antecedent basis.
Claim 1, it is unclear which device performs the “receiving” function. Furthermore, it is unclear which device performs the functions, associated with all clauses. In addition, is it the same device, as for Claim 5?
Claim 5, it is unclear which device performs the functions, associated with all clauses.
Claim 5, line 3, recites “using a device identifier”, which device is this referring to?
Claim 8, line 3, it is unclear what is meant by “mapping the I/O queues to the first device and to the second device”.
Claim 15, line 2, 3, recites “unique device address”, which device is this referring to?
Claim 15, line 5, recites “device identifier”, which device is this referring to?
Claim 16, line 2, 3, recites “unique device address”, which device is this referring to?
Claim 16, line 5, recites “device identifier”, which device is this referring to?
Claim 17, line 2, 3, recites “unique device address”, which device is this referring to?
Claim 17, line 5, recites “device identifier”, which device is this referring to?
Claim 18, line 2, 3, recites “unique device address”, which device is this referring to?
Claim 18, line 4-5, recites “device identifier”, which device is this referring to?
The dependent Claims do not cure the deficiency, in their parent Claims.
Claim 19, it is unclear which device performs the “receiving” function. Furthermore, it is unclear which device performs the functions, associated with all clauses.
Claim 19, line 4, recites “using a device identifier”, which device is this referring to?
Claim 19, line 5, recites “unique device address”, which device is this referring to?
Claim 19, line 5: “BDF” needs to be defined, spelled out, in the Claim.
Claim 19 recites the limitation “the BDF” in line 5. There is insufficient antecedent basis for this limitation in the claim.
Claim 20, it is unclear which device performs the “receiving” function. Furthermore, it is unclear which device performs the functions, associated with all clauses.
Claim 20, line 5, recites “using a device identifier”, which device is this referring to?
Claim 20, line 6, recites “unique device address”, which device is this referring to?
Claim 20, line 6: “BDF” needs to be defined, spelled out, in the Claim.
Claim 20 recites the limitation “the BDF” in line 6. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 4-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chappell (US 20060206655 A1) in view of LAL (US 20220094590 A1).
Examiner note: Applicant is requested to, also, carefully review the references, in the Conclusion section, below.
Claim 1.
Chappell teaches a method for communication, comprising: receiving a first plurality of packets from a first device, wherein the first plurality of packets is addressed to a second device of a plurality of devices using a device identifier ([0019] AS uses a path-defined routing methodology in which the source of an AS packet provides all information required by a switch (or switches) to route the AS packet to the desired destination. FIG. 3 shows an AS transaction layer packet (TLP) format 300. The AS packet includes an AS header 302 and an encapsulated packet payload 304. The AS header 302 contains the information (i.e., "the path") that is necessary to route the AS packet through the AS fabric 102, and a field that specifies the Protocol Interface (PI) of the AS payload 304. AS switch elements route AS packets using the information contained in the AS header 302 without necessarily requiring interpretation of the contents of the AS payload 304); mapping the device identifier of the second device to a unique device address; encapsulating each of the plurality of packets to generate a first plurality of encapsulated packets ([0021] The PI field in the AS route header 302 determines the format of the encapsulated packet payload 304. The PI field is inserted by the AS endpoint 104 that originates the AS packet and is used by the AS endpoint 104 that terminates the AS packet to correctly interpret the packet contents. The separation of routing information from the remainder of the AS packet enables the AS fabric 102 to tunnel packets of any protocol); and communicating each of the first plurality of encapsulated packets over a fabric network, wherein the unique device address of the second device is used to route the first plurality of encapsulated packets to the second device ([0037] For the PI-8 host switch 510, which is implemented to logically function as a PCIe switch, traffic routed through each of the downstream ports is physically transported via a single AS physical layer 210, AS data link layer 208, and AS transaction layer 206 stack. To accomplish this, the downstream tunneling processor 524 pre-pends a unique AS header that routes the encapsulated PCIe packet through the AS fabric 102 to the destination I/O switch at an AS-PCIe bridge 108a-108d. Since the PCIe packet is not physically transferred from an upstream port to a downstream port, all downstream packet validation and routing functions are performed by the downstream tunneling processor 524 for all ports in the PI-8 host switch 510).
Chappell does not explicitly teach the combination of the underlined feature, above; as interpreted in light of the disclosure, namely, device identifier bus: device: function identifier.
Chappell does not explicitly teach the combination of these features: mapping the device identifier of the second device to a unique device address; as interpreted in light of the disclosure, namely, device identifier bus: device: function identifier.
The missing elements are disclosed by LAL ([0097] fNIC core 910 can include a lookup table, such as content addressable memory (CAM) 922, that matches a key (e.g., XPU ID, bus device function, and/or address mapped to a BAR) to a network address of a destination remote IPU or to a locally attached XPU. In one example, a PCIe {Bus, Device, Function} or process address space ID (PASID) is mapped to an RDMA queue pair (QP) in the CAM 922. The fNIC core 910 may also include an RDMA backend 924, that encapsulates the PCIe TLPs in a transport and sends the encapsulated TLP over an RDMA transport to the targeted remote IPU as determined based on the CAM 922 table lookup. Alternately, other transports, such as TCP, may be used over any type of communication media.)
(AIA ) the claimed invention, as a whole, would have been obvious, before the effective filing date, of the claimed invention, to a person having ordinary skill in the art, to which the claimed invention pertains, because: e.g., see LAL [0002] There is a trend to move the cloud service providers' infrastructure control and management to the IPU (Infrastructure Processing Unit), freeing up the host CPU for compute operations. Also, there is a trend to frontend a cluster of hardware accelerators with IPUs for control and management, with no local host CPU. In these configurations, if the IPU goes down due to some problem, the XPUs would become unavailable even if the resources are healthy and fully functional. This results in poor utilization of those resources.
Therefore, the combination of references, discloses the combination of the claimed limitations.
Claim 2. Chappell in view of LAL teaches the method of claim 1, wherein the device identifier of the second device is a bus: device: function identifier, the first device is a host device, and the second device is a storage device ([0097] fNIC core 910 can include a lookup table, such as content addressable memory (CAM) 922, that matches a key (e.g., XPU ID, bus device function, and/or address mapped to a BAR) to a network address of a destination remote IPU or to a locally attached XPU. In one example, a PCIe {Bus, Device, Function} or process address space ID (PASID) is mapped to an RDMA queue pair (QP) in the CAM 922. The fNIC core 910 may also include an RDMA backend 924, that encapsulates the PCIe TLPs in a transport and sends the encapsulated TLP over an RDMA transport to the targeted remote IPU as determined based on the CAM 922 table lookup. Alternately, other transports, such as TCP, may be used over any type of communication media. In LAL).
Compact notation has been utilized above, wherein, when a feature is, partly, attributed to a reference, other than the primary reference, the primary reference does not explicitly disclose the combination of the feature.
The motivation to combine references, is the same as, the parent claim.
Claim 4. Chappell in view of LAL teaches the method of claim 1, wherein the device identifier of the second device is a bus: device: function identifier, the first device is a storage device, and the second device is a host device ([0097] fNIC core 910 can include a lookup table, such as content addressable memory (CAM) 922, that matches a key (e.g., XPU ID, bus device function, and/or address mapped to a BAR) to a network address of a destination remote IPU or to a locally attached XPU. In one example, a PCIe {Bus, Device, Function} or process address space ID (PASID) is mapped to an RDMA queue pair (QP) in the CAM 922. The fNIC core 910 may also include an RDMA backend 924, that encapsulates the PCIe TLPs in a transport and sends the encapsulated TLP over an RDMA transport to the targeted remote IPU as determined based on the CAM 922 table lookup. Alternately, other transports, such as TCP, may be used over any type of communication media. In LAL).
Compact notation has been utilized above, wherein, when a feature is, partly, attributed to a reference, other than the primary reference, the primary reference does not explicitly disclose the combination of the feature.
The motivation to combine references, is the same as, the parent claim.
Claim 5. Chappell in view of LAL teaches the method of claim 1, further comprising: receiving a second plurality of packets from the second device, wherein the second plurality of packets is addressed to the first device using a device identifier ([0019] AS uses a path-defined routing methodology in which the source of an AS packet provides all information required by a switch (or switches) to route the AS packet to the desired destination. FIG. 3 shows an AS transaction layer packet (TLP) format 300. The AS packet includes an AS header 302 and an encapsulated packet payload 304. The AS header 302 contains the information (i.e., "the path") that is necessary to route the AS packet through the AS fabric 102, and a field that specifies the Protocol Interface (PI) of the AS payload 304. AS switch elements route AS packets using the information contained in the AS header 302 without necessarily requiring interpretation of the contents of the AS payload 304. In Chappell); mapping the device identifier of the first device to a unique device address of the first device ([0097] fNIC core 910 can include a lookup table, such as content addressable memory (CAM) 922, that matches a key (e.g., XPU ID, bus device function, and/or address mapped to a BAR) to a network address of a destination remote IPU or to a locally attached XPU. In one example, a PCIe {Bus, Device, Function} or process address space ID (PASID) is mapped to an RDMA queue pair (QP) in the CAM 922. The fNIC core 910 may also include an RDMA backend 924, that encapsulates the PCIe TLPs in a transport and sends the encapsulated TLP over an RDMA transport to the targeted remote IPU as determined based on the CAM 922 table lookup. Alternately, other transports, such as TCP, may be used over any type of communication media. In LAL); encapsulating each of the second plurality of packets received from the second device to generate a second plurality of encapsulated packets ([0021] The PI field in the AS route header 302 determines the format of the encapsulated packet payload 304. The PI field is inserted by the AS endpoint 104 that originates the AS packet and is used by the AS endpoint 104 that terminates the AS packet to correctly interpret the packet contents. The separation of routing information from the remainder of the AS packet enables the AS fabric 102 to tunnel packets of any protocol. In Chappell); and communicating each of the second plurality of encapsulated packets over the fabric network, wherein the unique device address of the first device is used to route the second plurality of encapsulated packets to the first device ([0037] For the PI-8 host switch 510, which is implemented to logically function as a PCIe switch, traffic routed through each of the downstream ports is physically transported via a single AS physical layer 210, AS data link layer 208, and AS transaction layer 206 stack. To accomplish this, the downstream tunneling processor 524 pre-pends a unique AS header that routes the encapsulated PCIe packet through the AS fabric 102 to the destination I/O switch at an AS-PCIe bridge 108a-108d. Since the PCIe packet is not physically transferred from an upstream port to a downstream port, all downstream packet validation and routing functions are performed by the downstream tunneling processor 524 for all ports in the PI-8 host switch 510. In Chappell).
Compact notation has been utilized above, wherein, when a feature is, partly, attributed to a reference, other than the primary reference, the primary reference does not explicitly disclose the combination of the feature.
The motivation to combine references, is the same as, the parent claim.
Claim 6. Chappell in view of LAL teaches the method of claim 1, wherein: the device identifier of the second device is a bus: device: function identifier; and the first and second devices are configured to use peripheral component interconnect express (PCIe) bus interface for sending and receiving information ([0097] fNIC core 910 can include a lookup table, such as content addressable memory (CAM) 922, that matches a key (e.g., XPU ID, bus device function, and/or address mapped to a BAR) to a network address of a destination remote IPU or to a locally attached XPU. In one example, a PCIe {Bus, Device, Function} or process address space ID (PASID) is mapped to an RDMA queue pair (QP) in the CAM 922. The fNIC core 910 may also include an RDMA backend 924, that encapsulates the PCIe TLPs in a transport and sends the encapsulated TLP over an RDMA transport to the targeted remote IPU as determined based on the CAM 922 table lookup. Alternately, other transports, such as TCP, may be used over any type of communication media. In LAL).
Compact notation has been utilized above, wherein, when a feature is, partly, attributed to a reference, other than the primary reference, the primary reference does not explicitly disclose the combination of the feature.
The motivation to combine references, is the same as, the parent claim.
Claim 7. Chappell in view of LAL teaches the method of claim 1, wherein each of the first plurality of encapsulated packets are communicated statelessly over the fabric network ([0037] For the PI-8 host switch 510, which is implemented to logically function as a PCIe switch, traffic routed through each of the downstream ports is physically transported via a single AS physical layer 210, AS data link layer 208, and AS transaction layer 206 stack. To accomplish this, the downstream tunneling processor 524 pre-pends a unique AS header that routes the encapsulated PCIe packet through the AS fabric 102 to the destination I/O switch at an AS-PCIe bridge 108a-108d. Since the PCIe packet is not physically transferred from an upstream port to a downstream port, all downstream packet validation and routing functions are performed by the downstream tunneling processor 524 for all ports in the PI-8 host switch 510. In Chappell).
Claim 8. Chappell in view of LAL teaches the method of claim 1, further comprising: establishing input/output (I/O) queues; and mapping the I/O queues to the first device and to the second device ([0036] A PCIe downstream queue 522 connected to the PCIe transaction layer interface 520 provides buffer space for downstream PCIe TLP packets. The PCIe downstream queue 522 adheres to standard PCI transaction ordering rules requiring posted transactions pass non-posted transactions in the case of blocked non-posted transactions. [0038] For PCIe configuration TLP's, the downstream tunneling processor 524 identifies the packet's configuration type (i.e., Type 0 or Type 1). For PCIe Type 0 configuration TLP packets, the downstream tunneling processor 524 either writes the payload of the packet or reads data to/from the register in the upstream port's PCIe configuration space 526 specified by the register number field of the PCIe configuration TLP, and returns a PCIe completion TLP to the requester via the PCIe upstream queue arbiter (532). In Chappell).
Claim 9. Chappell in view of LAL teaches the method of claim 8, wherein communicating each of the first plurality of encapsulated packets over the fabric network is initiated by writing a command to the I/O queue, and comprises sending the first plurality of encapsulated packets to the second device ([0036] PCIe TLP packets (e.g., PCIe Memory TLP packets, PCIe I/O TLP packets, PCIe Configuration TLP packets, and PCIe Message TLP packets) are received at the PI-8 host switch 510 from the source PCIe fabric 110 through the PCIe physical layer 202, PCIe data link layer 204, and the PCIe transaction layer interface 520. A PCIe downstream queue 522 connected to the PCIe transaction layer interface 520 provides buffer space for downstream PCIe TLP packets. The PCIe downstream queue 522 adheres to standard PCI transaction ordering rules requiring posted transactions pass non-posted transactions in the case of blocked non-posted transactions. In Chappell).
Claim 10. Chappell in view of LAL teaches the method of claim 1, wherein: the device identifier of the second device is a bus: device: function identifier; the first plurality of packets are peripheral component interconnect express (PCIe) packets; and each of the first plurality of packets are encapsulated as a plurality of packets of TCP/IP/Ethernet (TIE) packets ([0017] Although the example refers specifically to performing an encapsulation-tunneling-extraction process on a PCIe TLP packet, packets of other protocols, such as Ethernet, Fibre Channel, and Infiniband, can also be tunneled through the AS fabric 102. A mixture of protocols can be simultaneously tunneled through a single, universal AS fabric making it a powerful and desirable feature for next generation modular applications, such as media gateways, broadband access routers, and blade servers. [0054] The invention can be implemented in a computing system that includes a back-end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front-end component, e.g., a client computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the invention, or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), e.g., the Internet, and a wireless network. In Chappell).
Claim 11. Chappell in view of LAL teaches the method of claim 1, wherein: the device identifier of the second device is a bus: device: function identifier; the first plurality of packets are peripheral component interconnect express (PCIe) packets; and each of the first plurality of packets are encapsulated as a plurality of packets of UDP/IP/Ethernet (UIE) packets ([0017] Although the example refers specifically to performing an encapsulation-tunneling-extraction process on a PCIe TLP packet, packets of other protocols, such as Ethernet, Fibre Channel, and Infiniband, can also be tunneled through the AS fabric 102. A mixture of protocols can be simultaneously tunneled through a single, universal AS fabric making it a powerful and desirable feature for next generation modular applications, such as media gateways, broadband access routers, and blade servers. [0054] The invention can be implemented in a computing system that includes a back-end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front-end component, e.g., a client computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the invention, or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), e.g., the Internet, and a wireless network. In Chappell).
Claim 12. Chappell in view of LAL teaches the method of claim 1, wherein: the device identifier of the second device is a bus: device: function identifier: the first plurality of packets are peripheral component interconnect express (PCIe) packets; and each of the first plurality of packets are encapsulated as a plurality of packets of Fibre Channel (FC) packets ([0017] Although the example refers specifically to performing an encapsulation-tunneling-extraction process on a PCIe TLP packet, packets of other protocols, such as Ethernet, Fibre Channel, and Infiniband, can also be tunneled through the AS fabric 102. A mixture of protocols can be simultaneously tunneled through a single, universal AS fabric making it a powerful and desirable feature for next generation modular applications, such as media gateways, broadband access routers, and blade servers. [0054] The invention can be implemented in a computing system that includes a back-end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front-end component, e.g., a client computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the invention, or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), e.g., the Internet, and a wireless network. In Chappell).
Claim 13. Chappell in view of LAL teaches the method of claim 1, wherein: the device identifier of the second device is a bus: device: function identifier; the first plurality of packets are peripheral component interconnect express (PCIe) packets; and each of the first plurality of packets are encapsulated as a plurality of packets of InfiniBand packets ([0017] Although the example refers specifically to performing an encapsulation-tunneling-extraction process on a PCIe TLP packet, packets of other protocols, such as Ethernet, Fibre Channel, and Infiniband, can also be tunneled through the AS fabric 102. A mixture of protocols can be simultaneously tunneled through a single, universal AS fabric making it a powerful and desirable feature for next generation modular applications, such as media gateways, broadband access routers, and blade servers. [0054] The invention can be implemented in a computing system that includes a back-end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front-end component, e.g., a client computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the invention, or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), e.g., the Internet, and a wireless network. In Chappell).
Claim 14. Chappell in view of LAL teaches the method of claim 1, wherein each of the first plurality of packets is 2 kilobytes (KB) or less ([0043] Packet length in 64 byte increments include the entire base Required packet plus AS Header. In Chappell).
Claim 15. Chappell in view of LAL teaches the method of claim 1, wherein: the unique device address is a media access control (MAC) address; and mapping the device identifier of the second device to the unique device address comprises mapping the device identifier of the second device to the MAC address by using the device identifier as a lower three bytes of the MAC address ([0017] Although the example refers specifically to performing an encapsulation-tunneling-extraction process on a PCIe TLP packet, packets of other protocols, such as Ethernet, Fibre Channel, and Infiniband, can also be tunneled through the AS fabric 102. A mixture of protocols can be simultaneously tunneled through a single, universal AS fabric making it a powerful and desirable feature for next generation modular applications, such as media gateways, broadband access routers, and blade servers. [0054] The invention can be implemented in a computing system that includes a back-end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front-end component, e.g., a client computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the invention, or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), e.g., the Internet, and a wireless network. In Chappell) (Examiner note: Ethernet utilizes MAC addresses. There are only a finite number of solutions regarding populating a MAC address; utilizing the lower three bytes of the MAC address would have been obvious to try).
Claim 16. Chappell in view of LAL teaches the method of claim 1, wherein: the unique device address is an internet protocol (IP) address; and mapping the device identifier of the second device to the unique device address comprises mapping the device identifier of the second device to the IP address by using the device identifier as three bytes of the IP address ([0017] Although the example refers specifically to performing an encapsulation-tunneling-extraction process on a PCIe TLP packet, packets of other protocols, such as Ethernet, Fibre Channel, and Infiniband, can also be tunneled through the AS fabric 102. A mixture of protocols can be simultaneously tunneled through a single, universal AS fabric making it a powerful and desirable feature for next generation modular applications, such as media gateways, broadband access routers, and blade servers. [0054] The invention can be implemented in a computing system that includes a back-end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front-end component, e.g., a client computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the invention, or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), e.g., the Internet, and a wireless network. In Chappell) (Examiner note: Internet utilizes IP addresses. There are only a finite number of solutions regarding populating an IP address; utilizing three bytes of the IP address would have been obvious to try).
Claim 17. Chappell in view of LAL teaches the method of claim 1, wherein: the unique device address is a 24-bit Fibre Channel (FC) identifier; and mapping the device identifier of the second device to the unique device address comprises mapping the device identifier of the second device to the 24-bit FC identifier by using the device identifier as the 24-bit FC identifier ([0017] Although the example refers specifically to performing an encapsulation-tunneling-extraction process on a PCIe TLP packet, packets of other protocols, such as Ethernet, Fibre Channel, and Infiniband, can also be tunneled through the AS fabric 102. A mixture of protocols can be simultaneously tunneled through a single, universal AS fabric making it a powerful and desirable feature for next generation modular applications, such as media gateways, broadband access routers, and blade servers. [0054] The invention can be implemented in a computing system that includes a back-end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front-end component, e.g., a client computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the invention, or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), e.g., the Internet, and a wireless network. In Chappell) (Examiner note: Fibre Channel utilizes Fibre Channel (FC) identifier. There are only a finite number of solutions regarding populating a Fibre Channel (FC) identifier; utilizing the 24-bit FC identifier would have been obvious to try).
Claim 18. Chappell in view of LAL teaches the method of claim 1, wherein: the unique device address is a local identifier (LID); and mapping the device identifier of the second device to the unique device address comprises mapping the device identifier of the second device to the LID by using the device identifier as the LID address ([0005] PCIe was designed to be fully compatible with the widely used PCI local bus standard. In Chappell) (Examiner note: local bus utilizes a local identifier (LID). There are only a finite number of solutions regarding populating a local identifier (LID); utilizing the local identifier would have been obvious to try).
Claim 19.
Chappell teaches a system comprising processing circuitry configured to perform a method, the method comprising: receiving information from a first device, wherein the information is addressed to a second device of a plurality of devices using a device identifier ([0019] AS uses a path-defined routing methodology in which the source of an AS packet provides all information required by a switch (or switches) to route the AS packet to the desired destination. FIG. 3 shows an AS transaction layer packet (TLP) format 300. The AS packet includes an AS header 302 and an encapsulated packet payload 304. The AS header 302 contains the information (i.e., "the path") that is necessary to route the AS packet through the AS fabric 102, and a field that specifies the Protocol Interface (PI) of the AS payload 304. AS switch elements route AS packets using the information contained in the AS header 302 without necessarily requiring interpretation of the contents of the AS payload 304); mapping the BDF identifier of the second device to a unique device address; generating a plurality of packets from the information; encapsulating each of the plurality of packets to generate a plurality of encapsulated packets ([0021] The PI field in the AS route header 302 determines the format of the encapsulated packet payload 304. The PI field is inserted by the AS endpoint 104 that originates the AS packet and is used by the AS endpoint 104 that terminates the AS packet to correctly interpret the packet contents. The separation of routing information from the remainder of the AS packet enables the AS fabric 102 to tunnel packets of any protocol); and communicating each of the plurality of encapsulated packets over a fabric network, wherein the unique device address of the second device is used to route the plurality of encapsulated packets to the second device ([0037] For the PI-8 host switch 510, which is implemented to logically function as a PCIe switch, traffic routed through each of the downstream ports is physically transported via a single AS physical layer 210, AS data link layer 208, and AS transaction layer 206 stack. To accomplish this, the downstream tunneling processor 524 pre-pends a unique AS header that routes the encapsulated PCIe packet through the AS fabric 102 to the destination I/O switch at an AS-PCIe bridge 108a-108d. Since the PCIe packet is not physically transferred from an upstream port to a downstream port, all downstream packet validation and routing functions are performed by the downstream tunneling processor 524 for all ports in the PI-8 host switch 510).
Chappell does not explicitly teach the combination of the underlined feature, above; as interpreted in light of the disclosure, namely, device identifier bus: device: function identifier.
Chappell does not explicitly teach the combination of these features: mapping the BDF identifier of the second device to a unique device address; as interpreted in light of the disclosure, namely, device identifier bus: device: function identifier.
The missing elements are disclosed by LAL ([0097] fNIC core 910 can include a lookup table, such as content addressable memory (CAM) 922, that matches a key (e.g., XPU ID, bus device function, and/or address mapped to a BAR) to a network address of a destination remote IPU or to a locally attached XPU. In one example, a PCIe {Bus, Device, Function} or process address space ID (PASID) is mapped to an RDMA queue pair (QP) in the CAM 922. The fNIC core 910 may also include an RDMA backend 924, that encapsulates the PCIe TLPs in a transport and sends the encapsulated TLP over an RDMA transport to the targeted remote IPU as determined based on the CAM 922 table lookup. Alternately, other transports, such as TCP, may be used over any type of communication media.)
(AIA ) the claimed invention, as a whole, would have been obvious, before the effective filing date, of the claimed invention, to a person having ordinary skill in the art, to which the claimed invention pertains, because: e.g., see LAL [0002] There is a trend to move the cloud service providers' infrastructure control and management to the IPU (Infrastructure Processing Unit), freeing up the host CPU for compute operations. Also, there is a trend to frontend a cluster of hardware accelerators with IPUs for control and management, with no local host CPU. In these configurations, if the IPU goes down due to some problem, the XPUs would become unavailable even if the resources are healthy and fully functional. This results in poor utilization of those resources.
Therefore, the combination of references, discloses the combination of the claimed limitations.
Claim 20 is rejected substantially the same as Claim 19, with the addition of Chappell teaches a non-transitory computer-readable storage medium comprising computer-executable instructions that, when executed by a processor, cause the processor to perform operations ([0053] Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read-only memory or a random-access memory or both. The essential elements of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks. Information carriers suitable for embodying computer program instructions and data include all forms of non-volatile memory, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in special purpose logic circuitry).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chappell in view of LAL as applied to claim 2 above, and further in view of Norrie (US 20220398207 A1).
Claim 3. Chappell in view of LAL teaches the method of claim 2.
Chappell in view of LAL does not explicitly teach the combination of these features: wherein the second device is a just a bunch of flash (JBOF) device .
The missing elements are disclosed by Norrie ([0028] The CXL.cache protocol defines interactions between a host and a device, allowing attached CXL devices to efficiently cache host memory with very low latency using a request-response approach. The CXL.mem protocol provides the master CXL device (typically a host processor) with access to the memory of an attached subordinate CXL device (e.g. accelerator, dynamic random-access memory (DRAM), Flash) using load and store commands.)
(AIA ) the claimed invention, as a whole, would have been obvious, before the effective filing date, of the claimed invention, to a person having ordinary skill in the art, to which the claimed invention pertains, because: e.g., see [0003] The amount of data has drastically increased since the advent of artificial intelligence, machine learning, cloud computing, etc. This drastic data growth requires high-speed, high-bandwidth, low-latency solutions (e.g., servers) for seamless data processing. Peripheral component interconnect express (PCIe) is one of the technologies that are widely used in handling a large amount of data. PCIe, however, has some shortcomings such as high communication overheads, reduced performance due to small packet transfer size, lack of load balancing, etc. Computer express link (CXL) builds upon the physical and electrical interfaces of the fifth generation of PCIe (PCIe 5.0) with protocols that establish coherency, simplify the software stack, and maintain compatibility with existing standards. While CXL has evolved to improve host communications with endpoints devices, where root complex devices (e.g., hosts) and endpoint devices are two main types of PCIe devices, CXL does not currently address endpoint-to-endpoint communications.
Therefore, the combination of references, discloses the combination of the claimed limitations.
Conclusion
The prior art made of record and considered pertinent to applicant's Claims and disclosure:
MAROLIA (US 20190297015 A1)
[0024] Network interface 250 processes RDMA send/receive requests associated with various memory regions and uses translated addresses to generate the input/output (I/O) requests to primary or secondary fabrics via respective primary or secondary heads. Primary heads of network interface 250 communicate with host-to-device fabric 206-0 or 206-1. Primary heads of network interface 250 can be managed through drivers running on the general purpose processors (e.g., CPU). Additionally, multiple primary heads are used for the I/O non-uniform memory access (NUMA) performance optimizations. Primary and secondary heads of network interface 250 are assigned unique identifiers in their respective fabrics, e.g. Bus:Device:Function in case of PCI fabric.
[0041] FIG. 3B depicts an example processing of a received packet. Network interface controller 300 receives a packet 308. Received packet 308 can represent one or more packets. Packet 308 can be an Ethernet frame, although other protocols can be used such as TCP/IP. Physical and transport layer processing 310 can perform physical and transport layer processing in accordance with applicable protocols, such as but not limited to encoding or decoding data packets according to applicable physical layer specifications or standards, assembly or disassembly of data based on destination and source addresses along with network control information and error detection hash values. In this example, network interface controller 300 identifies packet 308 is part of an RDMA connection by characteristics of its packet header. Based on received packet header (e.g., tagged buffer, memory address, and length of the remote destination buffer), network interface controller 300 can determine a destination address for a portion of a received packet. On systems where IOMMU is disabled, a destination memory address could be a physical address. On systems where IOMMU is enabled, a destination memory address is an IO Virtual Address (IOVA). An IOVA is to be converted to a physical address that can be decoded to make routing decisions.
Sajeepa (US 20170171075 A1)
[0030] RoCE is a network protocol that allows RDMA transport over an Ethernet network (although also applicable to non-converged Ethernet networks) and, currently, there are two implementations of RoCE, namely RoCE v1 and RoCE v2. RoCE v1 is a non-routable protocol that operates at the link layer and require that HCA and TCA are in same Ethernet switching domain. On the other hand, RoCE v2 is a routable protocol, where RDMA work requests and responses are encapsulated in User Datagram Protocol (UDP) and Internet Protocol (IP) packets.
[0050] The VIC adapter 202, typically implemented as a firmware and capable of supporting RDMA, creates various resources in hardware that are used to handle ingress and egress RDMA data flows. The virtual network interface card (vNIC) is associated with a group of hardware queues to receive commands from a host 204, handle incoming RDMA work requests, command completions, acknowledgements and other protocol related communications. In this context, the host 204 refers to e.g. one of the compute nodes 102 described above or an application on one of the compute nodes 102. In particular, each vNIC may be associated with PCIe end point on the compute node 102, represented by PCI identifier (Bus:Device:Function)
[0065] EG packet classifier 212 is programmed with a set of entries to be matched by the outgoing RDMA commands 252, such as e.g. RDMA READ, WRITE, SEND, etc. commands, as defined e.g. in the InfiniBand™ Specification. Matching of the entries in terms of the match criteria and action taken for the EG packet classifier 212 is similar to that described above for the IG packet classifier 222, and, therefore, in the interests of brevity is not repeated. Also similar to the IP packet classifier 222, the EG packet classifier 212 is configured to provide a filter ID indicating a particular outgoing RDMA command (i.e. one of e.g. SEND, WRITE, or READ commands) for each outgoing RDMA work request received at the VIC adapter, i.e. received at the EG packet classifier 212. The filter ID provided by the EG packet classifier 212 to the EG flow table 214 represents the outgoing operation (SEND, WRITE, READ, etc.) and, in combination with the QP ID, it provides an index into the EG FT 214, i.e. an index as to which entry in the EG flow table is to be matched.
[0147] As illustrated in FIG. 11 with step 4, the EG PKT processor 216 programs the DMA context with parameters from the RDMA command packet. If the operating mode is RoCE v1, the v1 command decode rewrite rule executing on EG PKT processor 216 saves the Source MAC and destination MAC address in the DMA context. For v2 QPs, the v2 command decode rewrite rule executing on EG PKT processor 216 saves the source and destination IP addresses, in addition to the MAC addresses. The destination QP number, MSS and starting Packet Sequence Number is saved irrespective of operating mode. DMA context is also updated with the operating mode to be used.
Sajeepa (US 20170168986 A1)
Abstract: adaptively coalescing remote direct memory access (RDMA) acknowledgements is provided. The method includes determining one or more input/output (I/O) characteristics of RDMA packets of a plurality of queue pairs (QPs) on a per-QP basis, each QP identifying a respective RDMA connection between a respective first compute node and a respective second compute node. The method further includes determining an acknowledgement frequency for providing acknowledgements of the RDMA packets on a per-QP basis (i.e., a respective acknowledgement frequency is set for each QP) based on the determined one or more I/O characteristics for each QP.
[0021] Wide variety of distributed systems and applications use RDMA as primary interface for transport. For example, data center storage technologies have seen great performance improvements by using RDMA as transport protocol. Both file based and block based storage protocols have defined mappings to RDMA transport primitives. File transfer protocols such as Server Message Block (SMB) over RDMA and Network File System (NFS) over RDMA have evolved over a period of time and now offer a mature and stable alternative to file transfer over conventional Transmission Control Protocol/Internet Protocol (TCP/IP). Even block based protocols such as Internet Small Computer Systems Interface (iSCSI) and Small Computer Systems Interface (SCSI) can be transported over RDMA by making use of iSCSI Extensions for RDMA (iSER) and SCSI RDMA Protocol (SRP) respectively.
[0034] network traffic between compute nodes 102 and the network 122 (i.e. traffic between the compute nodes 102 shown in FIG. 1 and compute nodes which may be connected on the other side of the network 122) may be termed as “North-South Traffic”, while network traffic among compute nodes 102 shown in FIG. 1 may be termed as “East-West Traffic”. Note that compute nodes in communication with one another may be, and typically are, unaware of the physical location of other compute nodes, for example whether they exist in the same local network, or are in another network, connected over the network 122. Thus, compute nodes described herein are agnostic to the direction of network traffic they originate or terminate, such as whether the traffic is North-South, or East-West because the network driver 108 is typically unaware of the location of the peer node and may use the same addressing mechanism (e.g., L2 Ethernet MAC address or L3 IP address) for addressing nodes located e.g. in same microserver chassis or located in a remote node in same L2/L3 domain. Irrespective of the direction of the network traffic, the VIC adapter 120 presents a uniform interface to compute nodes for both North-South traffic and East-West traffic. Furthermore, embodiments of coalescing of acknowledgements described herein are not limited to microserver architectures.
[0041] The VIC adapter 202, typically implemented as a firmware and capable of supporting RDMA, creates various resources in hardware that are used to handle ingress and egress RDMA data flows. The virtual network interface card (vNIC) is associated with a group of hardware queues to receive commands from a host 204, handle incoming RDMA work requests, command completions, acknowledgements and other protocol related communications. In this context, the host 204 refers to e.g. one of the compute nodes 102 described above or an application on one of the compute nodes 102. In particular, each vNIC may be associated with PCIe end point on the compute node 102, represented by PCI identifier (Bus:Device:Function)
[0057] On the other hand, the EG packet classifier 212 is programmed with a set of entries to be matched by the outgoing RDMA commands 252, such as e.g. RDMA READ, WRITE, SEND, etc. commands, as defined e.g. in the InfiniBand™ Specification. Matching of the entries in terms of the match criteria and action taken for the EG packet classifier 212 is similar to that described above for the IG packet classifier 222, and, therefore, in the interests of brevity is not repeated. Also similar to the IP packet classifier 222, the EG packet classifier 212 is configured to provide a filter ID indicating a particular outgoing RDMA command (i.e. one of e.g. SEND, WRITE, or READ commands) for each outgoing RDMA work request received at the VIC adapter, i.e. received at the EG packet classifier 212. The filter ID provided by the EG packet classifier 212 to the EG flow table 214 represents the outgoing operation (SEND, WRITE, READ, etc.) and, in combination with the QP ID, it provides an index into the EG FT 214, i.e. an index as to which entry in the EG flow table is to be matched.
[0065] Each entry in the FT 500 has set of match criteria 520, which, in the example shown in FIG. 5, includes the identification of the network interface (vNIC) 506 on which the packet has arrived and an L2, e.g. MAC, address of the remote QP, as indicated in FIG. 5 with a flow match 508 column (FIG. 5 not showing the actual flow match criteria in that column). If an incoming packet matches the set of match criteria 520, then this is a valid RoCE packet for the matching opcode. In this case, the VIC adapter updates the FT 500 with a timestamp 510 and a number of bytes in the packet (i.e. byte count) 512, and increments the number of packets (i.e. packet count) 514 for that RoCE packet (i.e. for the incoming RoCE packet of certain opcode type belonging to a particular QP ID). Thus, together, the timestamp 510, the byte count 512, and the packet count 514 of each FT entry form a FT update 522 for every packet.
Colenbrander (US 20210042255 A1)
[0135] The cloud compute system 303 includes firmware to start its hardware. This firmware may have code to boot from a local storage device, over a network, or over a PCIe fabric. In the case of the cloud compute system 303 booting over a network, the firmware of the cloud compute system 303 may issue a Dynamic Host Configuration Protocol (DHCP) request to request an Internet Protocol (IP) address and information about a storage server, such as the cloud storage system 301. The information about the cloud storage system 301 can include an IP address and a file system path to locate data, but may also include PCIe information. The PCIe information can include a memory address, PCIe bus/device/function information, or other information that allows the cloud compute system 303 to locate the cloud storage system 301 on which its data is stored.
Baba (US 20250021510 A1)
Abstract: an information processing device and a method for controlling an information processing device that can increase the number of devices that can be recognized without special software. The information processing device includes a central processing unit and a host bus adapter in which input/output (I/O) devices conforming to the PCI Express standard are connected to a fabric, wherein the host bus adapter is an input/output interface of the PCI Express standard and uses a fabric communication function to communicate with an input/output unit (IOU) including at least one of the I/O devices, and the host bus adapter includes a functional part including a plurality of functions conforming to the PCI Express standard, and a mapping table in which the functions of the functional part and external I/O devices connected to the fabric are mapped in association with each other.
Norrie (US 20220398207 A1)
[0060] When using the fabQ protocol for external network connections, the cell switch 306 of switch 302 may need to interact with other external switches as part of the data path. Based on the fabQ, the cell switch 306 of switch 302 may enable a unified local/network protocol for moving data out of an interface (e.g., Ethernet or PCIe/CXL) using consistent header forwarding and classification semantics. This produces much greater protocol efficiency than existing methods. These existing methods bridge between PCIe/CXL and network interface domains using encapsulation (e.g., PCIe/CXL over Ethernet) or intermediate protocols (e.g. PCIe 5.0).
Galles (US 20150074322 A1)
[0063] The PCIe over Ethernet protocol defines connection establishment, packet encapsulation, reliable delivery, and alternate path retry in the event of failure. The protocol may guarantee in-order delivery of CRC protected PCIe transactions between a PCIe initiator and target (either upstream or downstream). To establish a connection, PCIe over Ethernet connections are set up using a management agent, such as eCPU 206 in FIG. 2 or any suitable processor in the first interconnect fabric 304, and/or the second interconnect fabric 308. The target side, i.e., the second interconnect fabric 308, performs a local enumeration of the PCIe bus, and informs the management agent of discovered cards. The management agent may assign the endpoint(s) 306a and 306b to the host 302 (e.g., in a virtual topology). Note that a PCIe card having single root I/O virtualization may assign each function (BDF number) to a single host or various hosts, assuming the physical driver can be run by a local management agent at the target interconnect fabric. The management agent informs the first interconnect fabric 304 of the device association and creates a vNIC configuration which includes a virtual PCIe slot for each remote PCIe device to be connected. The initiator host (i.e., the first interconnect fabric 304) may discover the remote PCIe slot during its next reboot during the normal PCIe enumeration process. The management agent may also inform each end of the connection of the L2 address of its peer. Once the connection is established, all PCIe transactions to/from the remote device ID for forwarded to the remote peer in the PCIe over Ethernet tunnel.
Johnson (US 20230096451 A1)
[0045] fNIC core 226 can include a lookup table, such as content addressable memory (CAM) 227, that matches a key (e.g., host ID, bus device function, and/or address mapped to a BAR) to a network address of a destination remote disaggregated IPU 230. In one example, a PCIe {Bus, Device, Function} or process address space ID (PASID) is mapped to an RDMA queue pair (QP) in the CAM 227. The fNIC core 226 may also include an RDMA backend 228, that encapsulates the PCIe TLPs in a transport and sends the encapsulated TLP over an RDMA transport to the targeted IPU 230 as determined based on the CAM 227 table lookup. Alternately, other transports, such as TCP, may be used over any type of communication media.
[0116] In Example 19, the subject matter of Examples 16-18 can include wherein the IPU is to decapsulate the TLP sent from the network interface device and provide the decapsulated TLP to an interconnect controller of the IPU. In Example 20, the subject matter of Examples 16-19 can include wherein the network interface device comprises a peripheral component interconnect express (PCIe) controller, and where the key comprises at one of a PCIe bus ID, a PCIe device ID, a PCIe function ID, or a process address space identifier (PASID).
LAL (US 20220094590 A1)
[0024] XPUs communicate with the IPU over a Peripheral Component Interconnect Express (PCIe) interface. If the IPU that is managing the XPU cluster is not locally attached via PCIe, then the foundational NIC encapsulates the PCIe transaction layer packets (TLPs) into network packets and sends them over the network to the remote IPU, where the network packets are depacketized and the PCIe TLPs are decapsulated and delivered to the IPU. Conversely, any control and management commands from the remote IPU to the XPU, such as MMIO commands, come in with PCIe headers. The fNIC will strip of the network headers and decapsulate the PCIe TLPs for programming the XPU. This underlying transport is transparent to the XPUs.
[0050] Resource manager 202 will then migrate the workload of failed IPU 204 to IPU 206. This will include providing IPU 206 with applicable information relating to the workload that was handled by IPU 204, including identity of XPUs 212, 214, 216 and other information relating to these XPUs that are stored in IPU/XPU repository 238. Resource manager 202 will further provide IPU 206 with the network address (e.g., IP and/or MAC address) for fNIC 208, and could optionally include some workload information, such as the memory location for a work descriptor ring or the like. As shown by dashed outline 238b, following the IPU migration IPU2 (206) now manages both XPU Cluster1 and XPU Cluster2.
[0063] As shown in flowchart 400, in a block 412, XPU control/management logic 404 generates one or more PCIe TLPs containing an IPU payload to be sent to a XPU 410 and encapsulated one or more PCIe TLPs in one or more network packets. The IPU payload may include control and management commands (such as command for programming a register), as well as other commands and data associated with IPUs. The PCIe TLPs may include a PCIe destination address corresponding a memory buffer accessible to XPU 410 or a destination address for the XPU 410 itself, depending on what the data will be used for. The network packet(s) is/are forwarded from XPU control/management logic 404 to IPU NIC 406, e.g., by using a DMA transfer to queue the network packet(s) in an transmit queue for an applicable port on IPU NIC 406.
[0064] Next, in a block 414 IPU NIC 406 sends the network packet(s) over the network to fNIC 408. Upon receipt of a network packet, fNIC 408 decapsulates any PCIe TLP(s) encapsulated in the network packet and forwards the PCIe TLP(s) to an applicable XPU (XPU 410 in this instance) or applicable memory buffer using the PCIe destination address in the PCIe TLP(s). Upon receipt of the one or more PCIe TLPs, the XPU processes the packet(s), as shown in a block 418.
[0073] Next, resource manager 600 will migrate the workload to the new IPU. This will entail providing applicable information such as IP address of the remote fNIC(s), XPU cluster information, etc., to the newly assigned IPU B. It will also facilitate establishing secure and authenticated communication channel between the IPU B and the remote fNIC(s).
[0084] IPU 802 further includes a network block 816, storage block 818, and security block 820. Network block 816 supports network functions, including packet processing operations. Storage block 818 is a representation of various storage functions performed by IPU 802, such as NVME or NVMEoF (NVME over Fabric). Security block 820 supports various security aspects of IPU 802, such as provisioning keys, attesting an XPU to ensure it is running authenticated firmware.
[0093] fNIC 900 also includes circuitry to facilitate communication over a network, such as but not limited to Ethernet in the illustrated example. The circuitry includes an Ethernet PHY/MAC (Media Access Channel) block 914 that performs PHY and MAC layer functions for one or more Ethernet standards. The network circuitry also includes a network stack block 916 and a PCIe encapsulation/decapsulation block 918. Network stack block 916 perform function relating to network communication involving layers above the PHY and MAC layer, such as IP layer, TCP, and security features implemented in other network layers.
[0097] fNIC core 910 can include a lookup table, such as content addressable memory (CAM) 922, that matches a key (e.g., XPU ID, bus device function, and/or address mapped to a BAR) to a network address of a destination remote IPU or to a locally attached XPU. In one example, a PCIe {Bus, Device, Function} or process address space ID (PASID) is mapped to an RDMA queue pair (QP) in the CAM 922. The fNIC core 910 may also include an RDMA backend 924, that encapsulates the PCIe TLPs in a transport and sends the encapsulated TLP over an RDMA transport to the targeted remote IPU as determined based on the CAM 922 table lookup. Alternately, other transports, such as TCP, may be used over any type of communication media.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOOMAN HOUSHMAND whose telephone number is (571)270-1817. The examiner can normally be reached Monday - Friday 8-5 PT. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AYMAN ABAZA can be reached at (571)270-0422. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/H.H/Examiner, Art Unit 2465
/AYMAN A ABAZA/Primary Examiner, Art Unit 2465
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