DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 11, 12 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2020/0279850 (Sharma et al hereinafter Sharma).
Regarding claim 1, Sharma discloses an integrated circuit structure (fig. 3B), comprising: a frontend device layer (fig. 3B, region 340, para. [0038]) comprising a read transistor (fig. 3B, read circuitry 330, para. [0042] : “… include metal oxide 332, gate oxide 334, and channel 336…” this is the same read transistor structure of the applicant in fig. 1A); a backend device layer (fig. 3B, region 307, para. [0046]) above the frontend device layer, the backend device layer comprising a write transistor (fig. 3B, write circuitry 300, para. [0035] : “include metal gate 302, gate oxide 304, channel 306, and source (S) and drain (D) regions. Metal gate 302 can include one or more of: titanium nitride (TiN), tungsten, copper, tantalum nitride (TaN), ruthenium (Ru), copper oxide, nickel, carbon, titanium, tantalum, poly-Si, poly-Ge, iridium, iridium oxide, hafnium nitride, etc. Gate oxide 304 can include one or more of: hafnium oxide, silicon oxide, aluminum oxide, silicon nitride, silicon carbide, h-BN, carbon, lanthanum oxide, any combination or multi-layers of these. Channel 306…” this is the same write transistor structure of the applicant in fig. 1A ); and an intervening interconnect layer (fig. 3B, region 326) between the backend device layer and the frontend device layer, the intervening interconnect layer comprising a storage capacitor having an electrode (fig. 3B, storage capacitor 320 and dielectric 322, para. [para. 0041] ) coupling the write transistor of the backend device layer to the read transistor of the front-end device layer.
Regarding claim 2, Sharma also teaches wherein the write transistor of the backend device layer has a bottom gate and top contact structure (fig. 7A, (para. [0058]).
Regarding claim 3, Sharma also teaches wherein the write transistor of the backend device layer has a top gate and top contact structure (fig. 7A, (para. [0058]).
Regarding claim 4, Sharma also teaches wherein the write transistor of the backend device layer has a top gate and bottom contact structure (fig. 7A, (para. [0058]).
Regarding claim 5, Sharma also teaches wherein the write transistor of the backend device layer has a top gate and alternate contact structure (fig. 7A, (para. [0058]).
Regarding claim 11, Sharma discloses a computing device (fig. 22, para. [0107]), comprising: a board (para. [0108] a mother board); and a component coupled to the board (para. [0108], [0118]), the component including an integrated circuit structure (fig. 3B), comprising: a frontend device layer (fig. 3B, region 340, para. [0038]) comprising a read transistor (fig. 3B, read circuitry 330, para. [0042] : “… include metal oxide 332, gate oxide 334, and channel 336…” this is the same read transistor structure of the applicant in fig. 1A); a backend device layer (fig. 3B, region 307, para. [0046]) above the frontend device layer (fig. 3B), the backend device layer comprising a write transistor (fig. 3B, write circuitry 300, para. [0035] : “include metal gate 302, gate oxide 304, channel 306, and source (S) and drain (D) regions. Metal gate 302 can include one or more of: titanium nitride (TiN), tungsten, copper, tantalum nitride (TaN), ruthenium (Ru), copper oxide, nickel, carbon, titanium, tantalum, poly-Si, poly-Ge, iridium, iridium oxide, hafnium nitride, etc. Gate oxide 304 can include one or more of: hafnium oxide, silicon oxide, aluminum oxide, silicon nitride, silicon carbide, h-BN, carbon, lanthanum oxide, any combination or multi-layers of these. Channel 306…” this is the same write transistor structure of the applicant in fig. 1A); and an intervening interconnect layer (fig. 3B, region 326) between the backend device layer and the frontend device layer, the intervening interconnect layer comprising a storage capacitor having an electrode (fig. 3B, storage capacitor 320 and dielectric 322, para. [para. 0041]) coupling the write transistor of the backend device layer to the read transistor of the front-end device layer.
Regarding claim 12, Sharma also teaches further comprising: a memory coupled to the board (para. [0108], [0118]).
Regarding claim 15, Sharma also shows wherein the component is selected from the group consisting of a processor (fig. 22, processor 2210), a communications chip, and a digital signal processor.
Claim(s) 6 and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/0406782 (Sharma et al hereinafter Sharma ‘6782).
Regarding claim 6, Sharma ‘6782 discloses an integrated circuit structure (fig. 5, para. [0068] : the IC device 500), comprising: a frontend device layer (fig. 5, para. [0068], the FEOL layer 420) comprising a read transistor (para. [0068], frontend transistor 504); a backend device layer (see figs. 4 and 5, BEOL layer 430), the backend device layer comprising a write transistor (para. [0083], “…one or more transistors of the backend memory of the BEOL layers 430…) above the frontend device layer; and an intervening interconnect layer (fig. 5, para. [0069]: plurality of metal layers M1-M5) between the backend device layer and the frontend device layer, the intervening interconnect layer comprising a capacitor-less via structure coupling the write transistor of the backend device layer to the read transistor of the front-end device layer (see fig. 5).
Regarding claim 16, Sharma ‘6782 discloses a computing device (fig. 11, computing device 2400), comprising: a board (para. [0106], a circuit board, e.g., a mother board); and a component coupled to the board (para. [0106]), the component including an integrated circuit structure (fig. 5, para. [0068] : the IC device 500), comprising: a frontend device layer (fig. 5, para. [0068], the FEOL layer 420) comprising a read transistor (para. [0068], frontend transistor 504); a backend device layer ((see figs. 4 and 5, BEOL layer 430) above the frontend device layer, the backend device layer comprising a write transistor (para. [0083], “…one or more transistors of the backend memory of the BEOL layers 430…); and an intervening interconnect layer (fig. 5, para. [0069]: plurality of metal layers M1-M5) between the backend device layer and the frontend device layer, the intervening interconnect layer comprising a capacitor-less via structure coupling the write transistor of the backend device layer to the read transistor of the front-end device layer (see fig. 5).
Regarding claim 17, Sharma ‘6782 also taches a memory (fig. 11, memory 2404, para. [0117], [0120]) coupled to the board.
Regarding claim 18, Sharma ‘6782 also shows a communication chip ( fig. 11, communication chip 2412 and para. [0117], [0120]) coupled to the board.
Regarding claim 19, Sharma ‘6782 also teaches wherein the component is a packaged integrated circuit die (fig. 9, para. [0011], [0019]).
Regarding claim 20, Sharma ‘6782 also teaches wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (fig. 11, para. [0119], [0120].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma and in view of US 2022/0406782 (Sharma et al hereinafter Sharma ‘6782).
Regarding claim 13, Sharma does not explicitly disclose a communication chip coupled to the board.
However, this claimed limitation notorious old and well known.
For instance, in the related field of the invention, Sharma ‘6782 teaches a communication chip coupled to the board (fig. 11, memory 2404, para. [0117], [0120]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to use the well-known communication chip by Sharma ‘6782 in Sharma in order to easily communicate with other components or devices.
Regarding claim 14, Sharma does not explicitly disclose wherein the component is a packaged integrated circuit die.
However, this claimed limitation notorious old and well known.
For instance, in the related field of the invention, Sharma ‘6782 teaches the component is a packaged integrated circuit die (fig. 9, para. [0011], [0019]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to use the well-known packaged integrated circuit die by Sharma ‘6782 in Sharma for easily assembly.
Claim(s) 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma ‘6782 and in view of US 2020/0279850 (Sharma et al hereinafter Sharma).
Regarding claims 7-10, Sharma ‘6782 does not explicitly disclose wherein the write transistor of the backend device layer has a bottom gate and top contact structure, top gate and top contact structure, a top gate and bottom contact structure and a top gate and alternate contact structure.
However, these claimed limitations are notorious old and well known.
For instance, in the related field of the invention, Sharma teaches these claimed limitations (fig. 7A, (para. [0058])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to use the teaching by Sharma in Sharma ‘6782 for a particular application.
Conclusion
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/TUAN D NGUYEN/Primary Examiner, Art Unit 2699
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