DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment to Claim 1 entered. Applicant has not identified where the original disclosure supports the added limitations. Applicant is reminded that support for amendments should be specifically pointed out. See MPEP 714.02, 2163.06
The reply does not address the objection to the drawings under 37 CFR 1.83(a) and no replacement sheets were filed. A reply must address every ground of objection and rejection (37 CFR 1.111(b). The objection is maintained.
Request for Rejoinder
Applicant’s request for rejoinder is acknowledged. No elected Claim is presently allowable, claims 6-8 and 10-20 remain withdrawn.
Specification
The disclosure is objected to because of the following informalities:
[0086] refers to “phosphorous”. The reference should read “phosphorus” as it refers to a noun that names the chemical element with symbol P.
Appropriate correction is required.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims.
Structural limitations of Claims 1 and 2 (transistor channels, first and second sources and drains, connections between structural elements) in Fig. 1A and 1B.
the channels of the first and second transistors (Claims 1, 3-5)
the first and second sources and drains as distinguishable elements (Claims 1-2)
the coupling of the second source with the first gate and of the second drain with the first source, including direct coupling of Claim 2.
Fig. 1B places reference character 160 only withing the region of GaN layer 112. No connection extending through SiC layer 132 to transistors 134, as described in [0039] is shown.
Further, schematic couplings of Fig. 3A, 4 and 5 do not cure this for the following reasons. They belong to non-elected species and Fig. 5 depicts stack in which the SiC layer lies between the base wafer and the GaN layer, not in the claimed order.
Therefore, the features must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 4 is objected to because of the following informalities: “phosphorous” should read “phosphorus”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bhalla et al. (US 11,211,373 B) in view of Lan et al. (US 2020/0381398 A1).
Regarding Claim 1, Bhalla (Fig. 1, 4, 6) discloses an apparatus comprising:
a first transistor (SiC JFET 120), wherein
a channel of the first transistor (120) includes silicon (Si) and carbon (C) (SiC) (Claim 13, 14), and wherein
the first transistor includes a first source (topside JFET source pad 122), a first drain (backside drain connection 126), and a first gate (gate pad 124) (Fig. 1);
a second transistor (low voltage MOSFET 110) coupled to and stacked over the first transistor (110 bonded atop 120 by bonding material 130) (Fig. 1) wherein
the second transistor (low voltage MOSFET 110) includes a second source (source pad 112), a second drain (backside drain connection 116), and a second gate (topside MOSFET gate pad 114) (Fig. 1A); and wherein
the second source (112) is electrically coupled with the first gate (124) (multilevel connector 442B whose lower portion 442C is bonded to the JFET gate pad Fig. 41A; connector 180, 1B), and wherein
the second drain (116) is electrically coupled with the first source (112) (116 bonded to 122 by conductive bonding material 130) (Fig. 1A, 4A).
Bhall further discloses a top side member (top DBC substrate 650) bonded over the second transistor 110) through conductors (442A, B; 632A, 632B) and its copled to the first transistor 120 through conductor portion 442C. The second transistor (10) therefore lies between top side member (650) and the first transistor (120) See Fig. 6) Bhalla also disloses the the top chips (110) may be stacked on the bottom chips (120) while the bottom chips remain in the wafer form.
Bhalla does not explicitly disclose a carrier wafer; a first transistor coupled to the carrier wafer, a second transistor coupled to the carrier wafer and stacked over the first transistor such that the second transistor is vertically intervening between the carrier wafer and the first transistor.
Lan (Fig. 4A, 5B) discloses a carrier wafer (second carrier 410, a Si carrier or GaN wafer) [0063-0065]; a first transistor (214) coupled (217, 227 and 210, 220) to the carrier wafer (410), a second transistor (224) coupled (420, 221) to the carrier wafer (410) and stacked over the first transistor (214) such that the second transistor (224) is vertically intervening between the carrier wafer (410) and the first transistor. (214) (Fig. 5B, [0066]). Lan further discloses that the first and second transistors are electrically coupled through bonded interconnect (218, 228) while carrier remains attached [00344, 0038, 0067-0068].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the optoelectronic semiconductor device in Bhalla in view of Lan such that a carrier wafer; a first transistor coupled to the carrier wafer, a second transistor coupled to the carrier wafer and stacked over the first transistor such that the second transistor is vertically intervening between the carrier wafer and the first transistor in order to heterogeneous transistor stak at the wafer level, which shortens the interconnections between the stacked devices, reduces the size of the stack and permits wafer level testing and sorting [Lan 0021, 0056, 0061]. Bhalla himself recognizes the difficulty of handling and testing thinned chip stacks [col 3, lines 15-23].
Regarding Claim 2, Bhalla in view of Lan discloses the apparatus of claim 1, wherein
the second source is directly electrically coupled with the first gate, or wherein
the second drain (116) is directly electrically coupled with the first source (122). (Bhalla Claim 1 Fig. 1, 4)
Regarding Claim 3, Bhalla in view of Lan discloses the apparatus of claim 1, wherein
a material of a channel of the second transistor (110; silicon) is different than a material of the channel of the first transistor (120, SiC) (Bhalla, Claim 13, 14).
Regarding Claim 4, Bhalla in view of Lan discloses the apparatus of claim 1, wherein
a material of a channel of the second transistor (110) includes a selected one or more of: Si, (top chip is a silicon semiconductor device, Claim 14, Bhalla) gallium (Ga), germanium (Ge), nitrogen (N), oxygen (O), carbon (C), phosphorous (P) or arsenic (As).
Regarding Claim 5, Bhalla in view of Lan discloses the apparatus of claim 4.
Bhalla in view of Lan as previously combined does not explicitly disclose the material of the channel of the second transistor includes GaN.
Lan discloses the second transistor (224) in the carrier side tier (220) formed as HEMT of GaN [0005].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the optoelectronic semiconductor device in Bhalla in view of Lan such that the material of the channel of the second transistor includes GaN in order to obtain III-V device performance tha Lan attributes to the carrier side tier, including improved Ron-Coff fo switching devices [Lan 0054]. Bhalla expressly contemplates chip stacks that combine group IV and group II-V semiconductors [col 3 lines 65-67, col 4, lines 1-10].
Regarding Claim 9, Bhalla in view of Lan discloses the apparatus of claim 1, wherein
the first transistor or the second transistor are a selected one of: a high electron mobility transistor (HEMT), a junction gate field effect transistor (JFET) (120), metal oxide semiconductor high electron mobility transistor (MOSHEMT), or metal oxide semiconductor field-effect transistor (MOSFET) (110) (Bhalla Claim 13).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRIY YEMELYANOV whose telephone number is (571)270-7920. The examiner can normally be reached M-F 9a.m.-6p.m.
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/DMITRIY YEMELYANOV/Examiner, Art Unit 2891
