Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). The specification at page 6 expressly describes FIG. 1 as "a conventional 5-qubit QFT circuit diagram" and the detailed description at page 15 identifies FIG. 1 as "a standard a 5-qubit QFT circuit" (which also appears to contain a typo of the extraneous “a”). Because FIG. 1 depicts only the prior art circuit, it must carry a "Prior Art" legend. Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled "Replacement Sheet" in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: (1) 'Exression3' at spec page 9 is a misspelling and should read 'Expression 3'; (2) 'the the number' at spec page 1 is a doubled article and should read 'the number'; (3) the text at spec page 19 (NISQ Implementation section) references 'Fig. 3a' and 'Fig. 3b' (and 'Fig. 3c') but the application contains no such figures — the three circuit identity figures in the application are FIG. 6, FIG. 7, and FIG. 8, respectively, and the references should be corrected accordingly; (4) 'the those required gates' at spec page 16 is a double-article error and should read 'those required gates' or 'the required gates'; (5) 'obtaing' at spec page 18 is a misspelling and should read 'obtaining'; (6) 'Amazon Barket' at spec page 1 (Background section) is a misspelling of 'Amazon Braket,' which is spelled correctly at spec page 19 (NISQ Implementation section) — the specification should be consistent; and (7) several equations, variables and associated characters through the specification are difficult to discern.
Appropriate correction is required.
Claim Rejections - 35 USC § 112(a) or 35 USC § 112, first paragraph
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Written Description
Claims 2-4 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claim 2 recites a twelve-step "form in which the Rz gate is implemented" for an n-qubit (n ≥ 5) circuit, including, in the first step, “applying an Rz(3π/2k+1) gate to qk qubits (k is a natural number greater than or equal to 5 and less than or equal to n-1)”, and, in the seventh and tenth steps, Rz gates applied at index l (l greater than or equal to 5 and less than or equal to n-1). The specification does not reasonably convey possession of this generic algorithm. The only worked embodiment (specification at page 11, FIG. 4) applies the corresponding Rz(3π/2k+1) gates to qubits q2, q3, and q4 — i.e., the angle formula evaluates to 3π/8, 3π/16, and 3π/32 for k = 2, 3, 4 — so the disclosed circuit indexes these gates beginning at k = 2, not k ≥ 5. For the only fully described case (n = 5, where n-1 = 4), the claimed range 5 ≤ k ≤ 4 is empty, and the claimed steps therefore omit the q2–q4 rotation gates the disclosed circuit requires. The generic counterpart passage in the specification (page 1-2, Summary of the Invention) repeats the identical k ≥ 5 / l ≥ 5 limitation and thus provides no corrective support. The specification accordingly fails to convey to one of ordinary skill in the art that the inventors had possession of the n-qubit algorithm as claimed. See MPEP § 2163.
Claim 3 depends from claim 2 and retains its n-qubit scope (n ≥ 5), yet recites a sixteen-step sequence hard-coded to a five-qubit circuit: it references exactly three ancilla qubits ("first," "second," and "third ancilla qubit") operating only on qubits q2, q3, and q4. This sequence is supported only for n = 5 (specification at pages 12-14, FIG. 5 / FIG. 9). The specification does not describe how the number of ancilla qubits or the Rz gate-layer-reduction sequence generalizes to any n greater than 5, and discloses no representative species other than the five-qubit, three-ancilla embodiment. A genus directed to all n ≥ 5 is therefore not supported by a single disclosed species. The specification fails to convey possession of the claimed subject matter across its scope. See MPEP § 2163.
Claim 4 is captioned as "An n-qubits Quantum Fourier Transform circuit ... (n is a natural number greater than or equal to 5)" but recites a thirty-step body fixed to five qubits: it operates on q0–q4, uses exactly three ancilla qubits, and concludes with the five-qubit swap network "swapping the q1 qubit and the q3 qubit" (twenty-ninth step) and "swapping q0 and q4 qubits" (thirtieth step). This body is supported only for n = 5 (specification at pages 13–16, FIG. 9). The specification does not describe how the ancilla count, the per-qubit Rz angles, or the swap network generalize to any n greater than 5. In addition, the first step recites applying an Rz(3π/2k+1) gate to qk qubits (k ... greater than or equal to 5 ... less than or equal to n-1), which for n = 5 is an empty range and omits the q2–q4 rotations the disclosed first step actually applies (specification at page 14: Rz(3π/8) to q2, Rz(3π/16) to q3, Rz(3π/32) to q4). The specification therefore does not convey possession of an n-qubit (n ≥ 5) circuit as claimed. See MPEP § 2163.
Enablement
Claims 2-4 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
The factors to be considered in determining whether a disclosure meets the enablement requirement of 35 U.S.C. 112(a) have been described in In re Wands, 858 F.2d 731, 737 (Fed. Cir. 1988). See MPEP § 2164.01. These factors are applied to claims 2–4, which share the common defect that the specification provides a complete, gate-level construction only for a single five-qubit QFT circuit while the claims reach all n ≥ 5.
(1) Breadth of the claims: Claims 2–4 reach every n-qubit QFT circuit/method for n ≥ 5. The breadth of the claims is large relative to the disclosure.
(2) Nature of the invention: The invention is a fault-tolerant quantum-circuit construction in which Rz gate layers are built using quantum addition and reduced using ancilla qubits and QKM-derived circuit identities (specification pages 9–16). The construction details (number and indexing of Rz layers, gate angles, ancilla allocation, and swap network) depend on n.
(3) State of the prior art: Quantum addition and approximate QFT decomposition are known (specification pages 8–9), but the specific n-qubit construction recited — the asserted reduction of T-count and T-depth by half — is presented as the inventors' new contribution and is illustrated only for n = 5.
(4) Level of one of ordinary skill: A person of ordinary skill is highly educated (e.g., an advanced degree in physics or computer science with expertise in quantum-circuit synthesis). Even so, the specification's guidance for the full claimed scope is insufficient and, in part, internally inconsistent.
(5) Level of predictability in the art: At the gate-construction level the art is of limited predictability for this invention: the number of Rz layers, the rotation angles, the number of ancilla qubits, and the swap topology vary with n in ways the specification illustrates only for n = 5.
(6) Amount of direction provided by the inventor: The specification provides detailed, step-by-step direction only for the five-qubit circuit (FIGS. 4–9). The generic n-qubit recitations (specification pages 1–2) carry the same k ≥ 5 / l ≥ 5 limitation that, applied literally, omits the q2–q4 rotation gates present in the worked example (specification page 11); thus the generic direction does not even reproduce the disclosed circuit, and no direction is provided for ancilla scaling or the swap network at n > 5.
(7) Existence of working examples: A single working example is provided (n = 5; FIGS. 1–9 and Table 2 QPE demonstration). No example is provided for any n > 5, and the sole example is inconsistent with the generic index ranges recited in claims 2 and 4.
(8) Quantity of experimentation needed: To make and use the full claimed scope, a person of ordinary skill would first have to recognize and correct the index-range defect in the generic recitations, then independently derive, for each n > 5, the complete Rz-layer structure, the required number of ancilla qubits, the per-qubit rotation angles, and the swap network by applying the QKM-derived identities from scratch. This amounts to undue experimentation.
Considering the above factors, the specification does not enable a person of ordinary skill in the art to make and use the full scope of the claimed invention without undue experimentation.
Claim Rejections - 35 USC § 112(b) or 35 USC § 112, second paragraph
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites "moving Hadamard gate (H-gate) of an even-numbered qubits" in the first limitation. There is insufficient antecedent basis for "Hadamard gate" as introduced without an indefinite article, and the phrase "an even-numbered qubits" uses a singular article with a plural noun, creating ambiguity as to whether one or multiple qubits are intended. A PHOSITA cannot determine with reasonable certainty the scope of the first limitation. For purposes of examination, interpreted under BRI as referring to all H-gates applied to even-indexed qubits (q0, q2, q4, …) in the n-qubit QFT.
Claim 1 recites "to the earliest stage where there is no quantum entanglement with other qubits." There is insufficient antecedent basis for "the earliest stage" in claim 1. No prior recitation of "a stage" appears in the claim. For purposes of examination, interpreted under BRI as the leftmost gate layer in the circuit at which the target qubit is not entangled.
Claim 1 recites "decomposing quantum circuit into a form in which an Rz gate is implemented, using quantum addition." There is insufficient antecedent basis for "quantum circuit" in this limitation; no prior recitation of "a quantum circuit" appears in the claim, making the referent of "quantum circuit" ambiguous. For purposes of examination, interpreted under BRI as referring to the n-qubit QFT circuit following the H-gate movement step.
Claim 2, second step, recites "applying a CNOT gate to the q0 gate, based on the q1 qubit after the first step" and the fourth step recites "applying a CNOT gate to the q0 gate, based on the q1 qubit after the third step." There is insufficient antecedent basis for "the q0 gate" in steps 2 and 4. The first step introduces q0 as "the q0 qubit" — not "a q0 gate." A qubit is not a gate; the descriptor "gate" applied to q0 is technically incorrect and lacks a prior introduction. For purposes of examination, "the q0 gate" is interpreted under BRI as the qubit designated q0.
Claim 2, first step, recites "applying an Rz(3π/2k+1) gate to qk qubits (k is a natural number greater than or equal to 5 and less than or equal to n-1)." Claim 1 requires n ≥ 5. For n = 5, the constraint k ≥ 5 AND k ≤ n−1 = 4 is mathematically impossible. The first step cannot be performed for the minimum permissible n, rendering the scope of Claim 2 indeterminate. Moreover, the specification’s n = 5 working example (spec pages 10–12, FIG. 4) uses k = 2, 3, 4 — none of which satisfy k ≥ 5. The k ≥ 5 constraint is thus internally contradictory and inconsistent with the specification. For purposes of examination, interpreted as written: k ≥ 5 AND k ≤ n−1, limiting Claim 2 to n ≥ 6 circuits. The correct lower bound supported by the specification is k ≥ 2.
Claims 2 and 3 are additionally rejected under 35 U.S.C. 112(b) for failing to set forth the subject matter which the inventors regard as the invention. The specification (spec page 11) states: "As a configuration of the quantum circuit, a 5-qubit QFT circuit will be described as an example," and describes the n = 5 implementation in detail across FIGS. 4 and 5 (spec pages 11–15). The k ≥ 5 constraint in Claims 2 and 3 renders those claims inoperative for n = 5, the very embodiment the inventors identified as the primary example of the invention. Claims 2 and 3 therefore fail to claim what the inventors regard as the invention with respect to the five-qubit QFT. Claims 2 and 3 are interpreted as limited to n ≥ 6. The n = 5 five-qubit embodiment (FIG. 4, FIG. 5; spec pages 11–15) falls outside the scope of these claims as written.
Claim 3 independently recites in the first step: "applying an Rz(3π/2k+1) gate to qk qubits (k is a natural number greater than or equal to 5 and less than or equal to n-1)." The same impossibility identified for Claim 2’s first step applies here.
Claim 3 further recites in the sixteenth step: "applying Rz(7π/16) gate to the q1 qubit," omitting the required indefinite article "an" before "Rz(7π/16) gate." The gate is introduced for the first time in this step without proper article introduction. For purposes of examination, the k constraint limits Claim 3 to n ≥ 6; the sixteenth step is interpreted as "applying an Rz(7π/16) gate to the q1 qubit."
Claim 4 is an independent claim. The first step recites "applying an Rz(3π/2k+1) gate to qk qubits (k is a natural number greater than or equal to 5 and less than or equal to n-1)." Claim 4’s preamble permits n ≥ 5. For n = 5, k ≥ 5 AND k ≤ 4 is impossible. The specification’s primary circuit embodiment (FIG. 9, spec pages 13–15) is explicitly described as a 5-qubit QFT, using k = 2, 3, 4 in the first step — inconsistent with k ≥ 5. For purposes of examination, the constraint limits Claim 4 to n ≥ 6. The n = 5 FIG. 9 embodiment falls outside Claim 4 as written.
Claim 4, second and fourth steps, recite "applying a CNOT gate to the q0 gate." The first step introduces q0 as "q0 qubit." No "q0 gate" was introduced. The same antecedent-basis and technical-inconsistency deficiency identified for Claim 2 applies here. For purposes of examination, "the q0 gate" is interpreted as the qubit q0. See spec pages 14–15.
Claim 4 is additionally rejected under 35 U.S.C. 112(b) for failing to set forth the subject matter which the inventors regard as the invention. The specification (spec pages 13–15) states: "That is, the 5-qubit QFT circuit shown in FIG. 9 is configured to perform each step below," identifying FIG. 9 as "a decomposed quantum Fourier transform (QFT) circuit according to an embodiment of the present invention" (spec page 16). The k ≥ 5 constraint in Claim 4’s first step renders the claim inoperative for the n = 5 five-qubit QFT circuit of FIG. 9 that the inventors regarded as the primary circuit embodiment of the invention. Claim 4 is interpreted as limited to n ≥ 6 QFT circuits. The five-qubit QFT circuit of FIG. 9 falls outside the scope of Claim 4 as written.
Appropriate correction is required
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Approximate Quantum Fourier Transform with O(n log(n)) T gates to Nam et al. (hereinafter Nam) in view of Semiclassical Fourier Transform for Quantum Computation to Griffiths et al. (hereinafter Griffiths).
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Approximate Quantum Fourier Transform with O(n log(n)) T gates to Nam et al. (hereinafter Nam) in view of Semiclassical Fourier Transform for Quantum Computation to Griffiths et al. (hereinafter Griffiths).
Per claim 1, Nam discloses A method of forming a Quantum Fourier Transform (QFT) circuit (Nam: Abstract…Nam discloses a method of constructing an n-qubit (approximate) Quantum Fourier Transform circuit from elementary gates, which constitutes a method of forming a QFT circuit, "we show how to obtain approximate QFT with the T-count of O(n log(n))"), comprising:
moving Hadamard gate (H-gate) of an even-numbered qubits to the earliest stage where there is no quantum entanglement with other qubits, in a standard n (n is a natural number greater than or equal to 5) qubit QFT (Nam: Section II (Main Result) and Fig. 1…Nam affirmatively restructures the standard n-qubit QFT and relocates the single-qubit Hadamard (H) gates so that they separate the n−1 sets of entangling controlled-Za rotations, placing each H gate at a stage between (and therefore free of) the entangling operations, as expressly illustrated for n = 6 in Fig. 1. Note: under the specification's own definition (spec at page 11, "moved to the left as far as possible…"), positioning the H gate so as to precede the entangling rotation sets is the claimed "earliest stage where there is no quantum entanglement," and the alternating placement shown in Fig. 1 of Nam corresponds to the H gates of the even-numbered qubits, "We unite the individual controlled rotations into n-1 sets separated by the H gates, such as illustrated in Fig. 1");
decomposing quantum circuit into a form in which an Rz gate is implemented, using quantum addition (Nam: Section II…Nam decomposes the QFT's controlled z-axis phase rotations (Za / Rz-type rotation gates) into a phase-gradient operation that is carried out by a quantum adder operating in the Fourier basis, so that the rotation/Rz layers are implemented by quantum addition, "Such a transformation can be implemented by a b-bit adder at the cost of 4b + O(1) T gates"); and
reducing a number of Rz gate layers using ancilla qubits (Nam: Fig. 2…Nam introduces an ancilla register holding a reusable (b+1)-qubit phase-gradient state |ψb+1> that is shared across, and thereby collapses, all of the rotation (Rz) layers, reducing the number of separately synthesized Rz gate layers by means of ancilla qubits, "Ancilla-aided, measurement/feedforward-based fault-tolerant controlled-za gate"; Section II…"The quantum state |ψb+1> can be reused to induce phase gradient transformations in all n−1 sets of controlled-za rotations").
Nam restructures the standard QFT and relocates its Hadamard gates relative to the entangling rotation sets, but does not use the express phrase "moving the Hadamard gate … to the earliest stage where there is no quantum entanglement." Griffiths, however, does teach relocating the single-qubit (Hadamard-type) gates of the QFT relative to the entangling two-qubit gates by commutation, i.e., moving Hadamard gate (H-gate) of an even-numbered qubits to the earliest stage where there is no quantum entanglement with other qubits, in a standard n (n is a natural number greater than or equal to 5) qubit QFT (Griffiths: Abstract…Griffiths shows that the entangling two-bit gates of the Fourier transform can be reorganized into one-bit gates, and expressly establishes that the operation preceding a measured bit commutes with the entangling two-bit gates so that it can be "pushed" earlier in the circuit to the point (point B in Fig. 1) at which the qubit is not yet entangled — supplying the express ‘moving to the earliest non-entangled stage’ act that Nam performs structurally, "the two-bit gates in the Fourier transform can all be replaced by a smaller number of one-bit gates"; p. 4…"in the situation shown in Fig. 1, P commutes with the unitary transformations corresponding to the three 2-bit gates which precede the measurement of c0 and therefore one can “push” the corresponding property backwards in time to the point B in Fig. 1").
Nam and Griffiths are analogous art because they are both within the same field of endeavor, namely the construction and optimization of Quantum Fourier Transform circuits from elementary quantum gates, and both address the same problem of reducing the gate cost/depth of the QFT circuit. Nam expressly relocates the Hadamard gates so that they separate the entangling controlled-rotation sets (Nam: p.2), and Griffiths teaches that such single-qubit gates commute past the entangling two-qubit gates and may therefore be moved to an earlier, non-entangled stage (Griffiths: p.4).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to relocate the Hadamard gates in Nam's QFT to the earliest stage at which the corresponding qubit is not entangled, as taught by Griffiths, because doing so is a known and predictable rearrangement (single-qubit gates provably commute past the entangling two-qubit gates) that exposes the controlled-rotation layers for the adder-based, ancilla-assisted implementation that Nam already employs, thereby reducing circuit depth. Such a combination of prior-art elements according to known methods to yield predictable results is obvious under KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
The suggestion/motivation for doing so would have been the express teaching in Nam that the QFT is reorganized so that the Hadamard gates separate the n−1 entangling rotation sets to enable the adder-based phase-gradient implementation (Nam: pp. 2-3), taken together with Griffiths' demonstration that the single-qubit gates commute past the entangling two-qubit gates and can be relocated earlier (Griffiths: p.4) — a PHOSITA seeking to minimize QFT circuit depth would have been led to move the Hadamard gates to the earliest non-entangled stage.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Patents and/or related publications are cited in the Notice of References Cited (Form PTO-892) attached to this action to further show the state of the art with respect to Quantum Fourier Transform circuit formation.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALAN CHEN whose telephone number is (571)272-4143. The examiner can normally be reached M-F 10-7.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kamran Afshar can be reached at (571) 272-7796. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALAN CHEN/Primary Examiner, Art Unit 2125
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