Prosecution Insights
Last updated: April 20, 2026
Application No. 18/090,253

ELECTRO-OPTICAL CIRCUITS WITH LOW-VOLTAGE SWITCHABLE PHOTONIC INTERFACE

Non-Final OA §103
Filed
Dec 28, 2022
Examiner
PAK, SUNG H
Art Unit
2874
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
2y 2m
To Grant
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
1053 granted / 1202 resolved
+19.6% vs TC avg
Moderate +12% lift
Without
With
+11.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
23 currently pending
Career history
1225
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
50.2%
+10.2% vs TC avg
§102
37.9%
-2.1% vs TC avg
§112
2.2%
-37.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1202 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement Information disclosure statement filed 12/28/2022 has been considered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1-5, 7-11, 13-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. US 2016/0359568 A1 to De Dobbelaere et al. (hereinafter “De Dobbelaere”) in view of US Patent No. 6,845,184 B1 to Yoshimura et al. (hereinafter “Yoshimura”). Regarding claim 1, De Dobbelaere discloses an apparatus, comprising: a photonic integrated circuit (203 in Fig. 2A; paragraph [0046]), comprising a first surface (i.e. bottom of 203); an electrical IC (201 in Fig. 2A; paragraph [0028]), comprising a second surface (i.e. top of 201), wherein a first portion of the second surface is electrically coupled to the first surface (i.e. portion of top surface of 201 that is coupled with the bottom surface of 203); and a waveguide device (211 in Fig. 2A; paragraph [0036]- element 211 contains optical fiber) laterally adjacent, and optically coupled to, the photonic IC (Fig. 2A), wherein the waveguide device is over a second portion of the second surface (i.e. portion of top surface of 201 that is under 211 as shown in Fig. 2A). However, De Dobbelaere does not explicitly disclose that the waveguide device is a switchable waveguide device comprising a first metallization structure and a second metallization structure and a nonlinear optical material therebetween and at a same level as the first and second metallization structures in the manner claimed in the present application. On the other hand, such a switchable waveguide is known in the art. For example, Yoshimura discloses an optoelectronic system comprising a switchable waveguide (e.g. 626 in Fig. 17) disposed between a first and second metallization structures (24 in Fig. 17), wherein the waveguide comprises a nonlinear optical material (col. 23, ll. 50-51). One of ordinary skill in the art would readily recognize such a switchable optical waveguide as advantageous and desirable since it would allow for high speed, large capacity optical communications without the bottleneck created by external optical routing elements. It also allows for reliable splitting and routing of optical data which enhances the capabilities optical communications devices. Therefore, it would have been obvious to a person of ordinary skill in the art before the filing date of the present application to modify the device of De Dobbelaere to have a switchable waveguide device comprising a first metallization structure and a second metallization structure and a nonlinear optical material therebetween and at a same level as the first and second metallization structures in the manner claimed in the present application. Regarding claim 2, De Dobbelaere discloses the first portion of the second surface being directly bonded to the first surface (Fig. 2A). Regarding claim 3, De Dobbelaere does not explicitly disclose the use of a glass substrate laterally adjacent the photonic IC and over the electrical IC in the manner claimed in the present application. On the other hand, the use of a glass substrate covering a photonic IC and an electrical IC is well known and common in the art. Such a glass substrate is advantageously used in the art because it allows for effective protection of optical coupling elements while maintaining low insertion loss. Therefore, it would have been obvious to a person of ordinary skill in the art before the filling date of the present application to modify the device of De Dobbelaere to have a glass substrate laterally adjacent the photonic IC and over the electrical IC in the manner claimed in the present application. Regarding claim 4, since De Dobbelaere in view of Yoshimura renders the use of the nonlinear optical material obvious as already discussed above regarding claim 1, De Dobbelaere in view of Yoshimura also renders the claimed limitations of claim 4 obvious when modified to include a glass substrate in the manner discussed in reference to claim 3. Regarding claim 5, De Dobbelaere discloses the photonic IC directly contacting the optical waveguide (Fig. 2A). As such, De Dobbelaere in view of Yoshimura also renders the claimed limitations of claim 5 obvious when modified to include nonlinear optical material in the manner discussed regarding claim 1. Regarding claim 7, Yoshimura discloses the use of a first and second metallization structures in the manner discussed above in reference to claim 1. Although De Dobbelaere does not explicitly disclose the use of a third and fourth metallization structures being formed as a part of the electrical IC, such metallization structures which coupled with metallization structures of the photonic IC would have been necessarily present in the invention of De Dobbelaere. Without such metallization structures, active photonic components of De Dobbelaere would not function as disclosed. Therefore, the claimed limitations of claim 7 would be also rendered obvious when the invention is De Dobbelaere in view of Yoshimura to include the switcheable waveguide and the first and second metallization structures in the manner discussed above in reference to claim 1. Regarding claim 8, De Dobbelaere discloses a system, comprising: an electrical integrated circuit (e.g. 201 in Fig. 2A), coupled to a substrate (paragraph [0029]); a photonic IC (203 in Fig. 2A), wherein the photonic IC is electrically coupled to a first portion of the electrical IC (paragraph [0029]); and a waveguide device in, or coupled to, the photonic IC (211 in Fig. 2A; paragraph [0036]- element 211 contains optical fiber), wherein the waveguide device is over a second portion of the electrical IC (i.e. portion of top surface of 201 that is under 211 as shown in Fig. 2A) However, De Dobbelaere does not explicitly disclose that the waveguide device is a switchable waveguide device comprising a first metallization structure and a second metallization structure and a nonlinear optical material therebetween and at a same level as the first and second metallization structures in the manner claimed in the present application. On the other hand, such a switchable waveguide is known in the art. For example, Yoshimura discloses an optoelectronic system comprising a switchable waveguide (e.g. 626 in Fig. 17) disposed between a first and second metallization structures (24 in Fig. 17), wherein the waveguide comprises a nonlinear optical material (col. 23, ll. 50-51). One of ordinary skill in the art would readily recognize such a switchable optical waveguide as advantageous and desirable since it would allow for high speed, large capacity optical communications without the bottleneck created by external optical routing elements. It also allows for reliable splitting and routing of optical data which enhances the capabilities optical communications devices. Therefore, it would have been obvious to a person of ordinary skill in the art before the filing date of the present application to modify the device of De Dobbelaere to have a switchable waveguide device comprising a first metallization structure and a second metallization structure and a nonlinear optical material therebetween and at a same level as the first and second metallization structures in the manner claimed in the present application. Regarding claim 9, De Dobbelaere discloses the first portion of the second surface being directly bonded to the first surface (Fig. 2A). Regarding claim 10, De Dobbelaere does not explicitly disclose the use of a glass substrate laterally adjacent the photonic IC and over the electrical IC in the manner claimed in the present application. On the other hand, the use of a glass substrate covering a photonic IC and an electrical IC is well known and common in the art. Such a glass substrate is advantageously used in the art because it allows for effective protection of optical coupling elements while maintaining low insertion loss. Therefore, it would have been obvious to a person of ordinary skill in the art before the filling date of the present application to modify the device of De Dobbelaere to have a glass substrate laterally adjacent the photonic IC and over the electrical IC in the manner claimed in the present application. Regarding claim 11, since De Dobbelaere in view of Yoshimura renders the use of the nonlinear optical material obvious as already discussed above regarding claim 8, De Dobbelaere in view of Yoshimura also renders the claimed limitations of claim 11 obvious when modified to include a glass substrate in the manner discussed in reference to claim 10. Regarding claim 13, De Dobbelaere in view of Yoshimura renders the claimed limitations of claim 11 obvious as discussed above. However, it does not explicitly disclose the use of a module dielectric encircling the electrical IC as claimed in the present application. On the other hand, the use of a protective module dielectric is well known and common in the art. Such module dielectric is advantageously used in the art to provide a robust protective layer over fragile electrical and optical components of optical communications devices. Therefore, it would have been obvious to a person of ordinary skill in the art before the filling date of the present application to modify the invention of De Dobbelaere to have a module dielectric encircling the electrical IC in the manner claimed in the present application. Regarding claim 14, the use of a glass substrate adjacent to the photonic IC is obvious in view of De Dobbelaere in view of Yoshimura as discussed above in reference to claim 10. As such, the claimed limitations of claim 14 is also rendered obvious for the same reasons discussed in reference to claim 10. Regarding claim 15, De Dobbelaere in view of Yoshimura renders the claimed apparatus and system of claims 1 and 8 obvious as already discussed above. Therefore, De Dobbelaere in view of Yoshimura also renders the claimed method of making such a system obvious, including receiving a first metallization structure, a second metallization structure, a nonlinear optical material therebetween, a photonic integrated circuit (IC), and an electrical IC; forming or coupling a switchable waveguide device over the electrical IC and laterally adjacent to the photonic IC, the switchable waveguide device comprising the first and second metallization structures and the nonlinear optical material, wherein the first and second metallization structures are coupled to the electrical IC, and the nonlinear optical material and the first and second metallization structures are at a same level above the electrical IC; and coupling the photonic IC and the electrical IC. Such steps of “receiving”, “providing” and “forming” the recited structural elements would have been necessarily carried out while making the inventive device of De Dobbelaere in view of Yoshimura in the manner discussed in claim 1 and 8. Regarding claim 16, De Dobbelaere in view of Yoshimura renders the claimed limitations obvious for the same reasons discussed above in reference to claims 2 and 9. Regarding claim 17, De Dobbelaere in view of Yoshimura renders the claimed limitations obvious for the same reasons discussed above in reference to claim 7. Regarding claim 18-19, De Dobbelaere in view of Yoshimura renders the method step of “depositing” obvious since De Dobbelaere in view of Yoshimura renders obvious the use of the nonlinear optical material and first and second metallization structures in the manner discussed above in reference to claim 1 and 8. Allowable Subject Matter Claim 6, 12, 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: as discussed above, an apparatus, comprising: a photonic integrated circuit comprising a first surface; an electrical IC comprising a second surface, wherein a first portion of the second surface is electrically coupled to the first surface; and a waveguide device laterally adjacent, and optically coupled to, the photonic IC wherein the waveguide device is over a second portion of the second surface is known in the art. However, none of the prior art fairly teaches or suggests such an apparatus further comprising a substantially transparent polymer disposed between the photonic IC and the glass substrate as claimed claim 12, or between the nonlinear optical material and the photonic IC as claimed in claim 20, or a nonlinear optical material that adjoins a substantially transparent polymer between a glass substrate and the photonic IC, and further wherein the substantially transparent polymer has an index of refraction approximately equal to an index of refraction of the nonlinear optical material or the photonic IC as claimed in claim 6. While the use of a glass substrate with a photonic IC and an electrical IC is known in the art, there is no credible reasons why or how one of ordinary skilled in the art would modify the optical apparatus of De Dobbelaere to have a substantially transparent polymer between the glass substrate and the photonic IC in the manner claimed in the present application. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG H PAK whose telephone number is (571)272-2353. The examiner can normally be reached M-F: 7AM- 5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SUNG H PAK/ Primary Examiner, Art Unit 2874
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Prosecution Timeline

Dec 28, 2022
Application Filed
Jul 03, 2023
Response after Non-Final Action
Feb 21, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
99%
With Interview (+11.5%)
2y 2m
Median Time to Grant
Low
PTA Risk
Based on 1202 resolved cases by this examiner. Grant probability derived from career allow rate.

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