Prosecution Insights
Last updated: April 19, 2026
Application No. 18/090,260

ELECTRO-OPTICAL CIRCUITS WITH MODULAR SWITCHABLE PHOTONIC INTERFACE

Non-Final OA §DP
Filed
Dec 28, 2022
Examiner
TAVLYKAEV, ROBERT FUATOVICH
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
60%
Grant Probability
Moderate
1-2
OA Rounds
2y 4m
To Grant
72%
With Interview

Examiner Intelligence

Grants 60% of resolved cases
60%
Career Allow Rate
529 granted / 875 resolved
-7.5% vs TC avg
Moderate +12% lift
Without
With
+11.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
34 currently pending
Career history
909
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
70.2%
+30.2% vs TC avg
§102
13.0%
-27.0% vs TC avg
§112
11.1%
-28.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 875 resolved cases

Office Action

§DP
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. DETAILED ACTION Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claim 1 – 20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 20 of copending Application No. 18/090,253 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because both sets of claims define a switchable waveguide device for a photonic integrated circuit (PIC), the switchable waveguide device being separate from the PIC and controlled by an electric IC that is bonded/soldered to the PIC. Claim 1 – 20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 20 of copending Application No. 18/090,258 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because both sets of claims define a switchable waveguide device for a photonic integrated circuit (PIC), the switchable waveguide device being separate from the PIC and controlled by an electric IC that is bonded/soldered to the PIC. This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. Allowable Subject Matter The subject matter pertaining to the claims would be allowable, if Applicant overcomes the double-patenting rejections. The reason for indicating allowable subject matter is that none of the prior art of record, taken alone or in combination, provides a motivation for a switchable waveguide device for a photonic integrated circuit (PIC), the switchable waveguide device being separate from the PIC and controlled by an electric IC. While a wide variety of switchable waveguide devices are known in the art, they are either used as standalone devices or comprised in PICs to switch or modulate light in individual parts of the PICs. The prior art of record does not teach expressly, render obvious and provides a motivation for an input switch/modulator/gate for a PIC, the switch/modulator/gate controlled by an electric IC that is bonded/soldered to the PIC. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2023/0043794 A1 US 11,681,104 B1 Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT TAVLYKAEV whose telephone number is (571)270-5634. The examiner can normally be reached 10:00 am - 6:00 pm, Monday - Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached on (571)272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ROBERT TAVLYKAEV/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Dec 28, 2022
Application Filed
Jul 05, 2023
Response after Non-Final Action
Jan 24, 2026
Non-Final Rejection — §DP (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12578596
OPTICAL MODULE CONFIGURATION WITH ACCOMMODATION THROUGH OPENING FOR VARIOUS MODULATORS SUPPORTIVE OF DIFFERENT OPTICAL MODULE SPECIFICATIONS
2y 5m to grant Granted Mar 17, 2026
Patent 12572050
SEMICONDUCTOR DEVICE INCLUDING OPTICAL RING WAVEGUIDE
2y 5m to grant Granted Mar 10, 2026
Patent 12566343
THIN FILM LITHIUM-CONTAINING PHOTONICS WAFER HAVING A TRAP-RICH SUBSTRATE
2y 5m to grant Granted Mar 03, 2026
Patent 12560829
Photonic Semiconductor Device and Method
2y 5m to grant Granted Feb 24, 2026
Patent 12546952
FIBRE OPTIC CABLE PLUGS AND FIBRE OPTIC CABLE CONNECTORS HAVING SUCH
2y 5m to grant Granted Feb 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
60%
Grant Probability
72%
With Interview (+11.9%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 875 resolved cases by this examiner. Grant probability derived from career allow rate.

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