Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Regarding the objection to claims 1–5 in the previous office action, amendments to the claims have overcome the objection, which is withdrawn.
Regarding the objection to claims 6–7 in the previous office action, amendments to the claims have overcome the objection, which is withdrawn.
Regarding the rejection of claims under 35 U.S.C. 102 and 35 U.S.C. 103, Applicant submits that claim 1, as amended, is not taught by Li or any combination of previously cited references.
In particular, Applicant states that “the claimed invention and Li are fundamentally different from each other, in terms of their purposes and associated specific schemes to achieve their different purposes” (pg. 7), and that Li’s purpose is “To replicate ANN performance in an SNN hardware environment without complex retraining. In Li's mapping, the magnitude of the synaptic delay is likely proportional to the magnitude of the bias value itself,” while the purpose of the claimed invention is “to precisely control the timing of bias application to solve hardware-level synchronization issues” (pg. 8).
Examiner respectfully disagrees. What is at issue is not whether the reference and the claimed invention differ in terms of purpose and how the purpose is achieved, but whether the reference teaches the broadest reasonable interpretation of the claim. Amended claim 1 recites in relevant part:
wherein […] a predetermined delay is applied to timing when a bias is provided to the plurality of neuron layers, and
wherein the predetermined delay is adjusted according to a device latency of a neuron layer to which a corresponding bias is provided, or according to a device latency of a synaptic layer located at a front of the neuron layer to which the corresponding bias is provided
Li, paragraph 0017, reads, “Further, in an embodiment of the present disclosure, the mapping relations of the synaptic strength and the synaptic delay further include: the spiking information being superposed by adopting an analog current superposition principle, on a basis of mapping the weight and the bias of the artificial neuron based on the MP model to the synaptic strength and the synaptic delay of the neuron based on the LIF model, respectively.” Examiner finds that Li’s determination of a delay based on, the application of a bias and the synaptic delay of a neuron is a reasonable interpretation of a “predetermined delay […] adjusted according to a device latency of a neuron layer to which a corresponding bias is provided.” That this delay adjustment is based on the applied bias is found to be a reasonable interpretation of “a predetermined delay is applied to timing when a bias is provided to the plurality of neuron layers.”
From Applicant’s statement that the claimed invention’s purpose is to “precisely control the timing of bias application,” Examiner considers that the intended interpretation of “a predetermined delay is applied to timing when a bias is provided to the plurality of neuron layers” may be that the delay applies more specifically to the application of the bias; however, Examiner notes that a plain reading of the wording is broader and includes a delay that is applied as a result of the bias.
Examiner respectfully suggests that the further differences Applicant notes between Li and the invention in the present disclosure are not reflected in the amended claim 1 language. In particular, Applicant states that “the claimed Invention, there is no proportional relationship between the bias value and the delay. Instead, the delay is a fixed hardware characteristic—device latency—of the physical layers to ensure the spike signal and the bias arrive at the neuron simultaneously,” and that the Li reference “fails to show or teach the claimed core technical features ‘adjusting a bias-provision delay based on the physical device latency of hardware layers’.”
Examiner respectfully disagrees. Examiner notes that the latency of the claim is recited as being “adjusted,” and therefore cannot be entirely “fixed.” Examiner further notes that the term “device latency of a neuron layer,” in its broadest reasonable interpretation, is not limited to a physical hardware characteristic. The specification provide no definition of the term, nor can the Examiner find any reference in the specification to the neuron layer latency necessarily being a hardware characteristic. Examiner further notes that the device of claim 1, as written, is not limited to a hardware implementation, but could include software, and that this interpretation is supported by paragraph 0022 of the present specification (“A spiking neural network providing device according to the present invention means that a spiking neural network is implemented in hardware or software”).
Examiner further notes that the wording “adjusting a bias-provision delay based on the physical device latency of hardware layers,” quoted in Applicant’s remarks, does not appear in the claim, but rather appears to be Applicant’s interpretation of the claim.
The arguments are therefore found unpersuasive. Examiner respectfully suggests Applicant consider amending the claim to more fully recite the key features of the disclosed invention or to otherwise clarify the points of distinction between the disclosed invention and the prior references.
Claim Rejections - 35 USC § 102
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 rejected under 35 U.S.C. 102(a) (2) as being anticipated by Li et al., US Pre-Grant Publication No. 2021/0357726 (hereafter Li).
Li teaches:
“A spiking neural network providing device comprising”: Li, paragraph 0006, “To this end, an object of the present disclosure is to provide a fusion structure of a convolutional neural network and a spiking neural network [A spiking neural network providing device], capable of simultaneously taking into account advantages of the convolutional neural network and the spiking neural network, i.e., taking an advantage of a high recognition accuracy of the convolutional neural network in the field of image recognition, and giving play to an advantage of the spiking neural network in aspects of sparsity, low power consumption, overfitting alleviation, and the like, such that the structure can be applied to fields of feature extraction, accurate classification, and the like of high-speed time-varying information.”
“a plurality of neuron layers; and a plurality of synaptic layers”: Li, paragraph 0071, “The convolutional neural network part [synaptic layers], the spiking converting and encoding part [neuron layers], the spiking neural network part, and the number of network layers in which the convolution operation or the pooling operation is completed involved in the fused network structure provided by the present disclosure can be added or deleted appropriately based on practical application tasks, can adapt to any scale of neural network structures, and have high flexibility and scalability.”
“wherein the plurality of neuron layers and the plurality of synaptic layers are simulated”: Li, paragraph 0004, “On the other hand, the spiking neural network is a new type of neural network that uses discrete neural spiking for information processing. Compared with conventional artificial neural networks, the spiking neural network has better biological simulation performance [the plurality of neuron layers and the plurality of synaptic layers are simulated], and thus is one of the research hot spots in recent years.”
“a spike signal is processed, and”: Li, paragraph 0064, “As illustrated in FIG. 6, when the spiking neuron receives an output signal of an upper-layer network, the spiking neuron determines whether the signal is the spiking information or the pixel-level data [a spike signal is processed].”
“a predetermined delay is applied to timing when a bias is provided to the plurality of neuron layers”: Li, paragraph 0050, “In an embodiment of the present disclosure, the mapping relations of the synaptic strength and the synaptic delay further include the pixel-level convolutional kernel and a pixel-level pooling window mapping a weight and a bias of an artificial neuron based on an MP model to the synaptic strength and the synaptic delay of the neuron based on the LIF model, respectively [a predetermined delay is applied to timing when a bias is provided to the plurality of neuron layers, predetermined delay interpreted as including a defined mapping between the bias and the delay].”
“wherein the predetermined delay is adjusted according to a device latency of a neuron layer to which a corresponding bias is provided, or according to a device latency of a synaptic layer located at a front of the neuron layer to which the corresponding bias is provided”: Li, paragraph 0017, “Further, in an embodiment of the present disclosure, the mapping relations of the synaptic strength and the synaptic delay further include: the spiking information being superposed by adopting an analog current superposition principle, on a basis of mapping the weight and the bias of the artificial neuron based on the MP model to the synaptic strength and the synaptic delay of the neuron [the predetermined delay is adjusted according to a device latency of a neuron layer to which a corresponding bias is provided, interpreted as determining a delay based on a delay of a neuron and a bias of the neuron] based on the LIF model, respectively.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 6 rejected under 35 U.S.C. 103 over Li in view of Nataraj, US Patent No. 12,417,388.
Regarding claim 2:
Li teaches “the spiking neural network providing device of claim 1.”
Li further teaches (bold only) “wherein the synaptic layer stores learning model data including a weight and a bias, each synaptic layer outputs a value obtained by combining a spiking signal output from a previous neuron layer and the weight, and the neuron layer adds the bias to an output value transmitted from a previous synaptic layer and outputs a result of addition”: Li, paragraph 0071, “The convolutional neural network part [synaptic layer], the spiking converting and encoding part [neuron layer], the spiking neural network part [a spiking signal], and the number of network layers in which the convolution operation or the pooling operation is completed involved in the fused network structure provided by the present disclosure can be added or deleted appropriately based on practical application tasks, can adapt to any scale of neural network structures, and have high flexibility and scalability.”
Li does not explicitly teach (bold only) “wherein the synaptic layer stores learning model data including a weight and a bias, each synaptic layer outputs a value obtained by combining a spiking signal output from a previous neuron layer and the weight, and the neuron layer adds the bias to an output value transmitted from a previous synaptic layer and outputs a result of addition.”
Nataraj teaches (bold only) “wherein the synaptic layer stores learning model data including a weight and a bias, each synaptic layer outputs a value obtained by combining a spiking signal output from a previous neuron layer and the weight, and the neuron layer adds the bias to an output value transmitted from a previous synaptic layer and outputs a result of addition”: Nataraj, col. 2, line 57 – col. 3, line 13, “FIG. 2 is a functional block diagram of a neuron 200 in a neural network. The neuron 200 may be an example of each node 110 in the neural network 100 (FIG. 1). Assuming the neuron 200 is in a hidden layer (e.g., hidden layer 104 or 106, FIG. 1) or output layer (e.g., output layer 108, FIG. 1), the neuron 200 receives a vector X that includes values from the outputs of the neurons ( e.g., each neuron) in a previous layer of the neural network to which the inputs of the neuron 200 are coupled. (If the neuron 200 is in the input layer 102, it may have a single input 102 that receives input values.) A multiplication module 202 multiplies the vector X by a vector of weights W [learning model data including a weight], to produce the product W-X. Each weight in the vector W is for a respective input of the neuron 200, and thus corresponds to (i.e., weights) values from a respective neuron in the previous layer of the neural network [each … layer outputs a value combining a … output from a previous … layer and the weight]. An addition module 204 adds a bias b to the product W-X, to produce the sum W -X + b [adds the bias to an output value transmitted from a previous … layer]. The multiplication module 202 and the addition module 204 compose a module 206 that receives the vector X and provides W-X+b. An activation function module 208 computes an activation function f(x), using W·X+b, as received from the module 206, as the argument x. The value of the activation function f(x), as computed using W-X+b as the argument x, is provided on an output for the neuron 200 [outputs a result of addition].”
Nataraj and Li are analogous arts as they are both related to neural network design and implementation. It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to have combined the weights and biases of Nataraj with the teachings of Li to arrive at the present invention, in order to provide a trainable neural model, as stated in Nataraj, col. 3, lines 19-30, “A neural network (e.g., the neural network 100, FIG. 1) (e.g., with neurons 200 as nodes) may operate in two modes: a training mode and an operating mode. The operating mode is used after the neural network has been trained and deployed. During the training mode (e.g., during neural network training 500, FIG. 5, such as neural-network training 600, FIG. 6), weights and biases are determined iteratively, by comparing outputs of the neural network to expected outputs and updating the weights and biases accordingly. During the operating mode, the weights and biases remain fixed, and the neural network provides outputs based on given inputs.”
Regarding claim 6:
Li teaches:
“An operating method of a spiking neural network providing device that simulates a plurality of neuron layers and a plurality of synaptic layers, the operating method comprising”: Li, paragraph 0071, “The convolutional neural network part [neuron layers], the spiking converting and encoding part, the spiking neural network part [synaptic layers], and the number of network layers in which the convolution operation or the pooling operation is completed involved in the fused network structure provided by the present disclosure can be added or deleted appropriately based on practical application tasks, can adapt to any scale of neural network structures, and have high flexibility and scalability”; Li, paragraph 0004, “On the other hand, the spiking neural network is a new type of neural network that uses discrete neural spiking for information processing. Compared with conventional artificial neural networks, the spiking neural network has better biological simulation performance [simulates a plurality of neuron layers and a plurality of synaptic layers], and thus is one of the research hot spots in recent years.”
“inputting input data to the spiking neural network providing device”: Li, paragraph 0008, “In order to achieve the above objects, in an aspect, an embodiment of the present disclosure provides a fusion structure of a convolutional neural network and a spiking neural network, including: a convolutional neural network structure including an input layer, a convolutional layer and a pooling layer, wherein the input layer is configured to receive pixel-level image data [inputting input data to the spiking neural network providing device], the convolutional layer is configured to perform a convolution operation, and the pooling layer is configured to perform a pooling operation.”
(bold only) “performing inference, by the plurality of neuron layers and the plurality of synaptic layers, based on learning model data including weights and biases stored in the plurality of synaptic layers”: Li, “The convolutional neural network part [neuron layers], the spiking converting and encoding part, the spiking neural network part [synaptic layers], and the number of network layers in which the convolution operation or the pooling operation is completed involved in the fused network structure provided by the present disclosure can be added or deleted appropriately based on practical application tasks, can adapt to any scale of neural network structures, and have high flexibility and scalability.”
“wherein the performing of the inference comprises applying the predetermined delay to the timing when the bias is provided to the plurality of neuron layers”: Li, paragraph 0050, “In an embodiment of the present disclosure, the mapping relations of the synaptic strength and the synaptic delay further include the pixel-level convolutional kernel and a pixel-level pooling window mapping a weight and a bias of an artificial neuron based on an MP model to the synaptic strength and the synaptic delay of the neuron based on the LIF model, respectively [applying the predetermined delay to the timing when the bias is provided to the plurality of neuron layers].”
“wherein the predetermined delay is adjusted according to a device latency of a neuron layer to which a corresponding bias is provided, or according to a device latency of a synaptic layer located at a front of the neuron layer to which the corresponding bias is provided”: Li, paragraph 0017, “Further, in an embodiment of the present disclosure, the mapping relations of the synaptic strength and the synaptic delay further include: the spiking information being superposed by adopting an analog current superposition principle, on a basis of mapping the weight and the bias of the artificial neuron based on the MP model to the synaptic strength and the synaptic delay of the neuron [the predetermined delay is adjusted according to a device latency of a neuron layer to which a corresponding bias is provided, interpreted as determining a delay based on a delay of a neuron and a bias of the neuron] based on the LIF model, respectively.”
Li does not explicitly teach (bold only) “performing inference, by the plurality of neuron layers and the plurality of synaptic layers, based on learning model data including weights and biases stored in the plurality of synaptic layers.”
Nataraj teaches (bold only) “performing inference, by the plurality of neuron layers and the plurality of synaptic layers, based on learning model data including weights and biases stored in the plurality of synaptic layers”: Nataraj, col. 2, line 57 – col. 3, line 13, “FIG. 2 is a functional block diagram of a neuron 200 in a neural network. The neuron 200 may be an example of each node 110 in the neural network 100 (FIG. 1). Assuming the neuron 200 is in a hidden layer (e.g., hidden layer 104 or 106, FIG. 1) or output layer (e.g., output layer 108, FIG. 1), the neuron 200 receives a vector X that includes values from the outputs of the neurons ( e.g., each neuron) in a previous layer of the neural network to which the inputs of the neuron 200 are coupled. (If the neuron 200 is in the input layer 102, it may have a single input 102 that receives input values.) A multiplication module 202 multiplies the vector X by a vector of weights W, to produce the product W-X. Each weight in the vector W is for a respective input of the neuron 200, and thus corresponds to (i.e., weights) [weights] values from a respective neuron in the previous layer of the neural network [stored in the plurality of synaptic layers]. An addition module 204 adds a bias b [biases] to the product W-X, to produce the sum W -X + b. The multiplication module 202 and the addition module 204 compose a module 206 that receives the vector X and provides W-X+b. An activation function module 208 computes an activation function f(x), using W·X+b, as received from the module 206, as the argument x. The value of the activation function f(x), as computed using W-X+b as the argument x, is provided on an output for the neuron 200 [performing inference].”
Nataraj and Li are analogous arts as they are both related to neural network design and implementation. It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to have combined the weights and biases of Nataraj with the teachings of Li to arrive at the present invention, in order to provide a trainable neural model, as stated in Nataraj, col. 3, lines 19-30, “A neural network (e.g., the neural network 100, FIG. 1) (e.g., with neurons 200 as nodes) may operate in two modes: a training mode and an operating mode. The operating mode is used after the neural network has been trained and deployed. During the training mode (e.g., during neural network training 500, FIG. 5, such as neural-network training 600, FIG. 6), weights and biases are determined iteratively, by comparing outputs of the neural network to expected outputs and updating the weights and biases accordingly. During the operating mode, the weights and biases remain fixed, and the neural network provides outputs based on given inputs.”
Claim 4 rejected under 35 U.S.C. 103 over Li in view of DeYong et al., US Patent No. 5,355,435 (hereafter DeYong).
Li teaches “The spiking neural network providing device of claim 1.”
Li further teaches:
(bold only) “a synaptic array in which the synaptic layer is implemented” and (bold only) “a neuron circuit in which the neuron layer is implemented”: Li, paragraph 0071, “The convolutional neural network part [in which the synaptic layer is implemented], the spiking converting and encoding part [in which the neuron layer is implemented], the spiking neural network part, and the number of network layers in which the convolution operation or the pooling operation is completed involved in the fused network structure provided by the present disclosure can be added or deleted appropriately based on practical application tasks, can adapt to any scale of neural network structures, and have high flexibility and scalability.”
(bold only) “wherein the controller applies the predetermined delay to the timing when the bias is provided to the plurality of neuron layers”: Li, paragraph 0050, “In an embodiment of the present disclosure, the mapping relations of the synaptic strength and the synaptic delay further include the pixel-level convolutional kernel and a pixel-level pooling window mapping a weight and a bias of an artificial neuron based on an MP model to the synaptic strength and the synaptic delay of the neuron based on the LIF model, respectively [applies the predetermined delay to the timing when the bias
is provided to the plurality of neuron layers].”
Li does not explicitly teach:
(bold only) “a synaptic array in which the synaptic layer is implemented”
(bold only) “a neuron circuit in which the neuron layer is implemented”
“a controller configured to control operations of the synaptic array and the neuron” and (bold only) “wherein the controller applies the predetermined delay to the timing when the bias is provided to the plurality of neuron layers”
DeYong teaches:
(bold only) “a synaptic array in which the synaptic layer is implemented”: DeYong, col. 9, line 67 – col. 10, line 7, “An additional object of the present invention is to provide a general purpose neural network processing element having a plurality of synapse triads, each synapse being independently disableable, from arrays of which [a synaptic array] general purpose neural networks may be constructed which permit emulation of any circuitry constructible from a plurality of neural network processing elements of the invention.”
(bold only) “a neuron circuit in which the neuron layer is implemented”: DeYong, col. 8, lines 7 – 18, “In the preferred embodiment, the chemical synapse simulators comprise excitatory, inhibitory, and shunting synapse simulators, which simulate both presynaptic and post synaptic regions. Preferably, the processing element [a neuron circuit] includes one or more bias adaptation networks for dynamically controlling one or more operational parameters of the axon hillock simulator, such as threshold/delay level, action potential pulsewidth level, and refractory period, or one or more operational parameters of the chemical synapse simulators, such as current amplitude, current duration, and delay period.”
“a controller configured to control operations of the synaptic array and the neuron” and (bold only) “wherein the controller applies the predetermined delay to the timing when the bias is provided to the plurality of neuron layers”: DeYong, col. 8, lines 7 – 18, “In the preferred embodiment, the chemical synapse simulators comprise excitatory, inhibitory, and shunting synapse simulators, which simulate both presynaptic and post synaptic regions. Preferably, the processing element includes one or more bias adaptation networks for dynamically controlling [a controller configured to control operations of the synaptic array and the neuron][wherein the controller] one or more operational parameters of the axon hillock simulator, such as threshold/delay level, action potential pulsewidth level, and refractory period, or one or more operational parameters of the chemical synapse simulators, such as current amplitude, current duration, and delay period.”
DeYong and Li are analogous arts as they are both related to the simulation of neural processes. It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to have combined the hardware implementations of DeYong with the teachings of Li to arrive at the present invention, in order to provide devices which solve temporal problems, as stated in DeYong, col. 1, lines 15-19, “In particular, the present invention relates to asynchronous temporal processing elements which simulate neuron electrophysiology at subcellular levels. The present invention is useful in solving a wide range of temporal signal processing problems.”
Claim 5 rejected under 35 U.S.C. 103 over Li in view of Wong et al., US Pre-Grant Publication No. 2021/0133588 (hereafter Wong).
Li teaches “The spiking neural network providing device of claim 1.”
Li further teaches:
(bold only) “a memory storing a spiking neural network providing program for implementing operations of the plurality of synaptic layers and the plurality of neuron layers” and (bold only) “a processor configured to execute the spiking neural network providing program”: Li, paragraph 0071, “The convolutional neural network part [implementing operations of the plurality of synaptic layers], the spiking converting and encoding part [the plurality of neuron layers], the spiking neural network part [spiking neural network], and the number of network layers in which the convolution operation or the pooling operation is completed involved in the fused network structure provided by the present disclosure can be added or deleted appropriately based on practical application tasks, can adapt to any scale of neural network structures, and have high flexibility and scalability.”
(bold only) “wherein the spiking neural network providing program applies the predetermined delay to the timing when the bias is provided to the plurality of neuron layers”: Li, paragraph 0050, “In an embodiment of the present disclosure, the mapping relations of the synaptic strength and the synaptic delay further include the pixel-level convolutional kernel and a pixel-level pooling window mapping a weight and a bias of an artificial neuron based on an MP model to the synaptic strength and the synaptic delay of the neuron based on the LIF model, respectively [applies the predetermined delay to the timing when the bias is provided to the plurality of neuron layers, predetermined delay interpreted as including a defined mapping between the bias and the delay].”
Li does not explicitly teach:
(bold only) “a memory storing a spiking neural network providing program for implementing operations of the plurality of synaptic layers and the plurality of neuron layers”
(bold only) “a processor configured to execute the spiking neural network providing program”
(bold only) “wherein the spiking neural network providing program applies the predetermined delay to the timing when the bias is provided to the plurality of neuron layers”
Wong teaches (bold only) “a memory storing a spiking neural network providing program for implementing operations of the plurality of synaptic layers and the plurality of neuron layers”, (bold only) “a processor configured to execute the spiking neural network providing program” and (bold only) “wherein the spiking neural network providing program applies the predetermined delay to the timing when the bias is provided to the plurality of neuron layers”: Wong, paragraph 0007, “In a second aspect of the present disclosure, there is provided an electronic device. The electronic device comprises at least one processor [a processor configured to execute]; and at least one memory storing computer program instructions [a memory storing a … providing program], the at least one memory and the computer program instructions being configured, with the at least processor, to cause the electronic device to perform acts. The acts comprises processing first input data by using a first machine learning model having first parameter set values, to obtain first feature information of the first input data, the first machine learning model having a capability of self-ordering and the first parameter set values being updated after the processing of the first input data; generating a first classification result for the first input data based on the first feature information by using a second machine learning model having second parameter set values; processing second input data by using the first machine learning model having the updated first parameter set values, to obtain second feature information of the second input data; and generating a second classification result for the second input data based on the second feature information by using the second machine learning model having the second parameter set values”; Wong, paragraph 0035, “An example of the first machine learning model 210 is an unsupervised spiking neural network (SNN).”
Wong and Li are analogous arts as they are both related to spiking neural network models. It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to have combined the hardware implementation of Wong with the teachings of Li to arrive at the present invention, in order to provide an adaptable model implementation, as stated in Wong, paragraphs 0003-0004, “Such tasks are collectively referred to as machine learning tasks. Machine learning tasks often rely on a large amount of data and a high processing capability, especially a parallel processing capability. As such, in addition to general-purpose processing resources such as Central Processing Units (CPUs) and storage resources such as storage devices, execution of the machine learning tasks also requires dedicated processing resources such as Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs ). Depending on different task objectives, complexity, and accuracy, different machine learning tasks may have different resource demands.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wang et al., US Pre-Grant Publication No. 2015/0242745, discloses a method of inference and training for spiking neural networks which includes bias weights to input events.
Chen et al., US Pre-Grant Publication No. 2019/0197391, discloses a spiking neural network which may conditionally apply a bias to a neuron based on a comparison of the bias to a threshold, and which also includes setting a bias value based on whether the attached neuron issued a spike during a previous time period.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/VAS/
Examiner, Art Unit 2129
/MICHAEL J HUNTLEY/Supervisory Patent Examiner, Art Unit 2129
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