DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to RCE filed on 12/04/2025. Claims 3 and 12 were canceled before. New dependent claims 23-24 were added in this RCE. Claims 1-2, 4-11, and 13-24 have been examined and are pending in this application.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/04/2025 has been entered.
Response to Arguments
Applicant’s arguments, filed 11/03/2025, with respect to claims 1-2, 4-11, and 13-24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
A new reference Malshe et al. US 2023/0229325 is cited in this Office Action necessitated by the amendment.
The 35 U.S.C. 101 rejection of claims 10-11 and 13-18 is withdrawn.
In view of the new reference, independent claims 1, 10, and 19-20 are not in a condition for allowance. Claims depending therefrom, either directly or indirectly, are also not in a condition for allowance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-11, and 13-22 are rejected under 35 U.S.C. 103 as being unpatentable over Cariello US 2022/0342812 (“Cariello”) in view of Malshe et al. US 2023/0229325 (“Malshe”).
As per independent claim 1, Cariello teaches A method for operating a memory controller (Techniques for performing garbage collection by a memory controller is disclosed, paras 0012 and 0116), the method comprising:
providing a plurality of virtual blocks to be collected (FIG. 3B illustrates an example of a virtual block 300-b for garbage collection. The virtual block 300-b may include physical blocks 360, para 0087. Garbage collection procedure frees up blocks by moving valid data to new blocks, para 0011);
acquiring identification information of valid memory cell sets in the virtual blocks to be collected (The virtual block 300-b may include a valid PTU (page table unit) 334 or an invalid PTU 332 as well as associated color of each physical block to optimize garbage collection. A first color 322 may indicate hot data and a second color 324 may indicate cold data, para 0089);
determining valid memory cell sets for storing cold data in the virtual blocks to be collected according to the identification information (The virtual block 300-b may include a valid PTU (page table unit) 334 or an invalid PTU 332 as well as associated color of each physical block to optimize garbage collection. The second color 324 may indicate cold data, para 0089), wherein the identification information comprises hot and cold attributes indicating stored hot and cold data in the valid memory cell sets, respectively (The first color 322 may indicate hot data and the second color 324 may indicate cold data, para 0089), the hot data having a greater access frequency than the cold data (“hot data may be data that has a higher tendency for being overwritten, while cold data may have a lower tendency to be overwritten.” Para 0068).
Cariello discloses all of the claim limitations from above, but does not explicitly teach “if the sum of the numbers of the valid memory cell sets for storing cold data in the plurality of virtual blocks to be collected is greater than or equal to the number of memory cell sets of a target virtual block, collecting the cold data to fully fill the target virtual block”.
However, in an analogous art in the same field of endeavor, Malshe teaches if the sum of the numbers of the valid memory cell sets for storing cold data in the plurality of virtual blocks to be collected is greater than or equal to the number of memory cell sets of a target virtual block, collecting the cold data to fully fill the target virtual block (“Ideally the worn block stripe is entirely filled with ‘cold’ data. In the event there is not enough ‘cold’ data to entirely fill the block stripe, the remainder is typically filled with the ‘coldest’ data available.” Para 0020. “As used herein, a ‘block stripe’ generally refers to a logical grouping of blocks that share a same upper block number and can be accessed in parallel.” Para 0017. A “block stripe” is mapped to the claimed “virtual block”. Clearly para 0020 teaches that the cold data is greater than or equal to a capacity of the block stripe).
Given the teaching of Malshe, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Cariello with “if the sum of the numbers of the valid memory cell sets for storing cold data in the plurality of virtual blocks to be collected is greater than or equal to the number of memory cell sets of a target virtual block, collecting the cold data to fully fill the target virtual block”. The motivation would be that wear leveling and garbage collection operations extend the life of a memory device, para 0045 of Malshe..
As per dependent claim 2, Cariello in combination with Malshe discloses the method of claim 1. Cariello teaches wherein before the acquiring identification information of valid memory cell sets in the virtual blocks to be collected, the method further comprises: acquiring logic cell address and corresponding physical cell addresses of memory cell sets in the virtual blocks to be collected (The memory system controller 215 performs the task of address translations between logical addresses (e.g., LBAs) associated with commands from a host system 205 into physical addresses (e.g., PBAs) associated with memory cells within memory devices 240, para 0063);
determining the valid memory cell sets from the memory cell sets in the virtual blocks to be collected according to the physical cell addresses (The memory system 310 may reference a PVT (page validity table) 330 and may identify whether the pages 320 include valid data or invalid data, para 0073 and FIG. 3A).
As per dependent claim 4, Cariello in combination with Malshe discloses the method of claim 1. Cariello teaches wherein before the providing the plurality of virtual blocks to be collected, the method further comprises: acquiring the number of valid memory cell sets in a memory virtual block; and determining the plurality of virtual blocks to be collected from the memory virtual block according to the number of the valid memory cell sets in the memory virtual block (Prior to garbage collection, the PVT 330 may indicate that the block of data contains an amount of invalid data that exceeds a threshold amount. The memory system 310 may determine that an amount of valid data of a block falls below a threshold (e.g., contains invalid data) and responsively perform garbage collection, para 0075. FIG. 3B illustrates an example of a virtual block 300-b for garbage collection. The virtual block 300-b may include physical blocks 360, para 0087).
As per dependent claim 5, Cariello in combination with Malshe discloses the method of claim 1. Cariello teaches wherein before the providing the plurality of virtual blocks to be collected, the method further comprises: acquiring the number of valid memory cell sets in a memory virtual block; and determining the plurality of virtual blocks to be collected from the memory virtual block according to a first ratio of the number of the valid memory cell sets in the memory virtual block to the number of memory cell sets in the memory virtual block (Prior to garbage collection, the PVT 330 may indicate that the block of data contains an amount of invalid data that exceeds a threshold amount. The memory system 310 may determine that an amount of valid data of a block falls below a threshold (e.g., contains invalid data) and responsively perform garbage collection, para 0075. FIG. 3B illustrates an example of a virtual block 300-b for garbage collection. The virtual block 300-b may include physical blocks 360, para 0087).
As per dependent claim 6, Cariello in combination with Malshe discloses the method of claim 5. Cariello teaches wherein the determining the plurality of virtual blocks to be collected from the memory virtual block according to the first ratio of the number of the valid memory cell sets in the memory virtual block to the number of memory cell sets in the memory virtual block further comprises: if the first ratio is less than a first preset value, determining the memory virtual block as the virtual block to be collected (Prior to garbage collection, the PVT 330 may indicate that the block of data contains an amount of invalid data that exceeds a threshold amount. The memory system 310 may determine that an amount of valid data of a block falls below a threshold (e.g., contains invalid data) and responsively perform garbage collection, para 0075. FIG. 3B illustrates an example of a virtual block 300-b for garbage collection. The virtual block 300-b may include physical blocks 360, para 0087).
As per dependent claim 7, Cariello in combination with Malshe discloses the method of claim 1. Cariello teaches wherein before the providing the plurality of virtual blocks to be collected, the operation method further comprises: acquiring the number of valid memory cell sets in a memory virtual block and the number of valid memory cell sets for storing cold data in the memory virtual block; and determining the plurality of virtual blocks to be collected from the memory virtual block according to a second ratio of a difference between the number of the valid memory cell sets in the memory virtual block and the number of the valid memory cell sets for storing cold data in the memory virtual block to the number of memory cell sets in the memory virtual block (Prior to garbage collection, the PVT 330 may indicate that the block of data contains an amount of invalid data that exceeds a threshold amount. The memory system 310 may determine that an amount of valid data of a block falls below a threshold (e.g., contains invalid data) and responsively perform garbage collection, para 0075. FIG. 3B illustrates an example of a virtual block 300-b for garbage collection. The virtual block 300-b may include physical blocks 360, para 0087. Referring to FIG. 4, at 445, a determination may be made whether all the colors are processed. For example, the memory system may determine whether an amount of processed colors satisfies a threshold. In some examples, the memory system may determine that the amount of processed colors fails to satisfy the threshold. In response to determining that one or more colors remain to be processed, the memory system may load the color bitmap at 415. In other examples, the memory system may determine that the amount of processed colors satisfies the threshold (e.g., that all the colors are processed), para 0104 and FIG. 4).
As per dependent claim 8, Cariello in combination with Malshe discloses the method of claim 7. Cariello teaches wherein the determining the plurality of virtual blocks to be collected from the memory virtual block according to the second ratio of the difference between the number of the valid memory cell sets in the memory virtual block and the number of the valid memory cell sets for storing cold data in the memory virtual block to the number of memory cell sets in the memory virtual block further comprises: if the second ratio is less than a background garbage collection threshold, determining the memory virtual block as the virtual block to be collected (Prior to garbage collection, the PVT 330 may indicate that the block of data contains an amount of invalid data that exceeds a threshold amount. The memory system 310 may determine that an amount of valid data of a block falls below a threshold (e.g., contains invalid data) and responsively perform garbage collection, para 0075. FIG. 3B illustrates an example of a virtual block 300-b for garbage collection. The virtual block 300-b may include physical blocks 360, para 0087. Referring to FIG. 4, at 445, a determination may be made whether all the colors are processed. For example, the memory system may determine whether an amount of processed colors satisfies a threshold. In some examples, the memory system may determine that the amount of processed colors fails to satisfy the threshold. In response to determining that one or more colors remain to be processed, the memory system may load the color bitmap at 415. In other examples, the memory system may determine that the amount of processed colors satisfies the threshold (e.g., that all the colors are processed), para 0104 and FIG. 4).
As per dependent claim 9, Cariello in combination with Malshe discloses the method of claim 1. Cariello teaches wherein: the valid memory cell sets include a first valid memory cell subset and a second valid memory cell subset (The page validity table (PVT) may be used to track the mapping status (e.g., valid or invalid data) for pages within physical memory blocks, para 0011), and the first valid memory cell subset is used for storing user data (The page validity table (PVT) may be used to track the mapping status (e.g., valid or invalid data) for pages within physical memory blocks, para 0011);
the second valid memory cell subset is used for storing the identification information (The PVT may be stored in a location that is outside the physical memory blocks storing the pages of data because the PVT is frequently updated, para 0011. The present invention utilizes PVT colors for the garbage collection procedure. The PVT color information may indicate whether data is hot or cold, para 0013).
As per claims 10-11 and 13-18, these claims are respectively rejected based on arguments provided above for similar rejected claims 1-2 and 4-9. See FIG. 1 for memory controller 115, para 0019 of Cariello.
As per claims 19 and 21-22, this claim is rejected based on arguments provided above for similar rejected independent claim 1-2 and 4. See FIG. 1 for a memory system 110, para 0016 of Cariello.
As per independent claim 20, this claim is rejected based on arguments provided above for similar rejected independent claim 1. FIG. 1 illustrates an example system 100, para 0015 of Cariello.
Claims 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Cariello in view of Malshe and in further view of Peh et al. US 2022/0197535 (“Peh”).
As per dependent claim 23, Cariello in combination with Malshe discloses the method of claim 1. Cariello and Malshe may not explicitly disclose, but in an analogous art in the same field of endeavor, Peh teaches further comprising: sorting the numbers of valid memory cell sets in the virtual blocks to be collected from small to large (“The memory controller sorts (operation 204) the list of superblocks based on a number of valid memory unit counts.” Para 0044 and FIGS. 2A-B. Sorting in ascending or descending order is a design choice);
moving the numbers of the valid memory cell sets in the virtual blocks to be collected from small to large sequentially to target virtual blocks (“the superblock with the lowest count of valid memory counts is selected” para 0045 and FIGS. 2A-B. “as shown at operation 222, the processing device relocates data from the memory units to a new location. The new location can be in a separate block in a separate superblock that is not currently subject to garbage collection operations.” Para 0049 and FIGS. 2A-B).
Given the teaching of Peh, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Cariello with “sorting the numbers of valid memory cell sets in the virtual blocks to be collected from small to large” and ”moving the numbers of the valid memory cell sets in the virtual blocks to be collected from small to large sequentially to target virtual blocks”. The motivation would be that wear leveling and garbage collection operations extend the lifespan of a memory device and improves performance, para 0023 of Peh.
As per dependent claim 24, this claim is rejected based on arguments provided above for similar rejected dependent claim 23.
Conclusion
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/ZUBAIR AHMED/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132