DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-16, in the reply filed on 12/31/25 is acknowledged.
Claims 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/31/25.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2 and 9-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Okuda et al (10,707,155 B2).
Regarding claim 1, Okuda et al discloses a semiconductor device (Figures 4 and 5) comprising: a semiconductor layer (Figure 5, reference 51) having a partitioned region (Figure 5, reference 85) partitioned by a trench (Figure 5, reference 63); a field insulating layer (Figure 5, reference 76) which is formed on a main surface of the semiconductor layer (Figure 5, reference 51) at an interval from the trench (Figure 5, reference 76) toward an inner side of the partitioned region (Figure 5, reference 85) and covers the partitioned region (Figure 5, reference 76); a trench insulating layer (Figure 5, reference 72) formed at least in the trench (Figure 5, reference 71); an intermediate region (Figure 5, reference 78) annularly formed between the field insulating layer (Figure 5, reference 76) on the main surface of the semiconductor layer (Figure 5, reference 51) and the trench insulating layer (Figure 5, reference 72; and a bridge insulating layer (Figure 4, reference 79) which is formed in the intermediate region (Figure 5, reference 78) and connects the field insulating layer (Figure 5, reference 76) and the trench insulating layer (Figure 5, reference 72), wherein the bridge insulating layer (Figure 4, reference 79) has a bridge buried portion buried in the main surface of the semiconductor layer (Figure 5, reference 52).
Regarding claim 2, Okuda et al discloses wherein the bridge insulating layer has a peripheral edge portion including a bird's beak (Figure 4, reference 79).
Regarding claim 9, Okuda et al discloses further comprising: an interlayer insulating layer (Figure 5, reference 95) which is formed on the main surface of the semiconductor layer (Figure 5, reference 52) and covers the field insulating layer (Figure 5, reference 76) and the bridge insulating layer (Figure 4, reference 79), wherein the interlayer insulating layer has a thickness of 6,000 A or more and 10,000 A or less (Figure 5, reference 95).
Regarding claim 10, Okuda et al discloses wherein the field insulating layer (Figure 5, reference 76), the trench insulating layer (Figure 5, reference 72), and the bridge insulating layer (Figure 4, reference 79) are formed by one insulating layer which extends continuously (column 11, lines 40-43).
Regarding claim 11, Okuda et al discloses wherein an opening (Figure 5, reference 77) is formed in the field insulating layer (Figure 5, reference 76).
Regarding claim 12, Okuda et al discloses wherein the partitioned region (Figure 5, reference 85) is an active region including an insulated gate transistor (Figure 5, reference 90), and wherein a gate insulating layer (Figure 5, reference 84) of the insulated gate transistor (Figure 5, reference 90) is formed in the opening (Figure 5, reference 77) of the field insulating layer (Figure 5, reference 76).
Regarding claim 13, Okuda et al discloses wherein the trench insulating layer (Figure 5, reference 72) is formed in a film shape along an inner wall of the trench (Figure 5, reference 71) so as to partition a concave space within the trench (Figure 5, reference 71).
Regarding claim 14, Okuda et al discloses further comprising: a buried layer (Figure 5, reference 73) buried in the concave space partitioned by the trench insulating layer (Figure 5, reference 72) within the trench (Figure 5, reference 71).
Regarding claim 15, Okuda et al discloses wherein the buried layer (Figure 5, reference 73) contains polysilicon (column 10, lines 34-35).
Regarding claim 16, Okuda et al discloses wherein the trench (Figure 5, reference 71) is formed in an annular shape in a plan view (column 30, lines 27-28) seen in a normal direction of the main surface of the semiconductor layer (Figure 5, reference 51).
Allowable Subject Matter
Claims 3-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art does not disclose nor fairly suggest a semiconductor device comprising: wherein the trench insulating layer includes a trench inner covering portion covering an inner wall of the trench, and a field covering portion drawn out from the trench inner covering portion to the main surface of the semiconductor layer and connected to the field insulating layer via the bridge insulating layer, wherein the field covering portion has a first buried portion buried in the main surface of the semiconductor layer, wherein the field insulating layer has a second buried portion buried in the main surface of the semiconductor layer, and wherein the bridge buried portion, the first buried portion, and the second buried portion are formed by a single buried portion which is integrally continuous in a direction along the main surface of the semiconductor layer (claim 3) and wherein the semiconductor layer is in contact with a bottom of the bridge buried portion and has a low step surface having a step difference with respect to the main surface of the semiconductor layer, and wherein the step difference between the main surface of the semiconductor layer and the low step surface of the semiconductor layer is 1,000 A or more and 1,500 A or less (claim 8) further incorporated into independent claim 16 and in the context of its recited apparatus, along with its depending claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MONICA D HARRISON whose telephone number is (571)272-1959. The examiner can normally be reached M-F 7-4:30pm.
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/MONICA D HARRISON/Primary Examiner, Art Unit 2815
mdh
January 21, 2026