DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to the reply filed 04 February 2026.
Claims 2 and 7-27 are pending and have been presented for examination.
Claims 1 and 3-6 have been cancelled.
Response to Arguments
Applicant’s arguments with respect to claim(s) 12 and 23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 10-15 and 21-25 are is/are rejected under 35 U.S.C. 103 as being unpatentable over LI (U.S. Patent Application Publication #2022/0374149) in view of RAJENDIRAN (U.S. Patent Application Publication #2023/0066344).
2. The system of claim 23, wherein the plurality of data structures is one of a plurality of buffers, a plurality of queues, a plurality of stacks, or a plurality of heaps (see LI [0043]: queues).
10. The system of claim 23, wherein the processing circuitry is to: determine the second data structure further based on a depth of the second data structure (see RAJENDIRAN [0041]: memory space value).
11. The system of claim 10, wherein the processing circuitry is further to: determine the request block size of the second request; and determine the second data structure based on a data structure with a smallest depth among the plurality of data structures (see RAJENDIRAN [0041]: if one queue is unavailable, another queue that has memory space is selected, this selected queue would have a smaller depth than the unavailable queue).
12. LI discloses A method, comprising: receiving, by a storage device driver, a plurality of requests (see [0041]: receive I/O requests), comprising a first request and a second request (see [0041]: requests are plural, indicating multiple requests can be sent), wherein each request of the plurality of requests is of a request block size (see [0042]: size of I/O request; [0043]: number of vectors read in the request would be a block size); causing the first request to be stored in a first data structure from a plurality of data structures (see [0043]: request is placed in a queue based on the amount of vectors read, there are multiple queues); determining, by the storage device driver, based on the request block size of the second request, a second data structure from the plurality of data structures (see [0043]: request is placed in a queue based on the amount of vectors read, there are multiple queues) having sufficient available memory capacity for the request block size of the second request (see RAJENDIRAN below); and causing the second request to be stored in the second data structure (see [0043]: request is placed in a queue based on the amount of vectors read, there are multiple queues).
RAJENDIRAN discloses the following limitations that are not taught by LI: determining a second data structure from the plurality of data structures (see [0015]: multiple read and write buffers are configured in the system) having sufficient available memory capacity for the request block size of the second request (see [0041]: a buffer is selected using a memory space value to determine if the buffer is available). By increasing the number of buffers in the memory controller, the system is able to process more commands concurrently, thereby increasing the number of commands that can be performed over a period of time (see [0016]). A combination of LI and RAJENDIRAN would result in LI having multiple buffers for each command size, and selecting a buffer that is available based on memory space in the buffer.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify LI to select among multiple buffers based on available capacity, as disclosed by RAJENDIRAN. One of ordinary skill in the art would have been motivated to make such a modification to increase the number of commands that can be executed in parallel, as taught by RAJENDIRAN. LI and RAJENDIRAN are analogous/in the same field of endeavor as both references are directed to managing buffers for a storage system.
13. The method of claim 12, wherein the plurality of data structures is one of a plurality of queues, a plurality of stacks, or a plurality of heaps (see LI [0043]: queues).
14. The method of claim 12, wherein the first data structure is a same type of data structure as the second data structure (see LI [0043]: all the queues are the same type of structure, just allocated for different size commands).
15. The method of claim 12, wherein the plurality of data structures is to store non-volatile memory express (NVMe) requests, wherein a solid-state drive (SSD) storage device (see [0031]: SSD) comprises the storage device driver (see LI [0055]: NVMe driver).
21. The method of claim 12, further comprising: determining the second data structure further based on a depth of the second data structure (see RAJENDIRAN [0041]: memory space value).
22. The method of claim 21, further comprising: determining the request block size of the second request; and determining the second data structure based on a data structure with a smallest depth among the plurality of data structures (see RAJENDIRAN [0041]: if one queue is unavailable, another queue that has memory space is selected, this selected queue would have a smaller depth than the unavailable queue).
23. LI discloses A system, comprising: storage circuitry for storing a plurality of data structures to store requests (see [0029]: memory 115); and processing circuitry (see [029]: processor), to: receive a plurality of requests (see [0041]: receive I/O requests), comprising a first request and a second request (see [0041]: requests are plural, indicating multiple requests can be sent), wherein each request of the plurality of requests is of a request block size (see [0042]: size of I/O request; [0043]: number of vectors read in the request would be a block size), cause the first request to be stored in a first data structure from the plurality of data structures (see [0043]: request is placed in a queue based on the amount of vectors read, there are multiple queues), determine, based on the request block size of the second request, a second data structure from the plurality of data structures (see [0043]: request is placed in a queue based on the amount of vectors read, there are multiple queues) having sufficient available memory capacity for the request block size of the second request (see RAJENDIRAN below), and cause the second request to be stored in the second data structure (see [0043]: request is placed in a queue based on the amount of vectors read, there are multiple queues).
RAJENDIRAN discloses the following limitations that are not taught by LI: determining a second data structure from the plurality of data structures (see [0015]: multiple read and write buffers are configured in the system) having sufficient available memory capacity for the request block size of the second request (see [0041]: a buffer is selected using a memory space value to determine if the buffer is available). By increasing the number of buffers in the memory controller, the system is able to process more commands concurrently, thereby increasing the number of commands that can be performed over a period of time (see [0016]). A combination of LI and RAJENDIRAN would result in LI having multiple buffers for each command size, and selecting a buffer that is available based on memory space in the buffer.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify LI to select among multiple buffers based on available capacity, as disclosed by RAJENDIRAN. One of ordinary skill in the art would have been motivated to make such a modification to increase the number of commands that can be executed in parallel, as taught by RAJENDIRAN. LI and RAJENDIRAN are analogous/in the same field of endeavor as both references are directed to managing buffers for a storage system.
24. The system of claim 23, wherein the first data structure is a same type of data structure as the second data structure (see LI [0043]: all the queues are the same type of structure, just allocated for different size commands).
25. The system of claim 23, wherein the plurality of data structures is to store non- volatile memory express (NVMe) requests (see LI [0055]: NVMe driver), wherein the storage circuitry is located on a solid- state drive (SSD) storage device (see [0031]: SSD).
Allowable Subject Matter
Claims 7-9, 16-20, 26 and 27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The state of the art fails to anticipate, or render obvious, “…determining a depth of the first data structure, wherein determining the second data structure is further based on the depth of the first data structure.”
The state of the art fails to anticipate, or render obvious, “…determining whether a stored memory of the first data structure has exceeded a preset data structure memory; and in response to determining that the stored memory of the first data structure has exceeded the preset data structure memory: determining the second data structure, wherein the stored memory of the second data structure has not exceeded the preset data structure memory.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD J DUDEK JR whose telephone number is (571)270-1030. The examiner can normally be reached Monday - Friday, 8:00A-4:00P.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain T Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD J DUDEK JR/ Primary Examiner, Art Unit 2132
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