Prosecution Insights
Last updated: October 02, 2026
Application No. 18/091,207

CHARGE ISOLATION ARCHITECTURE IN VOLTAGE REGULATOR FOR IMPROVED BATTERY LIFE, RESPONSIVENESS AND REDUCED ACOUSTIC NOISE

Final Rejection §103
Filed
Dec 29, 2022
Examiner
NGUYEN, PHIL K
Art Unit
Tech Center
Assignee
Intel Corporation
OA Round
2 (Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
453 granted / 549 resolved
+22.5% vs TC avg
Moderate +14% lift
Without
With
+14.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
19 currently pending
Career history
567
Total Applications
across all art units

Statute-Specific Performance

§101
7.3%
-32.7% vs TC avg
§103
52.7%
+12.7% vs TC avg
§102
19.9%
-20.1% vs TC avg
§112
12.0%
-28.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 549 resolved cases

Office Action

§103
DETAILED ACTION Claims 1 – 21 are pending. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Brown et al (US Publication 20130249505 A1) and in view of McCune (US Publication 20140103889 A1). The teachings of Brown as disclosed in the previous office action are hereby incorporated by reference to the extent applicable to the amended claims. Applicant has amended independent claims 1 and 15 to incorporate the limitation that (1) turn off the switch to prevent discharge of the bulk capacitor via the power output rail due to leakage current in the circuit. Regarding limitation (1), Applicant Brown is silent about preventing discharge of the bulk capacitor via the power output rail due to leakage current in the circuit. However, McCune discloses the controller is to turn off the switch to prevent discharge of the bulk capacitor via the power output rail due to leakage current in the circuit when the signal indicates the circuit transitions from the active state [active state] to the idle state [inactive state] [0024: When the DC-DC converter 500 is in its operating state (FIG. 5A), the switch 504 remains closed and the linear regulator 502 operates to produce a regulated output voltage Vout, similar to as in a conventional linear regulator. However, upon a detected or expected large and abrupt decrease in load current (or based on some other external command independent of load conditions), the switch 504 is opened (FIG. 5B), isolating the output capacitor 506 and allowing the DC-DC converter 500 to transition rapidly to a disabled state][0020: a large and abrupt decrease in load current corresponds to a change of the load 212 from an active state to an inactive state][Claim 3: a shunt switch coupled across said capacitor configured to force an output voltage across the load to zero volts or substantially zero volts upon or as power delivery to the load is removed [Claim 7: disabling the DC-DC converter includes preventing charge stored in an output capacitor of the DC-DC converter from discharging through the load as the DC-DC converter is disabled] (prevent discharge of the bulk capacitor via the power output rail due to leakage current in the load circuit). PNG media_image1.png 640 489 media_image1.png Greyscale Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Brown and McCune together because they both directed to disconnect the capacitor in response to detecting idle condition of the load circuit. McCune’s disclosing of disconnecting the capacitor to remove power from the load circuit in response to idle condition of the load circuit would allow Brown to achieve more power saving or avoid wasted power by completely disconnecting the capacitor power from the load circuit, thereby avoiding/preventing leakage power in the load circuit. Regarding claim 2, McCune discloses the apparatus of claim 1, wherein: when the switch is turned on, a voltage of one side of the bulk capacitor is at ground; and when the switch is turned off, the voltage of the one side of the bulk capacitor is floated [0019-0024] [Figs. 2-6]. Regarding claim 3, McCune discloses the apparatus of claim 1, wherein: the capacitor is one of a plurality of bulk capacitors; and each capacitor of the plurality of bulk capacitors is coupled to the power output rail and ground via a respective path and each respective path comprises a respective switch [0019-0024] [Figs. 2-6]. Regarding claim 4, McCune discloses the apparatus of claim 1, further comprising one or more decoupling capacitors coupled to the power output rail [0019-0024] [Figs. 2-6]. Regarding claim 5, McCune discloses the apparatus of claim 1, wherein: the voltage regulator is a switching voltage regulator; and when the signal indicates the circuit transitions from the idle state to the active state, the controller is to start to switch the voltage regulator to increase a voltage of the power output rail, and the controller is to turn on the switch when the controller senses that a voltage of the power output rail has increased above a threshold [0019-0024] [Figs. 2-6]. Regarding claims 6 -10, these claims are taught by Brown as disclosed in the previous office action. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Brown et al (US Publication 20130249505 A1) and in view of McCune (US Publication 20140103889 A1) and in further view of Suryanarayana (US Publication 20220291732 A1). Regarding claim 11, Brown and McCune do not explicitly disclose wherein the signal comprises a voltage identification signal which identifies a requested voltage output of the voltage regulator. Suryanarayana discloses the signal comprises a voltage identification signal which identifies a requested voltage output of the voltage regulator [Claim 10: the control circuit is to encode an 8-bit voltage identifier code for a first voltage into an encoded value and send the encoded value to the voltage regulator to cause the voltage regulator to output a requested voltage]. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Brown, McCune and Suryanarayana together because they directed to regulate the voltage to the circuit. Suryanarayana’s disclosing of the signal comprises a voltage identification signal which identifies a requested voltage output of the voltage regulator would allow Brown in view of McCune to increase the efficiency by varying the output voltage based on the voltage identification signal. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 12 - 21 are rejected under 35 U.S.C. 103 as being unpatentable over Brown et al (US Publication 20130249505 A1) and in view of Suryanarayana (US Publication 20220291732 A1) and in further view of McCune (US Publication 20140103889 A1). Regarding claim 12, Brown and Suryanarayana together discloses this claim as set forth in the previous office action except the amended limitation “wherein when the signal indicates the processor transitions from the active state to the idle state, the controller is to turn off the switch to isolate the bulk capacitor and maintain charge on the bulk capacitor to prevent discharge due to system on a chip (SoC) leakage current during the idle state, and wherein the maintained charge is reused when the processor transitions back to the active state”. In the same field, McCune discloses the amended limitation “wherein when the signal indicates the processor transitions from the active state to the idle state, the controller is to turn off the switch to isolate the bulk capacitor and maintain charge on the bulk capacitor to prevent discharge due to system on a chip (SoC) leakage current during the idle state [inactive state] [0024: When the DC-DC converter 500 is in its operating state (FIG. 5A), the switch 504 remains closed and the linear regulator 502 operates to produce a regulated output voltage Vout, similar to as in a conventional linear regulator. However, upon a detected or expected large and abrupt decrease in load current (or based on some other external command independent of load conditions), the switch 504 is opened (FIG. 5B), isolating the output capacitor 506 and allowing the DC-DC converter 500 to transition rapidly to a disabled state][0020: a large and abrupt decrease in load current corresponds to a change of the load 212 from an active state to an inactive state][Claim 3: a shunt switch coupled across said capacitor configured to force an output voltage across the load to zero volts or substantially zero volts upon or as power delivery to the load is removed] [Claim 7: disabling the DC-DC converter includes preventing charge stored in an output capacitor of the DC-DC converter from discharging through the load as the DC-DC converter is disabled] (prevent discharge of the bulk capacitor via the power output rail due to leakage current in the load circuit), and wherein the maintained charge is reused when the processor transitions back to the active state [abstract and 0006: Residual energy stored in the electric field of the output capacitor and/or the magnetic field of the inductor at the time the load is next reactivated is available to hasten transition back to the operating state]. It would have been obvious before the effective filing date of the claimed invention to combine the teachings of Brown and Suryanarayana together for the same reasons as set forth in the previous office action. It would have further been obvious to combine the teachings of McCune into the disclosure of Brown and Suryanarayana for the same reasons as disclosed above in claim 1. Regarding claims 13 and 14, Brown and Suryanarayana together disclose these claims as set forth in the previous office action. Regarding claim 15, this claim is rejected for the same reasons as set forth in claim 12. Regarding claims 16-21, Brown and Suryanarayana together disclose these claims as set forth in the previous office action. Response to Arguments Applicant’s arguments filed on 05/20/2026 have been fully considered but are moot in view of new ground(s) of rejection because the arguments do not apply to any of the references being used in the current rejection. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). Examiner's note: Examiner has cited particular paragraphs and columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner (see MPEP § 2123). Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHIL K NGUYEN whose telephone number is (571)270-3356. The examiner can normally be reached 9:30 a.m - 5 p.m. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at (571)270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PHIL K NGUYEN/ Primary Examiner, Art Unit 2176
Read full office action

Prosecution Timeline

Dec 29, 2022
Application Filed
Mar 09, 2023
Response after Non-Final Action
Feb 25, 2026
Non-Final Rejection mailed — §103
May 20, 2026
Response Filed
Aug 17, 2026
Final Rejection mailed — §103
Aug 28, 2026
Interview Requested
Sep 08, 2026
Applicant Interview (Telephonic)
Sep 08, 2026
Examiner Interview Summary

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12743122
CIRCUITRY AND METHOD FOR QUANTIZATION ERROR CORRECTION FOR TIME SYNCHRONIZATION
2y 9m to grant Granted Sep 22, 2026
Patent 12737029
PROCESSORS HAVING CORE CONTROL CIRCUITS TO CONTROL CORE TRANSITIONS BETWEEN LOW POWER MODES AND RELATED METHODS
2y 6m to grant Granted Sep 15, 2026
Patent 12737021
CALIBRATION OF RESOURCE SERVER POWER ALLOCATIONS WITHIN A DATA STORAGE DEVICE USING CONFORMAL PREDICTIONS
1y 10m to grant Granted Sep 15, 2026
Patent 12724449
ASYNCHRONOUS ASIC
2y 1m to grant Granted Sep 01, 2026
Patent 12699432
CLOCK PULSE MANAGEMENT TO REDUCE PEAK POWER LEVELS
2y 7m to grant Granted Aug 04, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
97%
With Interview (+14.2%)
2y 8m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 549 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month