DETAILED ACTION Claims 1-21 are pending. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 – 10 are rejected under AIA 35 U.S.C. 102 (a)(1) as being anticipated by Brown et al (US Publication 20130249505 A1 ). Regarding claim 1, Brown discloses a n apparatus [Fig s . 2 and 9 ] , comprising: a voltage regulator [voltage regulator] comprising a power output rail and a path, wherein the path is coupled to the power output rail and ground, and wherein the path comprises a switch and a capacitor [switch transistor , capacitor] ; and a controller of the voltage regulator [controller] , wherein the controller is to receive a signal from a circuit [load circuit] which indicates whether the circuit is in an active state or an idle state, the power output rail is to provide power to the circuit, and the controller is to turn off the switch when the signal indicates the circuit transitions from the active state to the idle state [0010: The voltage regulator further includes a switched output filter for filtering the switching voltage and generating an output voltage, wherein the switched output filter comprises a plurality of capacitors that are selectively connected and included within the switched output filter. The voltage regulator further includes a mode controller, wherein the mode controller is operative to disconnect at least one of the plurality of capacitors ] [0011-0013] [0030-0031] [0075: When the load is inactive , or operating in a low-power condition, it is desirable to rapidly reduce the input voltage (that is, V.sub.out of the converter) to a low value V.sub.min, close to 0 , to minimize power consumption. To accomplish this, for an embodiment, the transistor Q.sub.CS is turned off ] . Regarding claim 2, Brown discloses t he apparatus of claim 1, wherein: when the switch is turned on, a voltage of one side of the capacitor is at ground; and when the switch is turned off, the voltage of the one side of the capacitor is floated [0010: disconnecting causes the at least one of the plurality of capacitors to electrically float ] [0011-0013] [0042] [0068-0069] . Regarding claim 3, Brown discloses t he apparatus of claim 1, wherein: the capacitor is one of a plurality of capacitors; and each capacitor of the plurality of capacitors is coupled to the power output rail and ground via a respective path and each respective path comprises a respective switch ( Fig. 5, [0011-0013 ], [ 0042 ], [ 0068-0069]: plurality of capacitor and respective switch ) . Regarding claim 4, Brown discloses t he apparatus of claim 1, further comprising one or more decoupling capacitors coupled to the power output rail [0010: disconnecting causes the at least one of the plurality of capacitors to electrically float ] [0011-0013] [0042] [0068-0069] . Regarding claim 5 , Brown discloses t he apparatus of claim 1, wherein: the voltage regulator is a switching voltage regulator; and when the signal indicates the circuit transitions from the idle state to the active state, the controller is to start to switch the voltage regulator to increase a voltage of the power output rail, and the controller is to turn on the switch when the controller senses that a voltage of the power output rail has increased above a threshold [0013, 0040, 0069, 0071-0072, 0075: turn on switch and reconnect capacitors based on voltage threshold] . Regarding claim 6, Brown discloses t he apparatus of claim 1, wherein the controller is to assert a power good signal to the circuit which indicates the power output rail is ready for use by the circuit, and the power good signal is delayed until after the controller turns on the switch [0007, 0031, 0045-0046,0064: switching out a PSM capacitor when changing the regulated output voltage from a first value to a second value, until a desired regulated output voltage is obtained ] . Regarding claim 7 , Brown discloses t he apparatus of claim 1, wherein when the signal indicates the circuit transitions from the active state to the idle state, the controller is to turn off the switch during a present switching cycle ( [0010-0013] [0030-0031] [0075]: When the load is inactive, turn off transistor). Regarding claim 8 , Brown discloses t he apparatus of claim 7, wherein when the signal indicates the circuit transitions from the active state to the idle state, the controller is to complete the present switching cycle before it is to stop switching the voltage regulator [ 0033, 0038, 0052, 0057: duty cycle] Regarding claim 9, Brown discloses t he apparatus of claim 1, wherein the switch comprises an n-type transistor between the capacitor and ground [0042: NMOS] . Regarding claim 10, Brown discloses apparatus of claim 1, wherein the switch comprises a p-type transistor between the capacitor and the power output rail [0032 , 0075: BJT, FET, CMOS ] . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 11-21 are rejected under 35 U.S.C. 103 as being unpatentable over Brown et al (US Publication 20130249505 A1 ) and in view of Suryanarayana (US Publication 20220291732 A1). Regarding claim 11, Brown does not explicitly disclose wherein the signal comprises a voltage identification signal which identifies a requested voltage output of the voltage regulator. Suryanarayana discloses the signal comprises a voltage identification signal which identifies a requested voltage output of the voltage regulator [Claim 10: the control circuit is to encode an 8-bit voltage identifier code for a first voltage into an encoded value and send the encoded value to the voltage regulator to cause the voltage regulator to output a requested voltag e]. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Brown and Suryanarayana together because they both directed to regulate the voltage to the circuit. Suryanarayana ’s disclosing of the signal comprises a voltage identification signal which identifies a requested voltage output of the voltage regulator would allow Brown to increase the efficiency by varying the output voltage based on the voltage identification signal. Regarding claim 12, Brown discloses this claim for the same reasons as set forth in claim 1 above except : (1) a memory to store instructions; and a processor coupled to the memory and (2) the load circuit is being a processor. In the same field, Suryanarayana discloses an apparatus comprises (1) a memory to store instructions; and a processor coupled to the memory [Claim 19: A system comprising: a voltage regulator to provide at least one voltage to a processor, the voltage regulator comprising at least one register; a non-volatile storage coupled to the processor to store firmware, the firmware comprising parameter information for the voltage regulator] . and (2) the load circuit is being a processor [Claim 19: processor] . Additionally, Suryanarayana discloses controlling the voltage regulator to output a desire voltage based on the performance state of the processor [claim 1: determine a performance state for at least one of the first core or the second core ][claim 2: a control circuit to generate a message based at least in part on the parameter information, the message to cause the voltage regulator to output a voltage to enable the at least one of the first core or the second core to operate at the performance state. ]. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Brown and Suryanarayana together because they both directed to regulate the voltage to the circuit. Suryanarayana ’s disclosing of the memory to store instructions; and a processor coupled to the memory and controlling the voltage regulator output the desire voltage to the processor would allow Brown to specifically achieve power saving for the processor by regulating the voltage to the processor based on its performance state. Regarding claim 13, Brown and Suryanarayana disclose t he apparatus of claim 12, wherein the processor is to execute the instructions to wait to receive a power good signal from the controller which indicates the switch has transitioned from being turned off to being turned on, before the processor resumes operations in the active state (Brown[0007, 0031, 0045-0046,0064: switching out a PSM capacitor when changing the regulated output voltage from a first value to a second value, until a desired regulated output voltage is obtained ]) ( Suryanarayana , claims 1,2 and 19) . Regarding claim 14 , Brown and Suryanarayana disclose t he apparatus of claim 13, wherein the processor is to receive the power good signal after a delay period has passed since the switch has transitioned from being off to being on (Brown[0007, 0031, 0045-0046,0064: switching out a PSM capacitor when changing the regulated output voltage from a first value to a second value, until a desired regulated output voltage is obtained ]) ( Suryanarayana , claims 1,2 and 19). Regarding claim 15, Brown and Suryanarayana disclose this claim for the same reasons as set forth in claim 12 above. Brown also discloses the load is a system on a chip (SoC) [Fig. 9 and 0074]. Regarding claim 16, Brown and Suryanarayana disclose t he apparatus of claim 15, wherein when the signal indicates the SoC transitions from the active state to the idle state, the microcontroller is to wait until the voltage regulator completes a present switching cycle before the microcontroller stops the switching of the voltage regulator (Brown [0033, 0038, 0052, 0057: duty cycle]) ( Suryanarayana , claims 1,2 and 19). Regarding claim 17, Brown and Suryanarayana disclose t he apparatus of claim 16, wherein when the signal indicates the SoC transitions from the active state to the idle state, the microcontroller is to prevent the discharge of the capacitor during the present switching cycle, before the stopping of the switching of the voltage regulator (Brown [0033, 0038, 0052, 0057: duty cycle]) ( Suryanarayana , claims 1,2 and 19). Regarding claim 18, Brown and Suryanarayana disclose t he apparatus of claim 15, wherein when the signal indicates the SoC transitions from the idle state to the active state, the microcontroller is to start switching of the voltage regulator, monitor a voltage of the power output rail and allow charging of the capacitor from the power output rail when the monitored voltage exceeds a threshold [Brown, 0013, 0040, 0069, 0071-0072, 0075: turn on switch and reconnect capacitors based on voltage threshold] ( Suryanarayana , claims 1,2 and 19). . Regarding claim 19, Brown and Suryanarayana disclose t he apparatus of claim 15, wherein: the voltage regulator comprises a power output rail; the capacitor is coupled to the power output rail and ground in a path; the path comprises a switch; and to prevent the discharge of the capacitor, the microcontroller is to turn off the switch (Brown, [0010-0013] [0030-0031] [0075: When the load is inactive, or operating in a low-power condition, it is desirable to rapidly reduce the input voltage (that is, V.sub.out of the converter) to a low value V.sub.min, close to 0, to minimize power consumption. To accomplish this, for an embodiment, the transistor Q.sub.CS is turned off] ( Suryanarayana , claims 1,2 and 19) . Regarding claim 20, Brown and Suryanarayana disclose t he apparatus of claim 19, wherein: when the microcontroller is to turn on the switch, the capacitor is to be charged by the power output rail; and when the microcontroller is to turn off the switch, the capacitor is to be isolated from charging from the power output rail (Brown, [0010-0013] [0030-0031] [0075: When the load is inactive, or operating in a low-power condition, it is desirable to rapidly reduce the input voltage (that is, V.sub.out of the converter) to a low value V.sub.min, close to 0, to minimize power consumption. To accomplish this, for an embodiment, the transistor Q.sub.CS is turned off] ( Suryanarayana , claims 1,2 and 19) . Regarding claim 21, Brown and Suryanarayana disclose t he apparatus of claim 19, wherein: when the microcontroller is to turn on the switch, a voltage of one side of the capacitor is at ground; and when the microcontroller is to turn off the switch, the voltage of the one side of the capacitor is floated (Brown, [0010: disconnecting causes the at least one of the plurality of capacitors to electrically float ] [0011-0013] [0042] [0068-0069]) ( Suryanarayana , claims 1,2 and 19) . Pertinent Arts The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cooper ( US 20170177068 A1 ) discloses t he method also includes receiving a signal indicating the processor has entered the low-power state, requesting a processor voltage regulator to transition to an off state [0056]. Taya ( US 20160065050 A1 ) discloses when the power source circuit 1 performs the operation described above, in the idle state, the PMOS transistor 41 and the NMOS transistor 42 of the switching circuit 40 are turned off; the PMOS transistor 71 of the series regulator 70 is turned off; and the PMOS transistor 81 of the switching portion 80 is turned off, so that the power source circuit 1 becomes the idle state [0061] . Shilimkar ( US 10228756 B2 ) discloses t he voltage controller 120 may turn off the buck converter when the first input signal VR_EN is received indicative of the platform load being in an idle state (or idle condition). At that time, an output voltage may be provided from the super-capacitor 176 while the buck converter 150 is turned off [Col. 5 lines 40-45] . Conclusion Examiner's note: Examiner has cited particular paragraphs and columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior a rt or disclosed by the examiner (see MPEP § 2123). Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT PHIL K NGUYEN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-3356 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT 9:30 a.m - 5 p.m . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. 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