DETAILED ACTION
The current Office Action is in response to the papers submitted 01/26/2026. Claims 1 – 16 and 19 - 22 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 – 16 and 19 - 22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claims 1, 11, and 19 disclose a memory of a first type having a plurality of memory channels, a memory of a second type having a plurality of links, and to homogenously interleave the plurality of memory channels with the plurality of links. The specification defines a memory as a holding place for data containing channels and gives an example of DDR memory as being memory in paragraph 0047. A channel is defined as a model for interprocess communication and synchronization via message passing and then discloses a memory channel can be interchanged with memory or DDR memory in paragraph 0048. A link is defined as any combination of hardware and/or software that provides a mechanism for data communication in paragraph 0049. Interleave is defined as the interspersing of data and for an interleave to be “homogenous” a range of addresses for two or more memories can be mapped to logical destinations that are included in a same interleave in paragraph 0052. Item 502 in figure 5 points to what appears to be a data path between items 540 and 520 and is labeled as “12 DDR Memory Channels” though. Item 562 in figure 5 is identified as homogenous interleave in paragraph 0060 while appearing in figure 5 to be a list of addresses. There is no indication what makes the list a homogenous interleave specifically. This fails certain tests of the In Re Wands, 858 F.2d 731,737, 8USPQ2d 1400, 1404 tests of undue experimentation as listed and described below.
(A) Breadth Of The Claims:
The claims disclose the act of homogenously interleaving memory channels with links. The definition of the memory channel make the use of a memory channel unclear. A memory channel can be interchanged with DDR memory according to paragraph 0048. This means then the claimed memory of a first type has a plurality of DDR memories. The term channel is also defined as a model in paragraph 0048. This makes the concept of interleaving a model unclear. The interspersing of data in an interleave does not appear to be the same as a mapping between physical and logical address as defined in paragraph 0052. Interspersing of data is an action where a mapping is not an action, an action might be based on a mapping but the mapping itself is not an action. The amendments add the concept of interleaving logical destinations spanning memory channels and links. The memory channel is interchangeable with memory while the link is defined as hardware and/or software that provides a mechanism for data communication. A mechanism for data communication is does not appear to be something that can accept a logical destination that is spanned across the link. A link is a mechanism to allow communication of information not specific logical destination.
(D) The Level Of One Of Ordinary Skill:
One of ordinary skill in the art would not readily know what the memory channels, links, and homogenously interleave are based on the definitions in the specification, the drawings, and the use of the terms in the claims. A memory channel is defined in the specification as a memory or DDR memory but is shown in figure 5 as being a data path by item 502 since it is depicted as a line with arrows pointing to 550 and 520. In the art one of ordinary skill would understand 502 to be a communication path where data is passed between 520 and 550 and not a memory itself such as DDR memory as defined in specification. This then would make the connection between 520 and 550 not enabled since simply having memory between 550 and 520 alone does not allow data communication as indicates by the double arrow line 502.
562 in figure 5 is identified as a homogenous interleave in the specification. Paragraph 0052 defines an interleave as an act of interspersing data and that a homogenous interleave is a mapping between addresses. A mapping itself is not interspersing of data. 562 alone does not intersperse data. 562 appears to be a grouping of storage locations. There is no indication of how memory channels, considered a DDR memories according to the specification, can be interleaved with links when interleaving is considered interspersing data. This makes the limitation of homogenously interleave items not enabled by one of ordinary skill since it is unclear what the limitation means.
The links are defined in paragraph 0049 as being software that provides a mechanism for data communications. Software is not a mechanism that provides for data communications. Data communications requires a data path to transfer data. The data path can be a wired or wireless path but is not software alone. A person of ordinary skill would not understand how to use software alone as the mechanism for data communication.
The term channel is referred to as a model for interprocess communication via message passing. This indicates a channel is not a physical construct that actually allows for the passing of data. A model is a conceptual idea of a device or idea. A model is not a real device that provides the functions of the conceptual idea. One of ordinary skill in the art would not understand how to use a model for item 502 to allow for the passage of data as indicated by the line with two arrows that item 502 points to.
A homogenous interleave is defined as a mapping between multiple memories to logical destinations that are included in a same interleave. An interleave is defined as the act of interspersing data as indicated previously. There is no clear direction provided how addresses can be mapped to logical destinations in an act of interspersing data. A mapping of addresses in the art if general mapped to other addresses not to a process of transferring data which is what interspersing of data is. The amendments to the claims fail to overcome the enablement issues.
The amendments add the concept of interleaving logical destinations spanning memory channels and links. The memory channel is interchangeable with memory while the link is defined as hardware and/or software that provides a mechanism for data communication. A mechanism for data communication is does not appear to be something that can accept a logical destination that is spanned across the link. A link is a mechanism to allow communication of information not specific logical destination. One of ordinary skill in the art would not understand how a logical destination could span links as defined in the specification in an interleave fashion.
(F) The Amount Of Direction Provided By The Inventor:
The inventor has failed to provide sufficient direction to explain what exactly the links, memory channels, and homogenously interleaving are meant to be and used. The specification defines the memory channels as being memory itself. This makes the representation of memory channels 502 in figure 5 unclear since item 502 appears to be a communication path since it is a line with two arrows. This is how a communication path is depicted in the art generally. Memories are usually depicted as square or rectangular items that communications are connected to.
A channel is defined as being a model for interprocess communication and synchronization via message passing. This shows the channel is not the actual device that provides for the passing of data but is actually a model representation of what the actual device is that provides for the passing of data. There is a lack of direction how a model can be depicted as being a real device such as item 502 in figure 5 that actually transmits data between multiple devices.
The links are disclosed in the specification as being software. There is no direction provided by the inventor how software alone can be a mechanism for data communication. Software might direct how communication is performed but a communication path is what actually provides the mechanism for the data communication.
Item 562 is identified as a homogenous interleave in the specification and appears as a grouping of memory devices or locations in figure 5. The specification though defines an interleave as an action of interspersing data. The act of interspersing data is not the same as a grouping of memory devices or locations. The group 562 does not appear to be a map also. There is no linking or association of one item to another item in the grouping 562. There is a linking arrow linking 562 and 564 to each other it appears in figure 5. However, this is not labeled or indicated as the homogeneous interleave, only item 562 is identified as a homogenous interleave. There is no direction provided by the applicant where the mapping is in the homogenous interleave or homogenously interleave process. The amendments to the claims fail to overcome the enablement issues.
The amendments add the concept of interleaving logical destinations spanning memory channels and links. The memory channel is interchangeable with memory while the link is defined as hardware and/or software that provides a mechanism for data communication. A mechanism for data communication is does not appear to be something that can accept a logical destination that is spanned across the link. A link is a mechanism to allow communication of information not specific logical destination. There is a lack of support indicating how links that are mechanisms for data communication can have logical destinations spanned across them in an interleave fashion.
(H) The Quantity Of Experimentation Needed To Make Or Use The Invention Based On The Content Of The Disclosure:
Due to the multiple issues listed above it would require an undo amount of experimentation to make and use the invention as claimed. It is unclear what the memory channels, links, a homogenously interleave process is, and how memory channels and links can be homogenously interleaved. The amendments to the claims fail to overcome the enablement issues.
All remaining claims are rejected for being dependent on a rejected base claim.
Claim 1 – 16 and 19 - 22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 11, and 19 disclose memory channels, links, homogenously interleave memory channels with links. As indicated above, the specification fails to sufficiently describe what memory channels and links are, what does it mean to have something interleaved, what is homogenously interleaving, and how memory channels and links can be interleaved. The specification discloses conflicting definitions for the terms in the claims and how they are used in the claims and shown in the drawings. This makes the limitations of memory channels, links, homogenously interleave memory channels with links indefinite since it is unclear what the terms are exactly and how they are used. The amendments to the claims fail to overcome the indefinite issues with the claims.
Claims 1, 11, and 19 disclose an address map that defines an interleave of logical destinations spanning the memory channels and the links. The links are a mechanism for data communications. There is no indication how the address defines an interleave of logical destinations that span the links. The logical destinations are a logical storing location in memory. The links are the mechanisms that the system uses to perform data communication such as data lines/paths. There is no indication what is meant by interleaving logical destinations spanning the links.
All remaining claims are rejected for being dependent on a rejected base claim and/or containing similar limitations rejected above.
Examiner’s Note
Due to the numerous inconsistencies identified above between the current claims and original specification and drawings a proper scope of the claims cannot be determined at this time. The lack of any prior art rejections is not to be taken as any indication of patentability; it is a result of the indefiniteness of the scope of the invention. Specifically, it is unclear what memory channels and links are, what does it mean to have something interleaved, what is homogenously interleaving, and how memory channels and links can be interleaved. The Applicant is asked to make sure any future amendments to the claims put the claims in better form with regard to what is specifically disclosed in the original specification and drawings.
Response to Arguments
Applicant's arguments filed 01/26/2026 have been fully considered but they are not persuasive.
The applicant argues on pages 8 – 9 that the specification provides proper support for all subject matter of the claims. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The arguments fail to properly explain how the claim limitations are not taught by the prior art other than saying they do not. There are no specific examples or explanation detailing how the prior art is different from the current claim limitations. Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references. The rejections contain citations and explanations detailing how the prior art teaches the current claim limitations.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER D BIRKHIMER whose telephone number is (571)270-1178. The examiner can normally be reached 8-5 Hoteling.
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/Christopher D Birkhimer/Primary Examiner, Art Unit 2136
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