DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/27/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
This office action is in response to the amendment filed on 06/22/2026. Claims 1-24 are pending. Claims 1, 4, 8-9, 12, and 16-24 are amended.
Response to Arguments
Applicant's arguments filed 06/22/2026 have been fully considered but they are not persuasive.
On pages 7-8 of the Remarks, Applicant argues:
Henry '03 describes that to use the "extended registers specifier" one has to use an "escape tag" opcode first. Then if there is an escape code a determination is made of if there is an extended prefix. Then a micro instruction is replace with an extended operand address. All of that has to happen to use extended registers. There is not an instance of a single instruction that allows for a prefix that provides a plurality of bits for a register location. Combining with the other Henry still requires all of this setup. As such, multiple instructions are required AND the decoder is not decoding the instruction to identify the operand location based using the MSBs from the prefix. Rather, a uop is replaced.
However, this argument is not persuasive because it does not consider how the references are combined. The office action modifies the instructions of Henry ’14 to include the prefix for identifying extended registers taught by Henry ’03, the office action does not rely on the escape prefix of Henry ’03. In the combination, the decoder/translator of Henry ’14 would decode the modified instructions, which would include an instance of a single instruction including the extended prefix of Henry ’03 having a payload that provides most significant bits to identify the first source operand location.
Claim Objections
Claims 2-4, 7, 9-12, 15, 17-20, and 23 are objected to because of the following informalities:
Claim 9 line 2- insert --a-- after “an instance of” to improve readability
Claim 17 line 2- insert --a-- after “an instance of” to improve readability
Claims 2-4, 10-12, and 18-20- insert --location-- after “the first source operand” to improve clarity as the independent claim introduces “a first source operand location”
Claims 2-3, 7, 10-11, 15, 18-19, and 23- insert --location-- after “the destination operand” to improve clarity as the independent claim introduces “a destination operand location”
Claim 12- delete “each of” in line 2
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 20 and 24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 20 recites “each of the first and second source operands”. There is insufficient antecedent basis for this limitation as the claim does not introduce a second source operand. For purposes of examination, this limitation will be interpreted as any second source operand.
Claim 24 recites “wherein bit position 20 of a payload of the prefix”. It is unclear whether this payload of the prefix is the same as the payload of the prefix introduced in claim 17 or if they are different. For purposes of examination, this limitation will be interpreted as the same payload introduced in claim 17 having a bit position 20.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 9-24 are rejected under 35 U.S.C. 103 as being unpatentable over Henry ’14 US 2014/0122847 in view of Henry ’03 US 2003/0188130 (cited on 03/01/2024 IDS).
Regarding claim 1, Henry ’14 teaches:
1. An apparatus comprising:
decoder circuitry to decode an instance of single instruction ([0161]: the conditional load instruction is a single instruction that is decoded by the instruction translator 204, see [0075] and Fig. 2; alternatively, [0209] discloses a conditional store instruction, which is a single instruction that is decoded by the instruction translator 204), the instance of the single instruction to at least include one or more fields to identify a first source operand location ([0161]: the conditional load instruction includes a field that specifies a base register RN, which identifies a memory address (i.e., a first source operand location); alternatively, [0209] discloses the conditional store instruction includes a field that specifies a data register, which identifies a first source operand location), one or more fields to identify a destination operand location ([0166]: the conditional load instruction includes a field that specifies a destination register RT (i.e., a destination operand location); alternatively, [0209] discloses the conditional store instruction includes a field that specifies a base register RN, which identifies a memory address (i.e., a destination operand location)), and an opcode to indicate execution circuitry is to conditionally move data from the identified first source operand location to the identified destination operand location based at least in part on evaluation of a condition code ([0161]: the opcode LDR<C> (see Fig. 11) indicates that the load unit (which executes the load instruction, see [0177]-[0179]) will conditionally move data from the memory address to the destination register based on evaluation of the condition <C> (i.e., a condition code); alternatively, [0214] discloses the opcode STR<C> (see Fig. 15) indicates that the store unit (which executes the store instruction, see [0189]-[0191]) will conditionally move data from the data register to the memory address based on evaluation of the condition <C> (i.e., a condition code)); and
the execution circuitry to execute the decoded instance of the single instruction according to the opcode ([0177]-[0179] the load unit is execution circuitry to execute the decoded conditional load instruction by executing its microinstructions; alternatively, [0189]-[0191] discloses the store unit, which is execution circuitry to execute the decoded conditional store instruction by executing its microinstructions).
Henry ’14 does not teach:
the instruction to include a prefix,
wherein a payload of the prefix is to provide most significant bits to identify the first source operand location
However, Henry ’03 teaches an instruction format including a prefix, wherein a payload of the prefix is to provide most significant bits to identify additional operand registers ([0042]: the extended prefix 305 payload specifies a plurality of source and destination registers by providing upper register address bits (i.e., most significant bits) that are combined with lower register address bits to identify the extended registers).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the instructions of Henry ’14 to include a prefix for identifying extended registers as taught by Henry ’03 such that the conditional load/store instructions of the combination may use the prefix to identify a first or second source operand register. One of ordinary skill in the art would have been motivated to make this modification to allow programmers to specify additional register beyond those provide by an existing instruction set architecture (Henry [0036]) which would improve flexibility.
Regarding claim 2, Henry ’14 in view of Henry ’03 teaches:
2. The apparatus of claim 1, wherein the first source operand is a memory location and the destination operand is a register (Henry ’14 [0161] and [0166]: the first source operand location identified by the base register is a memory address/location and the destination is a register).
Regarding claim 3, Henry ’14 in view of Henry ’03 teaches:
3. The apparatus of claim 1, wherein the first source operand is a register and the destination operand is a memory location (Henry ’14 [0209]: the first source operand location is a data register and the destination operand location identified by the base register is a memory address/location).
Regarding claim 4, Henry ’14 in view of Henry ’03 teaches:
4. The apparatus of claim 1, wherein the prefix is to include two bits for the first source operand to be used as most significant bits of a register identifier (the prefix of the combination would include two bits for each of its source operands to be used as most significant bits of a register identifier as Henry ’03 [0042] discloses that the extended prefix 305 may include upper register address bits (i.e., two bits to be used most significant bits of a register identifier) which are combined with lower register address bits to specify each extended register).
Regarding claim 5, Henry ’14 in view of Henry ’03 teaches:
5. The apparatus of claim 1, wherein the condition code is to be provided by the opcode (Henry ’14 [0161] and Fig. 11: the opcode LDR <C> provides the condition code <C>).
Regarding claim 6, Henry ’14 in view of Henry ’03 teaches:
6. The apparatus of claim 1, wherein memory faults are to be suppressed when the evaluation of the condition code is false (Henry ’14 [0182]-[0183] discloses that a page fault/memory fault is not generated (i.e., suppressed) at step 1234 when the condition is not satisfied (i.e., when the evaluation of the condition code is false)).
Regarding claim 7, Henry ’14 in view of Henry ’03 teaches:
7. The apparatus of claim 1, wherein the instance of the single instruction is to identify a second source and the destination operand is a new data destination (Henry ’14 [0161] and [0166]: the conditional load instruction may specify an immediate value to identify an offset/second source and the destination operand that specifies RT as the destination register is a new data destination in the sense that it is different from the source operand).
Regarding claim 9, Henry ’14 teaches:
9. A system comprising:
memory to store at least an instance of single instruction ([0051]: instructions are fetched from system memory);
decoder circuitry to decode the instance of the single instruction ([0161]: the conditional load instruction is a single instruction that is decoded by the instruction translator 204, see [0075] and Fig. 2; alternatively, [0209] discloses a conditional store instruction, which is a single instruction that is decoded by the instruction translator 204), the instance of the single instruction to at least include a prefix, one or more fields to identify a first source operand location ([0161]: the conditional load instruction includes a field that specifies a base register RN, which identifies a memory address (i.e., a first source operand location); alternatively, [0209] discloses the conditional store instruction includes a field that specifies a data register, which identifies a first source operand location), one or more fields to identify a destination operand location ([0166]: the conditional load instruction includes a field that specifies a destination register RT (i.e., a destination operand location); alternatively, [0209] discloses the conditional store instruction includes a field that specifies a base register RN, which identifies a memory address (i.e., a destination operand location)), and an opcode to indicate execution circuitry is to conditionally move data from the identified first source operand location to the identified destination operand location based at least in part on evaluation of a condition code, wherein a payload of the prefix is to provide most significant bits to identify the first source operand location ([0161]: the opcode LDR<C> (see Fig. 11) indicates that the load unit (which executes the load instruction, see [0177]-[0179]) will conditionally move data from the memory address to the destination register based on evaluation of the condition <C> (i.e., a condition code); alternatively, [0214] discloses the opcode STR<C> (see Fig. 15) indicates that the store unit (which executes the store instruction, see [0189]-[0191]) will conditionally move data from the data register to the memory address based on evaluation of the condition <C> (i.e., a condition code)); and
the execution circuitry to execute the decoded instance of the single instruction according to the opcode ([0177]-[0179] the load unit is execution circuitry to execute the decoded conditional load instruction by executing its microinstructions; alternatively, [0189]-[0191] discloses the store unit, which is execution circuitry to execute the decoded conditional store instruction by executing its microinstructions).
Henry ’14 does not teach:
the instruction to include a prefix,
wherein a payload of the prefix is to provide most significant bits to identify the first source operand location
However, Henry ’03 teaches an instruction format including a prefix, wherein a payload of the prefix is to provide most significant bits to identify additional operand registers ([0042]: the extended prefix 305 payload specifies a plurality of source and destination registers by providing upper register address bits (i.e., most significant bits) that are combined with lower register address bits to identify the extended registers).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the instructions of Henry ’14 to include a prefix for identifying extended registers as taught by Henry ’03 such that the conditional load/store instructions of the combination may use the prefix to identify a first or second source operand register. One of ordinary skill in the art would have been motivated to make this modification to allow programmers to specify additional register beyond those provide by an existing instruction set architecture (Henry [0036]) which would improve flexibility.
Regarding claim 10, Henry ’14 in view of Henry ’03 teaches:
10. The system of claim 9, wherein the first source operand is a memory location and the destination operand is a register (Henry ’14 [0161] and [0166]: the first source operand location identified by the base register is a memory address/location and the destination is a register).
Regarding claim 11, Henry ’14 in view of Henry ’03 teaches:
11. The system of claim 9, wherein the first source operand is a register and the destination operand is a memory location (Henry ’14 [0209]: the first source operand location is a data register and the destination operand location identified by the base register is a memory address/location).
Regarding claim 12, Henry ’14 in view of Henry ’03 teaches:
12. The system of claim 9, wherein the prefix is to include two bits for each of the first source operand to be used as most significant bits of a register identifier (the prefix of the combination would include two bits for each of its source operands to be used as most significant bits of a register identifier as Henry ’03 [0042] discloses that the extended prefix 305 may include upper register address bits (i.e., two bits to be used most significant bits of a register identifier) which are combined with lower register address bits to specify each extended register).
Regarding claim 13, Henry ’14 in view of Henry ’03 teaches:
13. The system of claim 9, wherein the condition code is to be provided by the opcode (Henry ’14 [0161] and Fig. 11: the opcode LDR <C> provides the condition code <C>).
Regarding claim 14, Henry ’14 in view of Henry ’03 teaches:
14. The system of claim 9, wherein memory faults are to be suppressed when the evaluation of the condition code is false (Henry ’14 [0182]-[0183] discloses that a page fault/memory fault is not generated (i.e., suppressed) at step 1234 when the condition is not satisfied (i.e., when the evaluation of the condition code is false)).
Regarding claim 15, Henry ’14 in view of Henry ’03 teaches:
15. The system of claim 9, wherein the instance of the single instruction is to identify a second source and the destination operand is a new data destination (Henry ’14 [0161] and [0166]: the conditional load instruction may specify an immediate value to identify an offset/second source and the destination operand that specifies RT as the destination register is a new data destination in the sense that it is different from the source operand).
Regarding claim 16, Henry ’14 in view of Henry ’03 teaches:
16. The system of claim 15, wherein bit position 20 of the payload of the prefix is to be set to 1 (Henry ’03 [0042] discloses that the prefix may be a plurality of bits, thus any prefix of the combination using a plurality of 20 or more bits would include a bit position 20 set to 1 for a particular extended register encoding).
Regarding claim 17, Henry ’14 (US20140122847) teaches:
17. An apparatus comprising:
translating an instance of single instruction of a first instruction set architecture to one or more instructions of a second instruction set architecture ([0116]: the hardware instruction translator translates instructions of an x86 ISA or ARM ISA (i.e., a first instruction set architecture) to microinstructions of a microinstruction set (i.e., a second instruction set architecture); the conditional load instruction, see [0161], or the conditional store instruction, see [0209], is a single instruction of a first instruction set architecture and the microinstructions they are translated to are one or more instructions of a second instruction set architecture), the instance of the single instruction to at least include one or more fields to identify a first source operand location ([0161]: the conditional load instruction includes a field that specifies a base register RN, which identifies a memory address (i.e., a first source operand location); alternatively, [0209] discloses the conditional store instruction includes a field that specifies a data register, which identifies a first source operand location), one or more fields to identify a destination operand location ([0166]: the conditional load instruction includes a field that specifies a destination register RT (i.e., a destination operand location); alternatively, [0209] discloses the conditional store instruction includes a field that specifies a base register RN, which identifies a memory address (i.e., a destination operand location)), and an opcode to indicate execution circuitry is to conditionally move data from the identified first source operand location to the identified destination operand location based at least in part on evaluation of a condition code ([0161]: the opcode LDR<C> (see Fig. 11) indicates that the load unit (which executes the load instruction, see [0177]-[0179]) will conditionally move data from the memory address to the destination register based on evaluation of the condition <C> (i.e., a condition code); alternatively, [0214] discloses the opcode STR<C> (see Fig. 15) indicates that the store unit (which executes the store instruction, see [0189]-[0191]) will conditionally move data from the data register to the memory address based on evaluation of the condition <C> (i.e., a condition code));
decoding the one or more instructions of the second instruction set architecture ([0135]: the control logic 1002A (or control logic 1002B, see [0142]) decodes the microinstruction (i.e., the instructions of the second instruction set architecture)); and
executing the decoded one or more instructions of the second instruction set architecture according to the opcode of the instance of the single instruction of the first instruction set architecture ([0166]: the LD.CC and LEA.CC microinstructions are executed according to the opcode of the conditional load instruction of the first instruction set architecture that they were translated from; alternatively, [0214] discloses the ST.FUSED.CC and LEA.CC microinstructions are executed according to the opcode of the conditional store instruction of the first instruction set architecture that they were translated from).
Henry ’14 does not teach:
the instruction to include a prefix,
wherein a payload of the prefix is to provide most significant bits to identify the first source operand location
However, Henry ’03 teaches an instruction format including a prefix, wherein a payload of the prefix is to provide most significant bits to identify additional operand registers ([0042]: the extended prefix 305 payload specifies a plurality of source and destination registers by providing upper register address bits (i.e., most significant bits) that are combined with lower register address bits to identify the extended registers).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the instructions of Henry ’14 to include a prefix for identifying extended registers as taught by Henry ’03 such that the conditional load/store instructions of the combination may use the prefix to identify a first or second source operand register. One of ordinary skill in the art would have been motivated to make this modification to allow programmers to specify additional register beyond those provide by an existing instruction set architecture (Henry [0036]) which would improve flexibility.
Regarding claim 18, Henry ’14 in view of Henry ’03 teaches:
18. The apparatus of claim 17, wherein the first source operand is a memory location and the destination operand is a register (Henry ’14 [0161] and [0166]: the first source operand location identified by the base register is a memory address/location and the destination is a register).
Regarding claim 19, Henry ’14 in view of Henry ’03 teaches:
19. The apparatus of claim 17, wherein the first source operand is a register and the destination operand is a memory location (Henry ’14 [0209]: the first source operand location is a data register and the destination operand location identified by the base register is a memory address/location).
Regarding claim 20, Henry ’14 in view of Henry ’03 teaches:
20. The apparatus of claim 17, wherein the prefix is to include two bits for each of the first and second source operands to be used as most significant bits of a register identifier (the prefix of the combination would include two bits for each of its source operands to be used as most significant bits of a register identifier as Henry ’03 [0042] discloses that the extended prefix 305 may include upper register address bits (i.e., two bits to be used most significant bits of a register identifier) which are combined with lower register address bits to specify each extended register).
Regarding claim 21, Henry ’14 in view of Henry ’03 teaches:
21. The apparatus of claim 17, wherein the condition code is to be provided by the opcode (Henry ’14 [0161] and Fig. 11: the opcode LDR <C> provides the condition code <C>).
Regarding claim 22, Henry ’14 in view of Henry ’03 teaches:
22. The apparatus of claim 17, wherein memory faults are to be suppressed when the evaluation of the condition code is false (Henry ’14 [0182]-[0183] discloses that a page fault/memory fault is not generated (i.e., suppressed) at step 1234 when the condition is not satisfied (i.e., when the evaluation of the condition code is false)).
Regarding claim 23, Henry ’14 in view of Henry ’03 teaches:
23. The apparatus of claim 17, wherein the instance of the single instruction is to identify a second source and the destination operand is a new data destination (Henry ’14 [0161] and [0166]: the conditional load instruction may specify an immediate value to identify an offset/second source and the destination operand that specifies RT as the destination register is a new data destination in the sense that it is different from the source operand).
Regarding claim 24, Henry ’14 in view of Henry ’03 teaches:
24. The apparatus of claim 23, wherein bit position 20 of a payload of the prefix is to be set to 1 (Henry ’03 [0042] discloses that the prefix may be a plurality of bits, thus any prefix of the combination using a plurality of 20 or more bits would include a bit position 20 set to 1 for a particular extended register encoding).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Henry ’14 US 2014/0122847 in view of Henry ’03 US 2003/0188130 and Plotnikov US 2019/0227798.
Regarding claim 8, Henry ’14 in view of Henry ’03 teaches:
8. The apparatus of claim 7, wherein a bit of a payload of the prefix is to be set to 1 (the prefix of the combination would include a bit position set to 1 for a particular extended register encoding).
Although Henry ’03 teaches an n-bit prefix, see [0036], Henry ’14 in view of Henry ’03 does not teach a prefix having a bit position 20.
However, Plotnikov teaches a 4-byte/32-bit prefix having a bit position 20, see [0204] and Fig. 15.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the prefix of Henry ’14 in view of Henry ’03 to be a 4-byte prefix as taught by Plotnikov such that bit position 20 of the prefix would be set to 1 for a particular extended register encoding. One of ordinary skill in the art would have been motivated to make this modification to enable encoding more registers in the prefix.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/KASIM ALLI/Examiner, Art Unit 2183 /JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183
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