DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1-20 are pending.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on 12/30/2022 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner.
Claim Objections
4. Claim 1 is objected to because of the following informalities: Line 3 states “IO interface” and should be replaced with “input/output (IO) interface”. Appropriate correction is required.
5. Claim 2 is objected to because of the following informalities: Line 2 states “ECC” and should be replaced with “error correction code (ECC)”. Appropriate correction is required.
6. Claim 8 is objected to because of the following informalities: Line 2 states “write first-in-first-out (FIFO)” and should be replaced with “ITPD” or “ITPDs”. Appropriate correction is required.
7. Claim 11 is objected to because of the following informalities: Line 3 states “IO interface” and should be replaced with “input/output (IO) interface”. Appropriate correction is required.
8. Claim 12 is objected to because of the following informalities: Line 2 states “ECC” and should be replaced with “error correction code (ECC)”. Appropriate correction is required.
9. Claim 17 is objected to because of the following informalities: Line 2 states “write first-in-first-out (FIFO)” and should be replaced with “ITPD” or “ITPDs”. Appropriate correction is required.
10. Claim 19 is objected to because of the following informalities: Line 3 states “IO interface” and should be replaced with “input/output (IO) interface”. Appropriate correction is required.
11. Claim 20 is objected to because of the following informalities: Line 2 states “ECC” and should be replaced with “error correction code (ECC)”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
12. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
13. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the respective memory controllers" in lines 12-13. There is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation "the memory controllers" in lines 12-13. There is insufficient antecedent basis for this limitation in the claim.
Claim 19 recites the limitation "the first memory controllers" in lines 13-14 and "the second memory controllers" in lines 23-24. There is insufficient antecedent basis for this limitation in the claim.
Claims 2-10, 12-18 and 20 are further rejected based on their dependency of claims 1, 11 and 19.
Related Prior Art
14. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
a. Srinivasan et al. (US Pub. No. 2022/0115047 A1 hereinafter “Srinivasan”) discloses an integrated circuit includes a first input/output lane comprising first external terminals and first driver circuits. The first driver circuits exchange signals with a first external device through the first external terminals as part of a first external interface. The first input/output lane is part of a sub-bank in an input/output bank that implements at least a part of the first external interface. The integrated circuit includes a second input/output lane comprising second external terminals and second driver circuits. The second driver circuits exchange signals with a second external device through the second external terminals as part of a second external interface. The second input/output lane is part of the sub-bank in the input/output bank that implements at least a part of the second external interface.
b. Manohar et al. (US Pub. No. 2010/0013517 A1 hereinafter “Manohar”) discloses asynchronous reconfigurable logic fabrics for integrated circuits and methods for designing asynchronous circuits to be implemented in the asynchronous reconfigurable logic fabrics.
c. Lacey et al. (US Patent No. 6,608,500 B1 hereinafter “Lacy”) discloses an apparatus comprising an input/output circuit and a programmable logic device. The input/output circuit may be configured to (i) connect to an end of a bus and (ii) operate in one or more modes in response to one or more control signals. The programmable logic device may be configured to generate said one or more control signals.
Allowable Subject Matter
15. Claims 1-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
The examiner finds that the prior art of record taken alone or in combination fails to teach and/or fairly suggest “A system, comprising:… wherein the IO interface comprises: a plurality of IO banks to implement a memory channel, wherein each IO bank of the plurality of IO banks comprises: a memory controller to control memory accesses of a memory device over the memory channel; and a plurality of physical layer and IOs circuits to provide connections between the memory controller and the memory device, wherein the memory channel is wider than the respective memory controllers, and each respective memory controller is to receive only a portion of data to be sent over the memory channel.”, in combination with other recited limitations in independent claim 1.
The examiner finds that the prior art of record taken alone or in combination fails to teach and/or fairly suggest “A system, comprising:… wherein the IO interface comprises: a plurality of IO banks to implement a memory channel, wherein each IO bank of the plurality of IO banks comprises: a memory controller to control memory accesses of a memory device over the memory channel; and a plurality of physical layer and IOs circuits to provide connections between the memory controller and the memory device, wherein each respective memory controller of the memory controllers is to receive all data sent over the memory channel.”, in combination with other recited limitations in independent claim 11.
The examiner finds that the prior art of record taken alone or in combination fails to teach and/or fairly suggest “A system, comprising:… wherein the IO interface comprises: a first plurality of IO banks to implement a first memory channel, wherein each IO bank of the first plurality of IO banks comprises: a first memory controller to control memory accesses of one or more memory devices over the first memory channel; and a first plurality of physical layer and IOs circuits to provide connections between the first memory controller and the one or more memory devices, wherein each respective first memory controller of the first memory controllers is to receive all data sent over the first memory channel; and a second plurality of IO banks to implement a second memory channel, wherein each IO bank of the second plurality of IO banks comprises: a second memory controller to control memory accesses of the one or more memory devices over the second memory channel; and a second plurality of physical layer and IOs circuits to provide connections between the second memory controller and the one or more memory devices, wherein each respective second memory controller of the second memory controllers is to receive all data sent over the second memory channel.”, in combination with other recited limitations in independent claim 19.
Dependent claims 2-10, 12-18 and 20 would be allowable based on their dependencies of independent claims 1, 11 and 19.
Conclusion
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R.I .Ill(c).
In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAYTON LEWIS-TAYLOR whose telephone number is (571) 2707754. The examiner can normally be reached on Monday through Thursday, 8AM TO 4PM, EASTERN TIME.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye, can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Dayton Lewis-Taylor/
Examiner, Art Unit 2181
Prosecution Insights