DETAILED ACTION
Response to Amendment
This action is responsive to the amendment filed on 7/9/2026. Claims 1-4, 6-14, 16-25 are pending and have been examined. Claims 1-3, 9, 11-13, 19 and 21-23 have been amended. Claims 5 and 15 have been canceled.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-4, 6-14 and 16-25 are objected to because of the following informalities:
In regard to claim 1, lines 6-7 amend the limitation to state “…comparison of data from the identified first source operand location to data from the identified second source operand location…” as to improve readability and clarity of the claim.
In regard to claim 1, lines 10-11 amend the limitation to state “…the source condition code…” as to improve readability and clarity of the claim.
In regard to claim 9, lines 2-3 amend the limitation to state “…data from the second source operand location is subtracted from data of the first source operand location…” as to improve readability and clarity of the claim.
In regard to claim 11, lines 6-7 amend the limitation to state “…comparison of data from the identified first source operand location to data from the identified second source operand location…” as to improve readability and clarity of the claim.
In regard to claim 11, line 12 amend the limitation to state “…the source condition code…” as to improve readability and clarity of the claim.
In regard to claim 19, lines 2-3 amend the limitation to state “…data from the second source operand location is subtracted from data of the first source operand location…” as to improve readability and clarity of the claim.
In regard to claim 21, lines 7-8 amend the limitation to state “…comparison of data from the identified first source operand location to data from the identified second source operand location …” as to improve readability and clarity of the claim.
In regard to claim 21, line 12 amend the limitation to state “…the source condition code…” as to improve readability and clarity of the claim.
Claims 2-4, 6-10, 12-14, 16-20 and 22-25 are dependent upon one or more claims above and therefore are similarly objected to for including the deficiencies of one or more claims above.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, 6-14 and 16-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In regard to claim 1, line 10 the limitation “the first source operand and the second source operand” lack clarity because the limitations lack proper antecedent basis as there is no prior recitation of “a first source operand and a second source operand”.
The examiner suggest the applicant amend the limitation to state 1) “…based on the comparison of data from the first source operand location and data from the second source operand location…” or 2) “…based on a comparison of a [[the]] first source operand and a [[the]] second source operand…”
Claims 11 and 21 are similarly rejected on the same basis as claim 1 above.
In regard to claim 4, line 2 the limitation “the first and second source operands” lack clarity because the limitations lack proper antecedent basis as there is no prior recitation of “a first source operand and a second source operand”. The examiner suggest correcting the issue by amending claim 1 as stated above.
Claims 14 and 24 are similarly rejected on the same basis as claim 4 above.
Claims 2-4, 6-10, 12-14, 16-20 and 22-25 are dependent upon one or more claims above and therefore are similarly rejected for including the deficiencies of one or more claims above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 8-13 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Combs, PGPUB No. 2013/0275723, Seal, PGPUB No. 2013/0097408 and further in view of Henry, PGPUB No. 2003/0188140 (cited on IDS filed on 7/27/2026).
In regard to claim 1, Combs discloses An apparatus (See Fig. 1) comprising: decoder circuitry to decode an instance of a single instruction ([0020-0021]) the instance of the single instruction to at least include a prefix, one or more fields to identify a first source operand location, one or more fields to identify a second source operand location, and an opcode ([0020-0025]: wherein instruction can include a prefix, one or more fields to identify one or more sources, and an opcode) to indicate execution circuitry is to conditionally perform a comparison of data from the identified first source operand location to the identified second source operand location based at least in part on an evaluation of a source condition code provided by the prefix ([0030-0033]: wherein an opcode can indicate a CMP instruction used for conditional execution based at least in part on an evaluation of a predicate condition specified by the prefix (See Fig. 2 and 7)) wherein when the source condition code is satisfied a flags register is to be updated based on a comparison of the first source operand and the second source operand and when the source condition is not satisfied the flags register is not set ([0028 and 0033]) wherein a payload of the prefix is to provide most significant bits to identify at least one of the first and second source operand locations (Figs. 2 and 5: wherein RXB bits in a VEX prefix are used to provide most significant bits to identify at least one of the first and second source operand locations) and execution circuitry to execute the decoded instance of the single instruction according to the opcode ([0021, 0024 and 0033])
Combs does not explicitly disclose opcode to indicate execution circuitry is to conditionally perform a comparison of data from the identified first source operand location to the identified second source operand location based at least in part on an evaluation of a source condition code nor wherein when the source condition code is satisfied a flags register is to be updated based on a comparison of the first source operand and the second source operand and when the source condition is not satisfied the flags register is to be set by a destination condition code provided by the prefix. Combs discloses a CMP instruction that can be performed conditionally, such that when a predicate condition is true arithmetic flags are updated and when the condition is false the flags are not updated. However, Combs does not disclose a conditional compare instruction that upon a predication condition being false using a condition code provided by the instruction to set the arithmetic flags.
Seal discloses opcode to indicate execution circuitry is to conditionally perform a comparison of data from the identified first source operand location to the identified second source operand location based at least in part on an evaluation of a source condition code ([0070-0071 and 0077]: wherein an opcode of CCMP instruction indicates processing circuitry is to conditionally perform a comparison of data from the first and second source operands based at least in part on evaluating a test condition code (Cond)(See Figs. 3A-B and 5)) wherein when the source condition code is satisfied a flags register is to be updated based on a comparison of the first source operand and the second source operand and when the source condition is not satisfied the flags register is to be set by a destination condition code provided by an immediate operand of instruction ([0070-0071] (See Figs.3A-B))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify instruction set of Combs, which includes conditional execution of compare instructions, to include a conditional compare instruction as taught in Seal. It would have been obvious to one of ordinary skill in the art because the conditional compare instruction allows for testing of a chained sequence of comparisons of different types and thus can be used more widely and is hence more easily usable by compilers (Seal [0016]). Furthermore, it would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (CCMP of Seal which upon a false condition updates a flags register with a failed condition code) for another (conditional compare of Combs which upon a false condition does not update flags register) to yield predictable results (performing a conditional compare operation that based on a condition code updates a flags register based on comparison result or failed condition code) (MPEP 2143, Example B).
The combination of Combs and Seal does not disclose a destination condition code provided by a prefix. The combination of Combs and Seal disclose using a prefix to provide a source condition code and a 4-bit immediate operand to provide a destination condition code. Thus, the combination does not disclose a prefix to provide both a source and destination condition code.
Henry discloses an extended prefix for conditional execution that provides a source condition code and includes spare bits which are unused (See Figs. 6-7 and [0050-0051)
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the conditional compare instruction of Combs and Seal, which includes source and destination condition codes, to utilize an extended prefix as taught in Henry to store both source and destination condition codes. It would have been obvious to one of ordinary skill in the art because using an extended prefix to store multiple condition codes used for conditional instruction execution can be used for added flexibility of the instruction by employing different condition code combinations (Henry [0042 and 0052]). Furthermore, it would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (storing a destination condition code in a prefix field of an instruction) for another (storing destination condition code in an immediate operand field of an instruction) to yield predictable results (performing a conditional compare instruction which includes an extended prefix to store both source and destination condition codes) (MPEP 2143, Example B).
Claim 11 is similarly rejected on the same basis as claim 1 above.
In regard to claim 2, the combination of Combs, Seal and Henry discloses The apparatus of claim 1 (see rejection of claim 1 above) wherein the first source operand location is a register. (Combs [0022-0023]|Seal [0071 and 0077-0078])
In regard to claim 3, the combination of Combs, Seal and Henry discloses The apparatus of claim 1 (see rejection of claim 1 above) wherein the first source operand location and second source operand location are registers. (Combs [0022-0023]: wherein first source and second source are registers |Seal [0071, 0077-0078])
Claim 13 is similarly rejected on the same basis as claim 3 above.
In regard to claim 8, the combination of Combs, Seal and Henry discloses The apparatus of claim 1 (see rejection of claim 1 above) wherein bit position 20 of a payload of the prefix is to be set to 1. (Combs: Fig. 5: wherein in byte 2 of VEX prefix (element 510) bit position 20 (e.g. bit 4 of byte 2) of prefix is set to 1 if unused)
Claim 18 is similarly rejected on the same basis as claim 8 above.
In regard to claim 9, the combination of Combs, Seal and Henry discloses The apparatus of claim 1 (see rejection of claim 1 above) wherein when the comparison is to be performed, data from the second source operand location is subtracted from the first source operand location and condition codes generated from the subtraction are to be stored in the flags register. (Combs [0033]|Seal [0071, 0082 and Fig. 5))
Claim 19 is similarly rejected on the same basis as claim 9 above.
In regard to claim 10, the combination of Combs, Seal and Henry discloses The apparatus of claim 1 (see rejection of claim 1 above) wherein the source condition code encodes a condition to test for. (Combs [0032-0033 and Fig. 7] |Seal [0070-0071|Henry [0050-0051 and 0056])
Claim 20 is similarly rejected on the same basis as claim 10 above.
In regard to claim 12, the combination of Combs, Seal and Henry discloses The system of claim 11 (see rejection of claim 11 above) wherein the first source operand location is a register and the second operand location is a memory location. (Combs [0022-0023])
Claim(s) 6-7 and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Combs, Seal, Henry and further in view of Dent, USPAT. No. 6,314,504.
In regard to claim 6, the combination of Combs, Seal and Henry discloses The apparatus of claim 1 (see rejection of claim 1 above) wherein when the comparison is to not be performed, a proper subset of flags of a flags register are to be changed. (Seal [0071 and 0078]: wherein when the comparison is not performed a proper subset of flags are set using a fail condition state)
The combination of Combs, Seal and Henry thus far does not disclose a proper subset of flags of a flags register are to be inverted. Seal discloses the flags register being set to a programmable fail condition that can be any programmable value (see [0021-0023]); however, Seal has not explicitly stated that the fail condition can indicate an inversion of flags.
Dent discloses a proper subset of flags of a flags register are to be inverted. (Column 12, lines 46-50: wherein bits of a condition register are inverted)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the failure condition set in status register of Combs, Seal and Henry to include inversion of flags in the status register as in Dent. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (setting a state of a status register by inverting bits as taught in Dent) for another (generically setting a state of a status register as taught in Seal) to yield predictable results (setting a failed state in a status register by inverting the bits) (MPEP 2143, Example B).
Claim 16 is similarly rejected on the same basis as claim 6 above.
In regard to claim 7, the combination of Combs, Seal, Henry and Dent discloses The apparatus of claim 6 (see rejection of claim 6 above) wherein the proper subset of flags includes an overflow flag, a sign flag, a zero flag, and a carry flag. (Combs [0028 and 0033]| Seal [0069-0071]|Henry [0045]|Dent: Column 7, lines 55-65)
Claim 17 is similarly rejected on the same basis as claim 7 above.
Claim(s) 1, 3-4, 11-14, and 21-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Collins, PGPUB No. 2016/0179538, Seal and further in view of Henry.
In regards to claim 21, Collins discloses A method comprising: translating an instance of single instruction of a first instruction set architecture to one or more instructions of a second instruction set architecture ([0071-0073 and Fig. 8]: wherein x86 instructions are converted to instructions of a different instruction set architecture) the instance of the single instruction of the first instruction set architecture to at least include a prefix, one or more fields to identify a first source operand location, one or more fields to identify a second source operand location ([0160, 0170 and 0178]: wherein single instruction format includes a prefix field (element 1702), source operand field (element 1744) and a source operand field (1746) (See Figs. 16-17)) wherein a payload of the prefix is to provide most significant bits to identify at least one of the first and second source operand locations ([0166-0167]: wherein payload (byte 1) of EVEX prefix provides most significant bits (highest bits of register indexes) to identify one of the first or second operand locations) decoding the one or more instructions of the second instruction set architecture; and executing the decoded one or more instructions of the second instruction set architecture. ([0035-0036 and 0072]: wherein a core which executes a different instruction set decodes and executes the converted instructions)
Collins does not disclose comprising: an instance of the single instruction to at least include one or more fields to identify a first source operand location, one or more fields to identify a second source operand location and an opcode to indicate execution circuitry is to conditionally perform a comparison of data from the identified first source operand location to the identified second source operand location based at least in part on an evaluation of a source condition code provided by the prefix, wherein when the source condition code is satisfied a flags register is to be updated based on a comparison of the first source operand and the second source operand and when the source condition is not satisfied the flags register is to be set by a destination condition code provided by the prefix nor executing the instance of the single instruction according to the opcode of the instance of the single instruction. Collins does generally disclose conditionally executing predicated instructions; however, Collins does not disclose a conditional compare instruction.
Seal discloses an instance of the single instruction to at least include one or more fields to identify a first source operand location, one or more fields to identify a second source operand location ([0070-0071 and 0076]: wherein a conditional compare instruction includes one or more fields to identify a first source operand register and a second source operand register) and an opcode to indicate execution circuitry is to conditionally perform a comparison of data from the identified first source operand location to the identified second source operand location based at least in part on an evaluation of a source condition code ([0070-0071 and 0077]: wherein an opcode of CCMP instruction indicates processing circuitry is to conditionally perform a comparison of data from the first and second source operands based at least in part on evaluating a test condition code (Cond) and update a condition code flags of a status register (element 15)(See Figs. 3A-B and 5)) wherein when the source condition code is satisfied a flags register is to be updated based on a comparison of the first source operand and the second source operand and when the source condition is not satisfied the flags register is to be set by a destination condition code provided ([0070-0071 and 0077]: wherein if condition is satisfied flags are updated based on comparison, if condition is not satisfied the flags register is set by failed condition code state in immediate (See Figs. 3A-B and 5)) executing the instance of the single instruction according to the opcode of the instance of the single instruction. ([0076-0077]: wherein the CCMP instruction is decoded and executed)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify instruction set of Collins, which includes conditional instructions, to include a conditional compare instruction as taught in Seal. It would have been obvious to one of ordinary skill in the art because the conditional compare instruction allows for testing of a chained sequence of comparisons of different types and thus can be used more widely and is hence more easily usable by compilers (Seal [0016])
The combination of Collins and Seal does not disclose a source condition code and destination condition code provided by a prefix.
Henry discloses an extended prefix for conditional execution that provides source condition code and includes spare bits which are unused (See Figs. 6-7 and [0050-0056)
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the conditional compare instruction of Collins and Seal to utilize an extended prefix as taught in Henry to store both source and destination condition codes. It would have been obvious to one of ordinary skill in the art because using an extended prefix to store multiple condition codes used for conditional instruction execution can be used for added flexibility of the instruction by employing different condition code combinations (Henry [0031, 0042 and 0052]). Furthermore, it would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (storing condition codes in a prefix field of an instruction) for another (storing condition codes in immediate fields of an instruction) to yield predictable results (performing a conditional compare instruction which includes an extended prefix to store source and destination condition codes) (MPEP 2143, Example B).
Claims 1 and 11 are similarly rejected on the same basis as claim 21 above. (See Collins Figs. 1B, 4 and 11 which disclose various processors and/or systems including decode and execute circuitry)
In regard to claim 22, the combination of Collins, Seal and Henry discloses The method of claim 21 (see rejection of claim 21 above) wherein the first source operand is a register and the second operand is a memory location. (Collins [0134-0136 and 0178-0180]: wherein first source is a register and destination is a memory location (see Figs. 16-17) |Seal [0071 and 0077-0078]: wherein first source is a register)
Claim 12 is similarly rejected on the same basis as claim 22 above.
In regard to claim 23, the combination of Collins, Seal and Henry discloses The method of claim 21 (see rejection of claim 21 above) wherein the first source operand and second source operand location are registers. (Collins [0178]: wherein first source and second source are registers |Seal [0071, 0077-0078])
Claims 3 and 13 are similarly rejected on the same basis as claim 23 above.
In regard to claim 24, the combination of Collins, Seal and Henry discloses The method of claim 23 (see rejection of claim 23 above) wherein the prefix is to include two bits for each of the first and second source operands to be used as most significant bits of a register identifier. (Collins [0166-0167 and 0178]: wherein EVEX prefix includes two bits for each of the first and second source operands to be used as the most significant bits of a register identifier (e.g. bits R and R’ for a first source and bits B and R’ for example; see elements 1705 and 1710 of Fig. 17))
Claims 4 and 14 are similarly rejected on the same basis as claim 24 above.
Claim(s) 6, 16 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Collins, Seal, Henry and further in view of Dent, USPAT. No. 6,314,504.
In regard to claim 25, the combination of Collins, Seal and Henry discloses The method of claim 21 (see rejection of claim 21 above) wherein when the comparison is to not be performed, a proper subset of flags of a flags register are to be changed. (Seal [0071 and 0078]: wherein when the comparison is not performed a proper subset of flags are set using a fail condition state)
The combination of Collins, Seal and Henry thus far does not disclose a proper subset of flags of a flags register are to be inverted. Seal discloses the flags register being set to a programmable fail condition that can be any programmable value (see [0021-0023]); however, Seal has not explicitly stated that the fail condition can indicate an inversion of flags.
Dent discloses a proper subset of flags of a flags register are to be inverted. (Column 12, lines 46-50: wherein bits of a condition register are inverted)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the failure condition set in status register of Collins, Seal and Henry to include inversion of flags in the status register as in Dent. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (setting a state of a status register by inverting bits as taught in Dent) for another (generically setting a state of a status register as taught in Seal) to yield predictable results (setting a failed state in a status register by inverting the bits) (MPEP 2143, Example B).
Claims 6 and 16 are similarly rejected on the same basis as claim 25 above.
Response to Arguments
Applicants’ arguments, see pages 6-8 of the remarks filed on 7/9/2026 with respect to the previous 35 USC 101 rejections have been fully considered and in light of the amendments made to the claims the previous rejections have been withdrawn.
Applicant’s arguments, see page 8 of the remarks, filed on 7/9/2026 with respect to the previous rejection(s) of claim(s) 1-25 under 35 USC 112(a-b) have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of 35 USC 112(b) and/or 35 USC 103.
Applicant’s arguments, see pages 8-11 of remarks filed on 7/9/2026, with respect to the rejection(s) of claim(s) 21-25 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of 35 USC 103 in view of Collins, Seal and Henry.
Conclusion
Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY P SPANN whose telephone number is (571)431-0692. The examiner can normally be reached M-F, 9am-6pm, EST.
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/COURTNEY P SPANN/ Primary Examiner, Art Unit 2183
