The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
This is a reply to the request for Continued Examination (RCE) filed on 8/8/2025, in which Claim(s) 1-10 and 12-21 are presented for examination.
Claim(s) 11 is/are cancelled.
Claims 18-20 are withdrawn.
Claim(s) 21 is/are newly added.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/8/2025 has been entered.
Response to Argument
Claim Rejections - 35 U.S.C. § 112:
Applicants’ arguments with respect to 112 1st paragraph with rejection of claim(s) 1-17 have been fully considered and are persuasive. The rejection of 112 1st paragraph has been withdrawn in view of the amendment(s).
Applicants’ arguments with respect to 112 2nd paragraph with rejection of claim(s) 1-17 have been fully considered and are persuasive. The rejection of 112 2nd paragraph has been withdrawn in view of the amendment(s).
Claim Rejections - 35 U.S.C. § 102 and 35 U.S.C. § 103:
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicants’ arguments with respect to claims rejected under prior art have been fully considered but they are not persuasive.
Applicant’s arguments with respect to the rejection of claim(s) 1-10 and 12-21 have been considered but are moot in view of the new ground(s) of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 7-9 and 12-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Binder (US 20120166582 A1) in view of Yang et al. (CN 107292192 A; hereinafter Yang) further in view of Wang et al. (US 20140185690 A1; hereinafter Wang) further in view of Pozidis et al. (US 20210303425 A1; hereinafter Pozidis).
Regarding claims 1 and 8, Binder discloses a data protection method comprising:
splitting input data into a plurality of data groups (the input information are splits into multiple portions, where the information is divided into files of variable length [Binder; ¶33, 98-99; Fig. 19a-19c, 45-46 and associated text]);
recording an original start-address of each data group [[and a data length of each data group]] (the split information are stored in the address spaces between the memories and length of slices [Binder; ¶33, 98-99, 193-194, 325; Fig. 19a-19c, 45-46 and associated text]);
reorder the data wherein the reordered data groups constitute random data (the data scrambler scrambles the data in different orders, by changing the order of the address bits [Binder; ¶33, 98-99, 263; Fig. 19a-19c, 45-46 and associated text]);
recording a new start-address for each reordered data group (the data will be stored to the memory at different locations [Binder; ¶33, 98-99, 263; Fig. 19a-19c, 45-46 and associated text]);
collecting the original start-addresses, the data lengths, and the new start-addresses to form a look-up table, wherein the look-up table records the original start-addresses of the data groups and the new start-addresses of the reordered data groups, and each original start-address corresponds to one new start-address (the memory is used in order to perform the address mapping. Such an arrangement is shown as sub-system 198 shown in FIG. 19c, disclosing a memory 199 being part of the address scrambler 196. The memory 199 is used to create the combinational logic function such as LUT (Look-Up Table), where the address over the bus 176 serves as the address of the memory 199, and the resulting data read from the memory 199 serves as the address to memory 171 over bus 182 [Binder; ¶33, 98-99, 263; Fig. 19a-19c, 45-46 and associated text]);
storing the random data into a storage memory (the data are stored to the memory [Binder; ¶Fig. 19a-19c, 45-46 and associated text]); and
storing the look-up table [[into a memory controller]] (storing the LUT [Binder; Fig. 19a-19c and associated text]). Binder discloses the use of look-up table (LUT). Binder does not explicilty discloses uses a Binary-Tree searches method to reorder the sequence of the data groups; however, in a related and analogous art, Yang teaches this feature.
In particular, Yang teaches using binary tree to reorder sequence of data, especially when the data sequence is unbalanced in the binary tree [Yang; Figs. 2-3 and associated text]. It would have been obvious before the effective filing date of the claimed invention to modify Binder in view of Yang reorder using rearranged tree with the motivation to balance the node and improve the efficiency of database operation [Yang; Abstract]. Binder-Yang combination does not explicilty disclose recording an original start-address of each data group and a data length of each data group; however, in a related and analogous art, Wang teaches this feature.
In particular, Wang teaches use of LUT that records address of the content and size to identifying position and location when the content is a whole [Wang; ¶27-33]. It would have been obvious before the filing of the claimed invention to modify Binder-Yang combination in view of Wang with the motivation to easier location and positions of each part within the whole.
Binder-Yang-Wang combination discloses the use of look-up table (LUT). Binder-Yang-Wang combination does not explicilty disclose storing the look-up table into a memory controller; however, in a related and analogous art, Pozidis teaches this feature.
IN particular, Pozidis teaches data splitting and scrambling and storing data based on LUT with mapping and the encoder/decoder pipeline in the NVM controller is modified as illustrated in FIGS. 8-12 to include a dynamic logical to physical mapper 820, that in an aspect includes the capability to remap the logical packages to physical packages. The updated mapping of the physical to logical packages preferably is stored in a conversion look-up L/P table 146 that is shared by the encoder 800 and decoder 1000. The conversion look-up L/P table 146 is preferably saved in NVM controller memory 142, NVM controller 140, and/or NVM memory packages on NVM card 126, although it can be stored in other alternative or additional locations. [Pozidis; ¶8-9, 46, 62]. It would have been obvious before the effective filing date of the claimed invention to modify Binder-Yang-Wang in view of Pozidis to store the LUT in the preferably memory controller with the motivation for faster and secure retrieval.
Regarding claim 2, Binder-Yang-Wang-Pozidis combination discloses the data protection method as claimed in claim 1, wherein the data length of a first data group of the data groups is different from the data length of a second data group of the data groups (where the information is divided into files of variable length or equal [Binder; ¶33, 98-99; Fig. 19a-19c, 45-46 and associated text]).
Regarding claim 3, Binder-Yang-Wang-Pozidis combination discloses the data protection method as claimed in claim 2, wherein the data length of the first data group is the same as the data length of a third data group of the data groups (The splitting non-limiting examples above involved splitting into equal length of slices [Binder; ¶192; Fig. 19a-19c, 45-46 and associated text]).
Regarding claim 4, Binder-Yang-Wang-Pozidis combination discloses the data protection method as claimed in claim 1, wherein the step of collecting the original start-addresses, the data lengths, and the new start-addresses to form a look-up table comprises: arranging the reordered data groups according to the data lengths of the data groups (the slices are sequentially and individually handled, based on a pre-determined order (or randomly) [Binder; ¶197; Fig. 19a-19c, 45-46 and associated text]).
Regarding claim 7, Binder-Yang-Wang-Pozidis combination discloses the data protection method as claimed in claim 1, further comprising: receiving a read command; decoding the read command to generate a read address; utilizing the look-up table to find a new start-address corresponding to the read address; reading the storage memory to determine a data group corresponding to the new start-address; and outputting the corresponding data group (the data scrambler retrieves the splitted data from the memory and mapped it to the new address before output it to the data logic [Binder; ¶274-277; Fig. 22 and associated text]).
Regarding claim 9, Binder-Yang-Wang-Pozidis combination discloses the data protection device as claimed in claim 8, wherein the storage memory and the memory controller are integrated into a micro-controller unit (MCU), and the reordering circuit is disposed outside of the micro-controller unit (MCU integrated and the disposed is in the memory [Binder; ¶252]).
Regarding claim 12, Binder-Yang-Wang-Pozidis combination discloses the data protection device as claimed in claim 8, wherein in response to the memory controller receiving a write command, the memory controller writes the random data to the storage memory according to the new start-addresses recorded in the look-up table (the processor may access the memory 199 in a way similar to the way the memory 171 is accessed, and can thus write its content and write to memory command [Binder; ¶266-268; Fig. 18-19 and associated texts]).
Regarding claim 13, Binder-Yang-Wang-Pozidis combination discloses the data protection device as claimed in claim 12, wherein: in response to the memory controller receiving a read command, the memory controller decodes the read command to generate a read address and checks the look-up table to find a corresponding new start-address corresponding to the read address, the memory controller reads the storage memory to determine a data group corresponding to the corresponding new start-address and outputs the data group (the processor may access the memory 199 in a way similar to the way the memory 171 is accessed, and can thus read the content and read to/from memory command [Binder; ¶28, 266-268; Fig. 18-19 and associated texts]).
Regarding claim 14, Binder-Yang-Wang-Pozidis combination discloses the data protection device as claimed in claim 13, wherein the memory controller comprises: a fast look-up engine searching the look-up table to determine the corresponding new start-address corresponding to the read address (fast address lookup with LUT [Binder; ¶266-268; Fig. 18-19 and associated texts]).
Regarding claim 15, Binder-Yang-Wang-Pozidis combination discloses the data protection device as claimed in claim 14, further comprising: a central processing unit (CPU) sending the write command and the read command; an instruction bus coupled between the CPU and the memory controller to transmit the write command and the read command; and a data bus coupled between the CPU and the memory controller to transmit the corresponding data groups (the controller 172 read/write to memory 171 either direct or indirect based on the bus [Binder; ¶266-268; Fig. 18-19 and associated texts]).
Regarding claim 16, Binder-Yang-Wang-Pozidis combination discloses the data protection device as claimed in claim 8. wherein the data length of a first data group of the data groups is different from the data length of a second data group of the data groups (where the information is divided into files of variable length or equal [Binder; ¶33, 98-99; Fig. 19a-19c, 45-46 and associated text]).
Regarding claim 17, Binder-Yang-Wang-Pozidis combination discloses the data protection device as claimed in claim 16. wherein the data length of the first data group is the same as the data length of a third data group of the data groups (The splitting non-limiting examples above involved splitting into equal length of slices [Binder; ¶192; Fig. 19a-19c, 45-46 and associated text]).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Binder-Yang-Wang-Pozidis combination further in view of Loh et al. (US 20050083298 A1; hereinafter Loh).
Regarding claim 5, Binder-Yang-Wang-Pozidis combination does not explicilty discloses the data protection method as claimed in claim 1, wherein the step of collecting the original start-addresses, the data lengths, and the new start-addresses to form a look-up table comprises: utilizing a Binary-tree search method to arrange the reordered data groups; however, in a related and analogous art, Loh teaches this feature.
In particular, Loh teaches the numeric values are arranged in a search pattern such as a binary tree search, in order to speed access to the look-up table [Loh; ¶69]. It would have been obvious before the effective filing date of the claimed invention to modify Binder-Yang-Wang-Pozidis combination in view of Loh with the motivation to search the LUT faster.
Claim(s) 6, 10 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Binder-Yang-Wang-Pozidis combination further in view of Reed et al. (US 20200004975 A1; hereinafter Reed).
Regarding claims 6 and 10, Binder-Yang-Wang-Pozidis combination discloses wherein the restored data is the unencrypted look-up table (accessing unencrypted look-up table [Binder; ¶213, 266]);
wherein the encryption circuit is disposed outside of the micro-controller unit, and the decryption circuit is disposed inside of the micro-controller unit (the controller is an embedded processor integrated and the decrypting is within the MCU [Binder; ¶27, 224, 252]). Binder-Yang-Wang-Pozidis combination does not explicilty discloses the step of storing the look-up table into a memory controller comprises: encrypting the look-up table to generate encrypted data; decrypting the encrypted data to generate restored data; and storing the restored data in the memory controller; however, in a related and analogous art, Reed teaches this feature.
In particular, Reed teaches access to encrypting and decrypting of the look-up table with proper authorization level, the look-up table is decrypted before it can be read [Reed; ¶45]. It would have been obvious before the effective filing date of the claimed invention to modify Binder-Yang-Wang-Pozidis combination in view of Reed with the motivation to prevent unauthorized access to the LUT.
Regarding claim 21, Binder-Yang-Wang-Pozidis-Reed combination discloses the data protection device as claimed in claim 10, wherein the reordering circuit uses the Binary-tree search method to reorder the sequence of the data groups and serves the reordered result as the look-up table (using binary tree to reorder sequence of data, especially when the data sequence is unbalanced in the binary tree [Yang; Figs. 2-3 and associated text]). The motivation to balance the node and improve the efficiency of database operation [Yang; Abstract].
Internet Communications
Applicant is encouraged to submit a written authorization for Internet communications (PTO/SB/439, http:ljwww.uspto.gov/sites/default/files/documents/sb0439.pdf) in the instant patent application to authorize the examiner to communicate with the applicant via email. The authorization will allow the examiner to better practice compact prosecution. The written authorization can be submitted via one of the following methods only: (1) Central Fax which can be found in the Conclusion section of this Office action; (2) regular postal mail; (3) EFS WEB; or (4) the service window on the Alexandria campus. EFS web is the recommended way to submit the form since this allows the form to be entered into the file wrapper within the same day (system dependent). Written authorization submitted via other methods, such as direct fax to the examiner or email, will not be accepted. See MPEP § 502.03.
Conclusion
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/DAO Q HO/Primary Examiner, Art Unit 2432