Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 8-12 are objected to because of the following informalities:
Claims 8-12 recites the limitation "the processing node of claim 1". There is insufficient antecedent basis for this limitation in the claim. It appears that this was a typographical error, and the claims were intended to depend upon claim 7. As such, claims 8-12 are interpreted to depend upon claim 7.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 14-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. Claims 14-20 recite a design structure tangibly embodied in a machine-readable storage device, but paragraph 0173 of the spec only provides an exclusionary provision for a "computer-readable storage device". Since those two terms are different, the exclusionary provision of paragraph 0173 does not cover a "machine-readable storage device" and therefore a "machine-readable storage device" is open-ended and can cover all possible mediums, including non-statutory ones. As such, the claims are not limited to statutory subject matter and are therefore non-statutory. See M.P.E.P. 2601.1 Section I, which states, “Since a computer program is merely a set of instructions capable of being executed by a computer, the computer program itself is not a process and USPTO personnel should treat a claim for a computer program, without the computer-readable medium needed to realize the computer program's functionality, as nonstatutory functional descriptive material.” Applicant is encouraged to align the claim terminology of claims 14-20 with that used in paragraph 0173.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 14-20 recite a design structure tangibly embodied in a machine-readable storage device. It is unclear whether or not the broadest reasonable interpretation of the “Design structure” would encompass a simple circuit drawing. It would appear that the claim could possibly encompass a pure drawing of a system with layout and wires - which is not functional in the same way as a program that runs when executed. Paragraph 171 of the specification indicates a design structure may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g., information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Applicant is encouraged to amend the claims towards more traditional programmatic language to close off the BRI of “design structure” encompassing simple drawings or schematics that don’t really “function”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 6-9, 12-16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi et al. (US 2015/0339167) in view of Villavieja et al. (DiDi…).
Regarding claim 1, Takeuchi discloses a method of multicast communication in a data processing system including a master processing node and a plurality of snoopers communicatively coupled to a system fabric for communicating requests, wherein the master processing node and the plurality of snoopers are distributed among a plurality of nodes [see Fig. 1 & paragraphs 11, 60-62 & 65-67; a plurality of nodes, any of which may be interpreted as a master node, the nodes being coupled by an interconnect. The nodes comprise shared resources such as CPU’s and memory (interpreted as snoopers). Applicant’s specification, at paragraph 65, provides a non-exhaustive list of snoopers including a token manager 120, L2 caches 230, IOMMUs 210, memory controllers 106, etc)], the method comprising:
maintaining logical partition (LPAR) information for each of a plurality of LPARs [see paragraph 66; LPAR management table].
Takeuchi does not expressly disclose the LPAR information indicates, for each of the plurality of LPARs, which of the plurality of nodes includes at least one snooper among the plurality of snoopers that may hold an address translation entry for said each LPAR;
based on the LPAR information, the master processing node selecting a broadcast scope of a multicast request on the system fabric, wherein the broadcast scope includes fewer than all of the plurality of nodes; and
the master processing node repetitively issuing, on the system fabric, the multicast request utilizing the selected broadcast scope until the multicast request is successfully received by all of the plurality of snoopers within the broadcast scope.
Villavieja discloses a multiprocessor system in which a TLB directory is maintained, the directory that tracks every address translation stored on first level TLBs of the whole system. Based on this information, an initiator processor may issue a TLB shootdown instruction to invalidate a TLB entry at the processor, and the information of the TLB directory is used to locate a subset (less than all) of processors containing the specified TLB entry. The TLB invalidation request is then broadcast in a multicast message to all of the affected processors until all of the processors have successfully replied to the request [see section VI-(a) and VI-(b)].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the TLB directory information of Villavieja in the LPAR management information of Takeuchi.
The motivation for doing so would have been to reduce the overheads and bottlenecks of performing TLB invalidations in multiprocessor systems [see Villavieja, I. Introduction].
Therefore, it would have been obvious to combine Villavieja with Takeuchi for the benefits listed above, to obtain the invention as specified in claim1-3, 6-9, 12-16 and 19.
Regarding claim 2, the combination discloses the method of Claim 1, wherein the multicast request comprises a translation entry invalidation request [see Villavieja, section VI; TLB invalidation request is multicast].
Regarding claim 3, the combination discloses the method of Claim 1, wherein: the maintaining includes maintaining LPAR information indicating which of the plurality of nodes holds input/output (I/O) address translation entries for the plurality of LPARs [see Villavieja, Section VI; TLB directory maintains tracks every address translation stored on first level TLBs of the whole system].
Regarding claim 6, the combination discloses the method of Claim 1, and further comprising:
the master processing node issuing on the system fabric to all of the plurality of nodes a
request for the plurality of snoopers to indicate node locations of address translations for a given LPAR; and the maintaining includes the master processing node updating the LPAR information
based on responses of the plurality of snoopers to the request [see Villavieja; Section IV; TLB directory is updated for all changes made to level 1 TLBs of the whole system].
Claims 7-9, 12-16 and 19 recite similar limitations to those of claims 1-3 and 6 and are rejected using the same citations and interpretations.
Claims 4, 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi in view of Villavieja and further in view of Li (US 2022/0121464).
Regarding claim 4, the combination discloses the method of claim 1 as discussed above.
The combination does not expressly disclose the maintaining includes maintaining in a processing node of the data processing system LPAR information for at least one inactive LPAR not executing in the processing node.
Li discloses virtualized processing system which logical-to-physical mapping information (LPAR information) is saved when a virtual machine (logical partition) is to be changed to an inactive state [see paragraphs 89-91].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the saved information of inactive virtual mchaines in the system of Takeuchi and Villavieja.
The motivation for doing so would have been to preserve the information for use when the virtual machine is changed back to an active sate [see Li, paragraph 40].
Therefore, it would have been obvious to combine Li with Takeuchi and Villavieja for the benefits listed above, to obtain the invention as specified in claims 4, 10 and 17.
Claims 10 and 17 recite similar limitations to those of claim 4 and are rejected using the same citations and interpretations.
Claims 5, 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi in view of Villavieja and further in view of Ono et al. (US 2022/0058044).
Regarding claim 5, the combination discloses the method of claim 1 as discussed above.
The combination does not expressly disclose establishing an entry for a LPAR in the LPAR information in response to execution of an enable instruction by a processor
core of the data processing system.
Ono discloses a virtualized processing system in which a new entry is added to a virtual machine (logical partition) management table (LPAR information) when a new VM (LPAR) is created [see paragraph 106].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the teachings of Ono to add new entries into the LPAR information of Takeuchi and Villavieja.
The motivation for doing so would have been to properly manage a newly created virtual machine (LPAR) [see Ono, paragraph 85].
Therefore, it would have been obvious to combine Ono with Takeuchi and Villavieja for the benefits listed above, to obtain the invention as specified in claims 5, 11 and 18.
Claims 11 and 18 recite similar limitations to those of claim 5 and are rejected using the same citations and interpretations.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kapoor (US 2017/0153982), Kessler (US 2016/0140051), Gannon (US 5,265,232) & Northup (US 10,540,292) – Generally teach invalidating TLB entries in a plurality of processing units.
Arroyo (US 2012/0155462) – Generally teaches sending multicast messages in logical partition environments.
Onodera (US 5,996,026) – Generally teaches maintaining LPAR information for a plurality of logical partitions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN BERTRAM whose telephone number is (571)270-1377. The examiner can normally be reached M-F 8:30-5MNT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached at 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RYAN BERTRAM/Primary Examiner, Art Unit 2137