Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 6-9, 12-16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi et al. (US 2015/0339167) in view of Villavieja et al. (DiDi…) and further in view of Moore et al. (US 5,437,017).
Regarding claim 1, Takeuchi discloses a method of multicast communication in a data processing system including a master processing node and a plurality of snoopers communicatively coupled to a system fabric for communicating requests, wherein the master processing node and the plurality of snoopers are distributed among a plurality of nodes [see Fig. 1 & paragraphs 11, 60-62 & 65-67; a plurality of nodes, any of which may be interpreted as a master node, the nodes being coupled by an interconnect. The nodes comprise shared resources such as CPU’s and memory (interpreted as snoopers). Applicant’s specification, at paragraph 65, provides a non-exhaustive list of snoopers including a token manager 120, L2 caches 230, IOMMUs 210, memory controllers 106, etc)], the method comprising:
maintaining logical partition (LPAR) information for each LPAR of a plurality of LPARs [see paragraph 66; LPAR management table].
Takeuchi does not expressly disclose the LPAR information indicates, for each LPAR of the plurality of LPARs, which of the plurality of nodes includes at least one snooper among the plurality of snoopers holds an address translation entry for a respective LPAR of the plurality of LPARs;
selecting by the master processing node a broadcast scope of a multicast request on the system fabric based on the LPAR information, wherein the broadcast scope includes one or more nodes of the plurality of nodes, and the one or more nodes are fewer than the plurality of nodes; and
issuing on the system fabric, by the master processing node, the multicast request utilizing the broadcast scope to the plurality of snoopers within the broadcast scope.
Villavieja discloses a multiprocessor system in which a TLB directory is maintained, the directory that tracks every address translation stored on first level TLBs of the whole system. Based on this information, an initiator processor may issue a TLB shootdown instruction to invalidate a TLB entry at the processor, and the information of the TLB directory is used to locate a subset (less than all) of processors containing the specified TLB entry. The TLB invalidation request is then broadcast in a multicast message to all of the affected processors until all of the processors have successfully replied to the request [see section VI-(a) and VI-(b)].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the TLB directory information of Villavieja in the LPAR management information of Takeuchi.
The motivation for doing so would have been to reduce the overheads and bottlenecks of performing TLB invalidations in multiprocessor systems [see Villavieja, I. Introduction].
Therefore, it would have been obvious to combine Villavieja with Takeuchi for the benefits listed above, to obtain the invention as specified in claims 1-3, 6-9, 12-16 and 19.
The combination of Takeuchi and Villavieja does not expressly disclose receiving, by the master processing node, a plurality of partial responses from the plurality of snoopers; combining, by the master processing node, the plurality of partial responses to generate a combined response; and reissuing, on the system fabric, by the master processing node, the multicast request based on the combined response indicating a retry of the multicast request.
Moore discloses a multiprocessor system in which a processor may broadcast a TLB invalidation request to the other processors within the system. Responses from all of the processors are received, and if any of the responses indicate “RETRY”, the process returns to an iterative fashion of once again attempting to broadcast the translation lookaside buffer invalidate request [see Col. 7, lines 36-65 to Col. 8, lines 1-10].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the response gathering technique of Moore in the system of Takeuchi and Villavieja.
The motivation for doing so would have been for maintaining translation lookaside buffer (TLB) coherency in a multiprocessor system which does not require interprocessor interrupts and software synchronization [see Moore, Col. 10, lines 26-46].
Therefore, it would have been obvious to combine Moore with Takeuchi and Villavieja for the benefits listed above, to obtain the invention as specified in claims 1-3, 6-9, 12-16 and 19.
Regarding claim 2, the combination discloses the method of Claim 1, wherein the multicast request comprises a translation entry invalidation request [see Villavieja, section VI; TLB invalidation request is multicast].
Regarding claim 3, the combination discloses the method of Claim 1, wherein the maintaining includes maintaining the LPAR information indicating which of the plurality of nodes holds input/output (I/O) address translation entries for the plurality of LPARs [see Villavieja, Section VI; TLB directory maintains tracks every address translation stored on first level TLBs of the whole system].
Regarding claim 6, the combination discloses the method of Claim 1, further comprising:
Issuing, on the system fabric, by the master processing node, to all of the plurality of nodes a request for the plurality of snoopers to indicate node locations of address translations for an LPAR of the plurality of LPARs, wherein the maintaining includes the master processing node updating the LPAR information based on responses of the plurality of snoopers to the request [see Villavieja; Section IV; TLB directory is updated for all changes made to level 1 TLBs of the whole system].
Claims 7-9, 12-16 and 19 recite similar limitations to those of claims 1-3 and 6 and are rejected using the same citations and interpretations.
Claims 4, 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi in view of Villavieja and Moore and further in view of Li (US 2022/0121464).
Regarding claim 4, the combination discloses the method of claim 1 as discussed above.
The combination does not expressly disclose the maintaining includes maintaining in a processing node of the data processing system, the LPAR information for at least one inactive LPAR not executing in the processing node, the plurality of LPARs including the at least one inactive LPAR.
Li discloses virtualized processing system which logical-to-physical mapping information (LPAR information) is saved when a virtual machine (logical partition) is to be changed to an inactive state [see paragraphs 89-91].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the saved information of inactive virtual mchaines in the system of Takeuchi and Villavieja and Moore.
The motivation for doing so would have been to preserve the information for use when the virtual machine is changed back to an active sate [see Li, paragraph 40].
Therefore, it would have been obvious to combine Li with Takeuchi and Villavieja and Moore for the benefits listed above, to obtain the invention as specified in claims 4, 10 and 17.
Claims 10 and 17 recite similar limitations to those of claim 4 and are rejected using the same citations and interpretations.
Claims 5, 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi in view of Villavieja and Moore and further in view of Ono et al. (US 2022/0058044).
Regarding claim 5, the combination discloses the method of claim 1 as discussed above.
The combination does not expressly disclose establishing an entry for an LPAR of the plurality of LPARs in the LPAR information based on execution of an enable instruction by a processor core of the data processing system.
Ono discloses a virtualized processing system in which a new entry is added to a virtual machine (logical partition) management table (LPAR information) when a new VM (LPAR) is created [see paragraph 106].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the teachings of Ono to add new entries into the LPAR information of Takeuchi and Villavieja and Moore.
The motivation for doing so would have been to properly manage a newly created virtual machine (LPAR) [see Ono, paragraph 85].
Therefore, it would have been obvious to combine Ono with Takeuchi and Villavieja and Moore for the benefits listed above, to obtain the invention as specified in claims 5, 11 and 18.
Claims 11 and 18 recite similar limitations to those of claim 5 and are rejected using the same citations and interpretations.
Response to Arguments
Applicant’s arguments, filed 5/11/2026, with respect to the 101 and 112 rejections have been fully considered and are persuasive. The 101 and 112 rejections of claims 14-20 have been withdrawn.
Applicant’s arguments, filed 5/11/2026, with respect to the rejection(s) of claim(s) 1-3, 6-9, 12-16 and 19 under Takeuchi and Villavieja have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Moore.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN BERTRAM whose telephone number is (571)270-1377. The examiner can normally be reached M-F 8:30-5MNT.
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/RYAN BERTRAM/Primary Examiner, Art Unit 2137
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