DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 10, 17, 18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ye et al. (U.S. Patent Application Publication 2017/0237434, hereafter Ye).
Claim 1: Ye teaches a pulse generator (Figure 3), comprising:
one or more logic gates (304, 306) comprising a first input (clk) and a second input (via 302), wherein the first input is to receive a clock signal (clk), and the one or more logic gates are to output a first clock pulse (pclk) and a second clock pulse (npclk) which is an inverse of the first clock pulse (via 306);
a first path (via 310) and a second path (via 312) coupled to the one or more logic gates (outputs of 304 and 306), wherein the first path is to couple the first clock pulse to one or more pulsed latches (314) and the second path is to couple the second clock pulse to the one or more pulsed latches (314); and
latch components of the pulse generator (302) which are to replicate a delay of latch components in the one or more pulsed latches ([0034] where D latches 314 are the same type of latch, use the same type of process technology, and operate at the same temperatures as D latch 302), wherein the latch components of the pulse generator are to provide an output to the second input of the one or more logic gates (to 304).
Claim 2: Ye further teaches that the one or more logic gates comprise a NAND gate (304) and an inverter (306);
the NAND gate comprises the first input (308) and the second input (output of 302);
the NAND gate is to output the first clock pulse (pclk); and
the inverter (306) receives the first clock pulse from the NAND gate (via 310) and is to output the second clock pulse (npclk).
Claim 3: Ye further teaches that the latch components of the pulse generator are to write a logic 1 to the second input of the one or more logic gates when the clock signal goes high (Figure 8; [0057]).
Claim 10: Ye teaches an apparatus (Figure 3), comprising:
a pulse generator (302, 304, 306) to receive a clock signal (clk), and in response to the clock signal, to output a first clock pulse (pclk) and a second clock pulse (npclk) which is an inverse of the first clock pulse (via 306), wherein the pulse generator comprises a delay circuit (302) to delay the first clock pulse relative to the clock signal (via 302); and
a pulsed latched (314; [0034] where D latches 314 are the same type of latch, use the same type of process technology, and operate at the same temperatures as D latch 302, shown in further detail in Figure 5) coupled to the pulse generator (via 310 and 312), wherein the pulsed latch comprises an input inverter (502) to receive an input bit (D), latch components (504, 508) which are responsive to the first clock pulse (pclk) and the second clock pulse (npclk), and an output inverter (506, where a NAND is an AND gate in series with an inverter) to output an output bit (Q), and the delay circuit replicates a delay of the latch components ([0034]).
Claim 17: Ye teaches a pulse generator (Figures 3 and 5), comprising:
a NAND gate (304) comprising a first input (308) and a second input (output of 302), wherein the first input is to receive a clock signal (clk) and to output a first clock pulse (pclk);
an inverter (306) coupled to the NAND gate (via 310), the inverter is to receive the first clock pulse (pclk) and to output a second clock pulse (npclk) which is an inverse of the first clock pulse (via 306); and
a delay circuit (302) responsive to the first clock pulse and the second clock pulse to provide an output to the second input of the NAND gate (to 304), to delay the first clock pulse relative to the clock signal ([0034] where D latches 314 are the same type of latch, use the same type of process technology, and operate at the same temperatures as D latch 302).
Claim 18: Ye further teaches that the delay circuit comprises a tri-state inverter (508; Figure 5), a transmission gate (504) and an inverter (506 where NAND is an AND gate in series with an inverter);
an output of the tri-state inverter is coupled to the transmission gate and to an input of the inverter (Figure 5);
an output of the inverter is coupled to an input of the tri-state inverter (Figure 5);
the first clock pulse (pclk) is coupled to a complementary enable input of the tri-state inverter (inverted enable input of 508); the second clock pulse (npclk) is coupled to a primary enable input of the tri-state inverter (enable input of 508);
the first clock pulse (pclk) is coupled to a p-gate of the transmission gate (enable input of 504); and the second clock pulse (npclk) is coupled to an n-gate of the transmission gate (inverted enable input of 504).
Claim 20: Ye further teaches that the delay circuit is to write a logic 1 to the second input of the NAND gate when the clock signal goes high (Figures 6 and 8; [0057]).
Allowable Subject Matter
Claims 4-9, 11-16 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4, the prior art does not fairly teach or suggest the latch components of the pulse generator comprise first, second and third inverters; an output of the first inverter is coupled to the transmission gate; an output of the tri-state inverter is coupled to the transmission gate and to an input of the second inverter; an output of the second inverter is coupled to an input of the tri-state inverter; and the output of the tri-state inverter is coupled to an input of the third inverter. Claims 5-9 are objected to merely for being dependent from claim 4.
Regarding claim 11, the prior art does not fairly teach or suggest the latch components of the pulsed latch comprise a tri-state inverter, a transmission gate and an inverter; an output of the tri-state inverter is coupled to the transmission gate and to an input of the inverter; and an output of the inverter is coupled to an input of the tri-state inverter. Claims 12-16 are objected to merely for being dependent from claim 11.
Regarding claim 19, the prior art does not fairly teach or suggest an even number of inverters in a chain to couple an output of the tri-state inverter to the second input of the NAND gate, the chain delays the first clock pulse relative to the clock signal.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
U.S. Patent 10,291,211
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/C.J.O/Examiner, Art Unit 2849
/Menatoallah Youssef/SPE, Art Unit 2849