Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is Non-Final and is in response to claims filed on 12/30/2022. Claims 1-20 are pending for examination.
Information Disclosure Statement
The Information Disclosure Statements (IDS) submitted on 12/30/2022 and 05/10/2024 are in compliance with the provisions of 37 CFR 1.97, 1.98, and MPEP § 609. They have been placed in the application file, and the information referred to therein has been considered as to the merits.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: pool engines, reduction engine, division engine, vertical pool engine, horizontal pool engine, multiplication units, summation units, post calculation engine, etc. in claims 2, 4-9, and 12.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
The specification in paragraph [00256] recite “The configurable pooling processing units, neural network accelerators, crossbars, convolution processing units, and convolution engines described herein may be embodied in hardware on an integrated circuit”.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract ideas without significantly more.
With regards to claim 1, at step 1, the claim is directed to a machine, which is a statutory category of invention.
At Step 2A Prong 1, the examiner notes that the claim is directed to mental processes and/or mathematical concepts. The claim language has been reproduced below:
A hardware accelerator to implement a configurable pooling processing unit, the hardware accelerator configured to: (mental process, evaluation)
receive an input tensor comprising at least one channel, (mental process, evaluation; mathematical relationship) each channel of the at least one channel comprising a plurality of tensels; (mental process, evaluation; mathematical relationship)
receive control information identifying one operation of a plurality of selectable operations to be performed on the input tensor, (mental process, evaluation; mathematical relationship) the plurality of selectable operations comprising a depth-wise convolution operation and one or more pooling operations; (mental process, evaluation; mathematical relationship)
perform, using a same set of hardware components of the hardware accelerator regardless of the identified operation, (mental process, evaluation) the identified operation on the input tensor to generate an output tensor by performing one or more operations on blocks of tensels of each channel of the at least one channel of the input tensor; and (mathematical calculation)
output the output tensor. (mental process, evaluation; mathematical relationship)
Each of the non-bolded limitations are mental processes and/or mathematical calculations. The “A hardware accelerator to implement a configurable pooling processing unit, the hardware accelerator configured to” limitation is an evaluation mental process that can be performed by choosing what the hardware accelerator is configured to do. The “an input tensor comprising at least one channel” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the input tensor comprises. The “each channel of the at least one channel comprising a plurality of tensels” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the channels comprise. The “control information identifying one operation of a plurality of selectable operations to be performed on the input tensor” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the control information is. The “the plurality of selectable operations comprising” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the selectable operations comprise. The “perform, using a same set of hardware components of the hardware accelerator regardless of the identified operation” limitation is an evaluation mental process that can be performed by choosing where the operations are performed. The “the identified operation on the input tensor to generate an output tensor by performing one or more operations” limitation is a mathematical calculation that can be performed by performing the operation by hand using pen and paper. The “output the output tensor” limitation is an evaluation mental process and mathematical relationship that can be performed by outputting the tensor by hand using pen and paper.
At step 2A Prong 2, the additional elements are bolded above. The “receive” limitations, as claimed under BRI, are additional elements that are insignificant extra-solution activity. The ‘receiving’ in the context of the claim encompasses mere data gathering. The “output” limitation, as claimed under BRI, are additional elements that are insignificant extra-solution activity. The ‘output’ in the context of the claim encompasses mere data gathering. The remaining additional elements amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f).
Under Step 2B, the claim recites “receive an input tensor comprising at least one channel”, “receive control information identifying one operation of a plurality of selectable operations”, “output the output tensor”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
Regarding claim 20, It recites similar language as claim 1, and is rejected for at least the same reasons therein. Herein claim 20 is directed towards the statutory category of a method, thus also satisfying step 1. Moreover, Under steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 2, it is directed to mental processes and/or mathematical concepts. The “comprising one or more pool engines” limitation is an evaluation mental process that can be performed by choosing what the hardware accelerator comprises. The “each pool engine configurable to” limitation is an evaluation mental process that can be performed by choosing what the pool engines are configurable to do. The “generate one of a plurality of different types of channel outputs” limitation is a mathematical calculation that can be performed by generating the outputs by hand using pen and paper. The “the plurality of different types of channel outputs comprising” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the outputs comprise. Under step 2A Prong 2, the “receive” limitation, as claimed under BRI, is an additional elements that are insignificant extra-solution activity. The ‘receive’ in the context of the claim encompasses mere data gathering. None of the remaining additional elements regarding the generic computer components (i.e. the pool engines, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim recites “receive tensels of a channel of the input tensor”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 3, it is directed to mental processes and/or mathematical concepts. The “wherein the one or more pooling operations comprises” limitation is an evaluation mental process sand mathematical relationship that can be performed by choosing what the pooling operations comprise. Under steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 4, it is directed to mental processes and/or mathematical concepts. The “wherein each of the one or more pool engines comprises” limitation is an evaluation mental process that can be performed by choosing what the pool engines comprise. The “a reduction engine configurable to” limitation is an evaluation mental process that can be performed by choosing what the reduction engine is configurable to do. The “generate, for a block of tensels of a channel of the input tensor, one of a plurality of types of block outputs” limitation is a mathematical calculation that can be performed by generating the outputs by hand using pen and paper. The “the plurality of types of block outputs comprising” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the outputs comprise. The “a division engine configurable to” limitation is an evaluation mental process that can be performed by choosing what the division engine is configurable to do. The “selectively perform a division operation on the block output” limitation is a mathematical calculation that can be performed by performing the division operation by hand using pen and paper. The “wherein when the control information identifies that an average pooling operation is to be performed on the input tensor, the reduction engine is configured to” limitation is an evaluation mental process that can be performed by choosing what the reduction engine is configured to do. The “generate a sum of tensels in the block” limitations is a mathematical calculation that can be performed by generating a sum of the tensels by hand using pen and paper. The “the division engine is enabled to” limitation is an evaluation mental process that can be performed by choosing what the division engine is enabled to do. The “divide the block output generated by the reduction engine by a number of tensels in the block” limitation is a mathematical calculation that can be performed by performing the division by hand using pen and paper. The “and wherein when the control information identifies that a depth-wise convolution operation is to be performed on the input tensor, the reduction engine is configured to” limitation is an evaluation mental process that can be performed by choosing what the reduction engine is configured to do. The “generate a weighted sum for the block” limitation is a mathematical calculation that can be performed by generating the weighted sum by hand using pen and paper. The “the division engine is disabled” limitation is an evaluation mental process that can be performed by choosing what components are disabled. Under step 2A Prong 2, none of the remaining additional elements regarding the generic computer components (i.e. the pool engines, the reduction engine, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 5, it is directed to mental processes and/or mathematical concepts. The “wherein each block of tensels comprises” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the blocks of tensels comprises. The “the reduction engine is configured to” limitation is an evaluation mental process that can be performed by choosing what the reduction engine is configured to do. The “generate a block output by generating column outputs” limitation is a mathematical calculation that can be performed by generating the block output by hand using pen and paper. The “generating the block output from one or more column outputs” limitation is a mathematical calculation that can be performed by generating the block output by hand using pen and paper. Under step 2A Prong 2, none of the remaining additional elements regarding the generic computer components (i.e. the reduction engine, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 6, it is directed to mental processes and/or mathematical concepts. The “when the control information identifies that an average pooling operation is to be performed on the input tensor, the reduction engine is configured to” limitation is an evaluation mental process that can be performed by choosing what the reduction engine is configured to do. The “generate a sum for each column of a block of tensels” limitation is a mathematical calculation that can be performed by generating the sums by hand using pen and paper. The “generate the sum for the block of tensels by summing” limitation is a mathematical calculation that can be performed by generating the sum by hand using pen and paper. The “when the control information identifies that a depth-wise convolution operation is to be performed on the input tensor, the reduction engine is configured to” limitation is an evaluation mental process that can be performed by choosing what the reduction engine is configured to do. The “generate a weighted sum for each column of a block of tensels” limitation is a mathematical calculation that can be performed by generating the weighted sums by hand using pen and paper. The “generate the weighted sum for the block by summing appropriate” limitation is a mathematical calculation that can be performed by generating the weighted sum by hand using pen and paper. Under step 2A Prong 2, none of the remaining additional elements regarding the generic computer components (i.e. the reduction engine, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 7, it is directed to mental processes and/or mathematical concepts. The “wherein the reduction engine comprises” limitation is an evaluation mental process that can be performed by choosing what the reduction engine comprises. The “a vertical pool engine configurable to” limitation is an evaluation mental process that can be performed by choosing what the vertical pool engine is configurable to do. The “generate one of a plurality of types of column outputs” limitation is a mathematical calculation that can be performed by generating the outputs by hand. The “a collector storage unit configured to” limitation is an evaluation mental process that can be performed by choosing what the collector storage unit is configured to do. The “a horizontal pool engine configured to” limitation is an evaluation mental process that can be performed by choosing what the horizontal pool engine is configured to do. The “generate a block output from appropriate column outputs” limitation is a mathematical calculation that can be performed by generating the output by hand. Under step 2A Prong 2, the “receive” limitation, as claimed under BRI, is an additional elements that are insignificant extra-solution activity. The ‘receive’ in the context of the claim encompasses mere data gathering. the “store” limitation, as claimed under BRI, is an additional elements that are insignificant extra-solution activity. The ‘store’ in the context of the claim encompasses mere data gathering. None of the remaining additional elements regarding the generic computer components (i.e. the reduction engine, the vertical pool engine, the horizontal pool engine, the collector storage unit, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim recites “receive a column of tensels”, “temporarily store the column outputs generated”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 8, it is directed to mental processes and/or mathematical concepts. The “when the control information identifies that an average pooling operation is to be performed on the input tensor, the vertical pool engine is configured to” limitation is an evaluation mental process that can be performed by choosing what the vertical pool engine is configured to do. The “generate a sum of the received tensels” limitation is a mathematical calculation that can be performed by generating the sum by hand using pen and paper. The “when the control information identifies that a depth-wise convolution operation is to be performed on the input tensor, the vertical pool engine is configured to” limitation is an evaluation mental process that can be performed by choosing what the vertical pool engine is configured to do. The “generate a plurality of weighted sums for the received tensels” limitation is a mathematical calculation that can be performed by generating the weighted sums by hand using pen and paper. The “each weighted sum based on a different set of weights” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the weighted sums are based on. Under step 2A Prong 2, the “receive” limitations, as claimed under BRI, are additional elements that are insignificant extra-solution activity. The ‘receive’ in the context of the claim encompasses mere data gathering. None of the remaining additional elements regarding the generic computer components (i.e. the vertical pool engine, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim recites “receive a column of tensels”, “receive a column of tensels”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 9, it is directed to mental processes and/or mathematical concepts. The “wherein the vertical pool engine comprises” limitation is an evaluation mental process that can be performed by choosing what the vertical pool engine comprises. The “each multiplication unit configurable to” limitation is an evaluation mental process that can be performed by choosing what the multiplication units are configurable to do. The “multiply each of the received multiplication input elements” limitation is a mathematical calculation that can be performed by multiplying the inputs by hand using pen and paper. The “each summation unit configurable to” limitation is an evaluation mental process that can be performed by choosing what the summation units are configurable to do. The “generate a sum of the received summation input elements” limitation is a mathematical calculation that can be performed by generating the sum by hand using pen and paper. The “wherein when the control information identifies that an average pooling operation is to be performed on the input tensor, one of the plurality of summation units is configured to” limitation is an evaluation mental process that can be performed by choosing what the summation units are configured to do. The “generate the sum of the set of tensels” limitation is a mathematical calculation that can be performed by generating the sum by hand using pen and paper. The “wherein when the control information identifies that a depth-wise convolution operation is to be performed on the input tensor, at least two of the plurality of multiplication units are configured to” limitation is an evaluation mental process that can be performed by choosing what the multiplication units are configured to do. The “generate multiplication outputs based on a different set of weights” limitation is a mathematical calculation that can be performed by generating the multiplication outputs by hand using pen and paper. The “at least two of the plurality of summation units are configured to” limitation is an evaluation mental process that can be performed by choosing what the summation units are configured to do. The “generate a sum of the multiplication outputs” limitation is a mathematical calculation that can be performed by generating the sum by hand using pen and paper. Under step 2A Prong 2, the “receive” limitations, as claimed under BRI, are additional elements that are insignificant extra-solution activity. The ‘receive’ in the context of the claim encompasses mere data gathering. None of the remaining additional elements regarding the generic computer components (i.e. the vertical pool engine, the multiplication units, the summation units, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim recites “multiplication unit configurable to receive a set of multiplication input elements”, “each summation unit configurable to receive a set of summation input elements”, “receive a set tensels”, “receive a same set of tensels”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 10, it is directed to mental processes and/or mathematical concepts. The “wherein each set of weights corresponds to a column of a filter to be applied to a channel of the input tensor” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the sets of weights correspond to. Under steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 11, it is directed to mental processes and/or mathematical concepts. The “wherein the collector storage unit is a register” limitation is an evaluation mental process that can be performed by choosing what the collector storage unit is. The “a set of pointers identify the appropriate column outputs” limitation is an evaluation mental process that can be performed by choosing what the set of pointers do. Under step 2A Prong 2, none of the remaining additional elements regarding the generic computer components (i.e. the collector storage unit, the register, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 12, it is directed to mental processes and/or mathematical concepts. The “wherein each pool engine further comprises” limitation is an evaluation mental process that can be performed by choosing what the pool engine comprises. The “a post calculation engine configurable to” limitation is an evaluation mental process that can be performed by choosing what the post calculation engine is configurable to do. The “reformat an output of the reduction engine or the division engine” limitation is a mathematical calculation that can be performed by reformatting the output by hand using pen and paper. Under step 2A Prong 2, none of the remaining additional elements regarding the generic computer components (i.e. the pool engine, the post calculation engine, the reduction engine, the division engine, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 13, it is directed to mental processes and/or mathematical concepts. The “comprising a parameter storage unit” limitation is an evaluation mental process that can be performed by choosing what the hardware accelerator comprises. The “when the control information identifies that a depth-wise convolution operation is to be performed on the input tensor, the hardware accelerator is configured to” limitation is an evaluation mental process that can be performed by choosing what the hardware accelerator is configured to do. The “the parameters for performing the depth- wise convolution operation comprising” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the parameters comprise. The “the set of parameters for a channel comprising” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the parameters comprise. Under step 2A Prong 2, the “fetch” limitation, as claimed under BRI, is an additional elements that are insignificant extra-solution activity. The ‘fetch’ in the context of the claim encompasses mere data gathering. The “store” limitation, as claimed under BRI, is an additional elements that are insignificant extra-solution activity. The ‘store’ in the context of the claim encompasses mere data gathering. None of the remaining additional elements regarding the generic computer components (i.e. the parameter storage unit, the hardware accelerator, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim recites “fetch parameters for performing the depth-wise convolution operation”, “store the fetched parameters in the parameter storage unit”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 14, it is directed to mental processes and/or mathematical concepts. The “wherein the set of parameters for a channel further comprises a bias value” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the parameters comprise. Under steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 15, it is directed to mental processes and/or mathematical concepts. The “wherein, when the weights for a channel are in an affine fixed point number format, the set of parameters for a channel further comprise a weight zero point” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the parameters comprise. The “the hardware accelerator is configured to” limitation is an evaluation mental process that can be performed by choosing what the hardware accelerator is configured to do. Under step 2A Prong 2, none of the remaining additional elements regarding the generic computer components (i.e. the hardware accelerator, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 16, it is directed to mental processes and/or mathematical concepts. The “wherein the hardware accelerator is embodied on an integrated circuit” limitation is an evaluation mental process that can be performed by choosing how the hardware accelerator is embodied. Under step 2A Prong 2, none of the remaining additional elements regarding the generic computer components (i.e. the hardware accelerator, the integrated circuit, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 17, it is directed to mental processes and/or mathematical concepts. The “A neural network accelerator comprising the hardware accelerator” limitation is an evaluation mental process that can be performed by choosing what the neural network accelerator comprises. Under step 2A Prong 2, none of the remaining additional elements regarding the generic computer components (i.e. the hardware accelerator, the neural network accelerator, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 18, it is directed to mental processes and/or mathematical concepts. The “further comprising a convolution processing unit configurable to” limitation is an evaluation mental process that can be performed by choosing what the neural network accelerator comprises. The “perform one of a plurality of different convolution operations” limitation is a mathematical calculation that can be performed by performing the convolution operations by hand using pen and paper. Under step 2A Prong 2, none of the remaining additional elements regarding the generic computer components (i.e. the convolution processing unit, the neural network accelerator, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 19, it is directed to mental processes and/or mathematical concepts. The “a computer readable dataset description of the hardware accelerator as set forth in claim 1 that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture” limitation is an evaluation mental process that can be performed by choosing what the dataset description does. Under step 2A Prong 2, the “stored” limitation, as claimed under BRI, is an additional elements that are insignificant extra-solution activity. The ‘stored’ in the context of the claim encompasses mere data gathering. None of the remaining additional elements regarding the generic computer components (i.e. the non-transitory computer readable storage medium, the integrated circuit manufacturing system, the integrated circuit, the hardware accelerator, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim recites “having stored thereon a computer readable dataset description”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10, 12-14, and 16-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Holm et al. (US 20210295140 A1), as included in the IDS filed 05/10/2024, hereinafter Holm in view of Vantrease et al. (US 20190294413 A1) hereinafter Vantrease.
With regards to claim 1, Holm teaches A hardware accelerator to implement a configurable pooling processing unit, the hardware accelerator configured to: receive an input tensor comprising at least one channel, (Holm [0064]: An input or output data array (feature map) can be any suitable array of data elements, and can have any suitable size and number of dimensions… an (input) data array may comprise a three dimensional array of data elements)
each channel of the at least one channel comprising a plurality of tensels; (Holm [0064]: An input or output data array (feature map) can be any suitable array of data elements, and can have any suitable size and number of dimensions… an (input) data array may comprise a three dimensional array of data elements)
receive control information identifying one operation of a plurality of selectable operations to be performed on the input tensor, (Holm [0125]: As discussed above, in various embodiments, the combined convolution and pooling circuit comprises one or more circuits that are selectively activatable or selectively configurable to perform different operations. To facilitate this, in an embodiment, the combined convolution and pooling circuit comprises a control circuit that is configured to activate or select the appropriate configuration of a, and in an embodiment each, circuit element of the combined convolution and pooling circuit that can be controlled in this manner)
the plurality of selectable operations comprising a [depth-wise] convolution operation and one or more pooling operations; (Holm [0192]: FIG. 4 shows in more detail the improved neural network processing unit (NPU) 5 of the present embodiment which may be used in the system of FIG. 1. The NPU 5 comprises a fixed function hardware combined convolution and pooling engine (circuit) configured to perform both convolution and pooling operations)
perform, using a same set of hardware components of the hardware accelerator regardless of the identified operation, the identified operation on the input tensor to generate an output tensor (Holm [0192]: FIG. 4 shows in more detail the improved neural network processing unit (NPU) 5 of the present embodiment which may be used in the system of FIG. 1. The NPU 5 comprises a fixed function hardware combined convolution and pooling engine (circuit) configured to perform both convolution and pooling operations)
by performing one or more operations on blocks of tensels of each channel of the at least one channel of the input tensor; (Holm [0087]: an input data array (feature map) may be divided into non-overlapping pooling windows that each encompass a respective 2×2 block of data elements of the input data array (feature map). In this case, each value of the output data array (feature map) will be determined from the values for a respective 2×2 block of data elements of the input data array (feature map), and thus the pooling operation will operate to reduce the size of the input data array (feature map) in two dimensions by a factor of two)
and output the output tensor (Holm [0067]: the combined convolution and pooling circuit can output processed output data array (feature map) values in any suitable manner).
Holm fails to teach a depth-wise [convolution operation].
However, Vantrease teaches a depth-wise [convolution operation] (Vantrease [0043]: First convolution layer 215 may perform convolutions on input image 210 using multiple filters to generate multiple output matrices (or feature maps) 220. The number of filters used may be referred to as the depth of the convolution layer).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Holm with the depth-wise convolution as taught by Vantrease. One of ordinary skill in the art would be motivated to make this combination to reduce the size of the data used for the computation and improve the efficiency of the computation during inference as taught by Vantrease (Vantrease [0017]). Also, this would allow for more data to be processed, increasing efficiency.
With regards to claim 2, Holm in view of Vantrease teaches all of the limitations of claim 1 above. Holm further teaches comprising one or more pool engines, (Holm [0158]: The data processing system also comprises a central processing unit (CPU) 3, graphics processing unit (GPU) 4 and a neural network processing unit (accelerator) (NPU) 5; (the NPU being the pool engine))
each pool engine configurable to receive tensels of a channel of the input tensor and generate one of a plurality of different types of channel outputs, (Holm [0064]: An input or output data array (feature map) can be any suitable array of data elements, and can have any suitable size and number of dimensions… an (input) data array may comprise a three dimensional array of data elements; Holm [0067]: the combined convolution and pooling circuit can output processed output data array (feature map) values in any suitable manner)
the plurality of different types of channel outputs comprising a [depth-wise] convolution channel output and one of one or more selectable pooling operation channel outputs (Holm [0192]: FIG. 4 shows in more detail the improved neural network processing unit (NPU) 5 of the present embodiment which may be used in the system of FIG. 1. The NPU 5 comprises a fixed function hardware combined convolution and pooling engine (circuit) configured to perform both convolution and pooling operations).
Holm fails to teach a depth-wise [convolution operation].
However, Vantrease teaches a depth-wise [convolution operation] (Vantrease [0043]: First convolution layer 215 may perform convolutions on input image 210 using multiple filters to generate multiple output matrices (or feature maps) 220. The number of filters used may be referred to as the depth of the convolution layer).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Holm in view of Vantrease with the depth-wise convolution as taught by Vantrease. One of ordinary skill in the art would be motivated to make this combination to reduce the size of the data used for the computation and improve the efficiency of the computation during inference as taught by Vantrease (Vantrease [0017]). Also, this would allow for more data to be processed, increasing efficiency.
With regards to claim 3, Holm in view of Vantrease teaches all of the limitations of claim 2 above. Holm further teaches wherein the one or more pooling operations comprises an average pooling operation (Holm [0037]: the combined convolution and pooling circuit performing at least one of a convolution operation, an average pooling operation and a maximum pooling operation for the neural network executing on the neural network processor).
With regards to claim 4, Holm in view of Vantrease teaches all of the limitations of claim 3 above. Holm further teaches wherein each of the one or more pool engines comprises: a reduction engine configurable to generate, for a block of tensels of a channel of the input tensor, one of a plurality of types of block outputs, (Holm [0158]: The data processing system also comprises a central processing unit (CPU) 3, graphics processing unit (GPU) 4 and a neural network processing unit (accelerator) (NPU) 5; Holm [0064]: An input or output data array (feature map) can be any suitable array of data elements, and can have any suitable size and number of dimensions… an (input) data array may comprise a three dimensional array of data elements; Holm [0067]: the combined convolution and pooling circuit can output processed output data array (feature map) values in any suitable manner)
the plurality of types of block outputs comprising a sum of tensels in the block and a weighted sum of tensels in the block; (Holm [0091]: Accordingly, the combined convolution and pooling circuit performing an average pooling operation in an embodiment comprises, for each output value of an output data array (feature map), the add circuit accumulating (summing) input feature map data values in the storage; Holm [0079]: accordingly, the combined convolution and pooling circuit performing a convolution operation in an embodiment comprises, for each output value of an output data array (feature map), performing a multiply-accumulate operation by the multiply circuit determining products of corresponding input feature map and convolution kernel weight values, and the add circuit accumulating (summing) the products determined by the multiply circuit in the storage)
and a division engine configurable to selectively perform a division operation on the block output generated by the reduction engine; (Holm [0091]: the divisor circuit determining a divisor value to use to determine a mean of the input feature map data values accumulated (summed) in the storage by the add circuit)
wherein when the control information identifies that an average pooling operation is to be performed on the input tensor, the reduction engine is configured to generate a sum of tensels in the block (Holm [0091]: Accordingly, the combined convolution and pooling circuit performing an average pooling operation in an embodiment comprises, for each output value of an output data array (feature map), the add circuit accumulating (summing) input feature map data values in the storage, and the divisor circuit determining a divisor value to use to determine a mean of the input feature map data values accumulated (summed) in the storage by the add circuit)
and the division engine is enabled to divide the block output generated by the reduction engine by a number of tensels in the block; (Holm [0091]: Accordingly, the combined convolution and pooling circuit performing an average pooling operation in an embodiment comprises, for each output value of an output data array (feature map), the add circuit accumulating (summing) input feature map data values in the storage, and the divisor circuit determining a divisor value to use to determine a mean of the input feature map data values accumulated (summed) in the storage by the add circuit)
and wherein when the control information identifies that a [depth-wise] convolution operation is to be performed on the input tensor, the reduction engine is configured to generate a weighted sum for the block and the division engine is disabled (Holm [0079]: Accordingly, the combined convolution and pooling circuit performing a convolution operation in an embodiment comprises, for each output value of an output data array (feature map), performing a multiply-accumulate operation by the multiply circuit determining products of corresponding input feature map and convolution kernel weight values, and the add circuit accumulating (summing) the products determined by the multiply circuit in the storage; Holm [125]: As discussed above, in various embodiments, the combined convolution and pooling circuit comprises one or more circuits that are selectively activatable or selectively configurable to perform different operations. To facilitate this, in an embodiment, the combined convolution and pooling circuit comprises a control circuit that is configured to activate or select the appropriate configuration of a, and in an embodiment each, circuit element of the combined convolution and pooling circuit that can be controlled in this manner; Holm Fig. 6: shows that during a convolution operation the divisor circuit is disabled).
Holm fails to teach a depth-wise [convolution operation].
However, Vantrease teaches a depth-wise [convolution operation] (Vantrease [0043]: First convolution layer 215 may perform convolutions on input image 210 using multiple filters to generate multiple output matrices (or feature maps) 220. The number of filters used may be referred to as the depth of the convolution layer).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Holm in view of Vantrease with the depth-wise convolution as taught by Vantrease. One of ordinary skill in the art would be motivated to make this combination to reduce the size of the data used for the computation and improve the efficiency of the computation during inference as taught by Vantrease (Vantrease [0017]). Also, this would allow for more data to be processed, increasing efficiency.
With regards to claim 5, Holm in view of Vantrease teaches all of the limitations of claim 4 above. Holm further teaches wherein each block of tensels comprises one or more rows of tensels and one or more columns of tensels, (Holm [0064]: An input or output data array (feature map) can be any suitable array of data elements, and can have any suitable size and number of dimensions… an (input) data array may comprise a three dimensional array of data elements)
and the reduction engine is configured to generate a block output by generating [column] outputs and generating the block output from one or more [column] outputs (Holm [0067]: the combined convolution and pooling circuit can output processed output data array (feature map) values in any suitable manner).
Holm fails to teach generating column outputs and one or more column outputs.
However, Vantrease teaches generating column outputs (Vantrease [0077]: The PE at the bottom row of each column may generate a weighted sum of input data elements received by all PEs in the column)
one or more column outputs (Vantrease [0077]: The PE at the bottom row of each column may generate a weighted sum of input data elements received by all PEs in the column).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Holm in view of Vantrease with the column outputs as taught by Vantrease. One of ordinary skill in the art would be motivated to make this combination to reduce the size of the data used for the computation and improve the efficiency of the computation during inference as taught by Vantrease (Vantrease [0017]). Also, this would allow for the data to be processed in parallel, increasing efficiency.
With regards to claim 6, Holm in view of Vantrease teaches all of the limitations of claim 5 above. Holm further teaches wherein: when the control information identifies that an average pooling operation is to be performed on the input tensor, the reduction engine is configured to generate a sum [for each column] of a block of tensels, (Holm [0091]: Accordingly, the combined convolution and pooling circuit performing an average pooling operation in an embodiment comprises, for each output value of an output data array (feature map), the add circuit accumulating (summing) input feature map data values in the storage, and the divisor circuit determining a divisor value to use to determine a mean of the input feature map data values accumulated (summed) in the storage by the add circuit)
and generate the sum for the block of tensels by summing appropriate [column] sums, (Holm [0091]: Accordingly, the combined convolution and pooling circuit performing an average pooling operation in an embodiment comprises, for each output value of an output data array (feature map), the add circuit accumulating (summing) input feature map data values in the storage, and the divisor circuit determining a divisor value to use to determine a mean of the input feature map data values accumulated (summed) in the storage by the add circuit)
and when the control information identifies that a [depth-wise] convolution operation is to be performed on the input tensor, the reduction engine is configured to generate a weighted sum [for each column] of a block of tensels, (Holm [0079]: Accordingly, the combined convolution and pooling circuit performing a convolution operation in an embodiment comprises, for each output value of an output data array (feature map), performing a multiply-accumulate operation by the multiply circuit determining products of corresponding input feature map and convolution kernel weight values, and the add circuit accumulating (summing) the products determined by the multiply circuit in the storage)
and generate the weighted sum for the block by summing appropriate [column] weighted sums (Holm [0079]: Accordingly, the combined convolution and pooling circuit performing a convolution operation in an embodiment comprises, for each output value of an output data array (feature map), performing a multiply-accumulate operation by the multiply circuit determining products of corresponding input feature map and convolution kernel weight values, and the add circuit accumulating (summing) the products determined by the multiply circuit in the storage).
Holm fails to teach generate a sum for each column of a block of tensels, summing appropriate column sums, a depth-wise [convolution operation], a sum for each column of a block of tensels, and summing appropriate column weighted sums.
However, Vantrease teaches generate a sum for each column of a block of tensels (Vantrease [0077]: The PE at the bottom row of each column may generate a weighted sum of input data elements received by all PEs in the column)
summing appropriate column sums (Vantrease [0077]: The PE at the bottom row of each column may generate a weighted sum of input data elements received by all PEs in the column)
a depth-wise [convolution operation] (Vantrease [0043]: First convolution layer 215 may perform convolutions on input image 210 using multiple filters to generate multiple output matrices (or feature maps) 220. The number of filters used may be referred to as the depth of the convolution layer)
a sum for each column of a block of tensels (Vantrease [0077]: The PE at the bottom row of each column may generate a weighted sum of input data elements received by all PEs in the column)
summing appropriate column weighted sums (Vantrease [0077]: The PE at the bottom row of each column may generate a weighted sum of input data elements received by all PEs in the column).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Holm in view of Vantrease with the column sums and depth wise convolution as taught by Vantrease. One of ordinary skill in the art would be motivated to make this combination to reduce the size of the data used for the computation and improve the efficiency of the computation during inference as taught by Vantrease (Vantrease [0017]). Also, this would allow for the data to be processed in parallel, increasing efficiency.
With regards to claim 7, Holm in view of Vantrease teaches all of the limitations of claim 4 above. Holm further teaches wherein the reduction engine comprises: a [vertical] pool engine configurable to receive [a column] of tensels and generate one of a plurality of types of [column] outputs for that [column]; (Holm [0158]: The data processing system also comprises a central processing unit (CPU) 3, graphics processing unit (GPU) 4 and a neural network processing unit (accelerator) (NPU) 5; Holm [0064]: An input or output data array (feature map) can be any suitable array of data elements, and can have any suitable size and number of dimensions… an (input) data array may comprise a three dimensional array of data elements; Holm [0067]: the combined convolution and pooling circuit can output processed output data array (feature map) values in any suitable manner)
a collector storage unit configured to temporarily store the [column] outputs generated by the [vertical] pool engine; (Holm [0079]: An accumulated (summed) value in the storage is then in an embodiment used for the corresponding output value for the output data array (feature map), in an embodiment by the output circuit writing out the accumulated value from the storage to an output data array in (the) memory)
and a [horizontal] pool engine configured to generate a block output from appropriate [column] outputs stored in the collector storage unit (Holm [0079]: An accumulated (summed) value in the storage is then in an embodiment used for the corresponding output value for the output data array (feature map), in an embodiment by the output circuit writing out the accumulated value from the storage to an output data array in (the) memory).
Holm fails to teach a vertical pool engine, receive a column of tensels, column outputs for that column, the column outputs generated by the vertical pool engine, a horizontal pool engine, and appropriate column outputs.
However, Vantrease teaches a vertical pool engine (Vantrease [0077]: the PE may also receive a partial weighted sum from the preceding PE in the same column... The PE at the bottom row of each column may generate a weighted sum of input data elements received by all PEs in the column)
receive a column of tensels (Vantrease [0077]: the PE may also receive a partial weighted sum from the preceding PE in the same column... The PE at the bottom row of each column may generate a weighted sum of input data elements received by all PEs in the column)
column outputs for that column (Vantrease [0077]: the PE may also receive a partial weighted sum from the preceding PE in the same column... The PE at the bottom row of each column may generate a weighted sum of input data elements received by all PEs in the column)
the column outputs generated by the vertical pool engine (Vantrease [0077]: the PE may also receive a partial weighted sum from the preceding PE in the same column... The PE at the bottom row of each column may generate a weighted sum of input data elements received by all PEs in the column; Vantrease [0078]: The updated partial sum may be propagated down along each column until it is output by PE 620d on the Mth row at the Mth clock cycle to an output buffer)
a horizontal pool engine (Vantrease [0080]: Referring back to FIG. 5, post-processor 528 may be configured to perform post-processing on the outputs of computing engine 524 (which may act as a neural network layer, such as a convolution layer or fully-connected layer) that may be stored in output buffer 526 to generate final outputs for the neural network layer)
appropriate column outputs (Vantrease [0077]: the PE may also receive a partial weighted sum from the preceding PE in the same column... The PE at the bottom row of each column may generate a weighted sum of input data elements received by all PEs in the column; Vantrease [0080]: Referring back to FIG. 5, post-processor 528 may be configured to perform post-processing on the outputs of computing engine 524 (which may act as a neural network layer, such as a convolution layer or fully-connected layer) that may be stored in output buffer 526 to generate final outputs for the neural network layer).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Holm in view of Vantrease with the column outputs and the vertical and horizontal pool engines as taught by Vantrease. One of ordinary skill in the art would be motivated to make this combination to reduce the size of the data used for the computation and improve the efficiency of the computation during inference as taught by Vantrease (Vantrease [0017]). Also, this would allow for the data to be processed in parallel, increasing efficiency.
With regards to claim 8, Holm in view of Vantrease teaches all of the limitations of claim 7 above. Holm further teaches wherein: when the control information identifies that an average pooling operation is to be performed on the input tensor, the [vertical] pool engine is configured to receive a [column] of tensels in a block and generate a sum of the received tensels; (Holm [0091]: Accordingly, the combined convolution and pooling circuit performing an average pooling operation in an embodiment comprises, for each output value of an output data array (feature map), the add circuit accumulating (summing) input feature map data values in the storage, and the divisor circuit determining a divisor value to use to determine a mean of the input feature map data values accumulated (summed) in the storage by the add circuit)
and when the control information identifies that a [depth-wise] convolution operation is to be performed on the input tensor, the [vertical] pool engine is configured to receive a [column] of tensels in a block, and generate a plurality of weighted sums for the received tensels, (Holm [0079]: Accordingly, the combined convolution and pooling circuit performing a convolution operation in an embodiment comprises, for each output value of an output data array (feature map), performing a multiply-accumulate operation by the multiply circuit determining products of corresponding input feature map and convolution kernel weight values, and the add circuit accumulating (summing) the products determined by the multiply circuit in the storage).
Holm fails to teach a vertical pool engine, receive a column of tensels, a depth-wise [convolution operation], the vertical pool engine, receive a column of tensels, and each weighted sum based on a different set of weights.
However, Vantrease teaches a vertical pool engine (Vantrease [0077]: the PE may also receive a partial weighted sum from the preceding PE in the same column... The PE at the bottom row of each column may generate a weighted sum of input data elements received by all PEs in the column)
receive a column of tensels (Vantrease [0077]: the PE may also receive a partial weighted sum from the preceding PE in the same column... The PE at the bottom row of each column may generate a weighted sum of input data elements received by all PEs in the column)
a depth-wise [convolution operation] (Vantrease [0043]: First convolution layer 215 may perform convolutions on input image 210 using multiple filters to generate multiple output matrices (or feature maps) 220. The number of filters used may be referred to as the depth of the convolution layer)
the vertical pool engine (Vantrease [0077]: the PE may also receive a partial weighted sum from the preceding PE in the same column... The PE at the bottom row of each column may generate a weighted sum of input data elements received by all PEs in the column)
receive a column of tensels (Vantrease [0077]: the PE may also receive a partial weighted sum from the preceding PE in the same column... The PE at the bottom row of each column may generate a weighted sum of input data elements received by all PEs in the column)
each weighted sum based on a different set of weights (Vantrease [0079]: In some implementations, each column of computing engine 600 may correspond to a processing node of a neural network layer, and may apply a different set of weights {w.sub.i} to generate a different weighted sum).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Holm in view of Vantrease with the column tensels, the vertical pool engine, the depth-wise convolution, and the different weights as taught by Vantrease. One of ordinary skill in the art would be motivated to make this combination to reduce the size of the data used for the computation and improve the efficiency of the computation during inference as taught by Vantrease (Vantrease [0017]). Also, this would allow for the data to be processed in parallel, increasing efficiency.
With regards to claim 9, Holm in view of Vantrease teaches all of the limitations of claim 7 above. Holm further teaches wherein the [vertical] pool engine comprises: a [plurality] of multiplication units, (Holm [0079]: Accordingly, the combined convolution and pooling circuit performing a convolution operation in an embodiment comprises, for each output value of an output data array (feature map), performing a multiply-accumulate operation by the multiply circuit determining products of corresponding input feature map and convolution kernel weight values, and the add circuit accumulating (summing) the products determined by the multiply circuit in the storage; Holm Fig. 6: shows the multiply circuit)
each multiplication unit configurable to receive a set of multiplication input elements and multiply each of the received multiplication input elements with a corresponding weight to generate a multiplication output; (Holm [0079]: Accordingly, the combined convolution and pooling circuit performing a convolution operation in an embodiment comprises, for each output value of an output data array (feature map), performing a multiply-accumulate operation by the multiply circuit determining products of corresponding input feature map and convolution kernel weight values, and the add circuit accumulating (summing) the products determined by the multiply circuit in the storage)
and a [plurality] of summation units, (Holm [0079]: Accordingly, the combined convolution and pooling circuit performing a convolution operation in an embodiment comprises, for each output value of an output data array (feature map), performing a multiply-accumulate operation by the multiply circuit determining products of corresponding input feature map and convolution kernel weight values, and the add circuit accumulating (summing) the products determined by the multiply circuit in the storage; Holm Fig. 6: shows the add circuit)
each summation unit configurable to receive a set of summation input elements and generate a sum of the received summation input elements to generate a summation output; (Holm [0079]: Accordingly, the combined convolution and pooling circuit performing a convolution operation in an embodiment comprises, for each output value of an output data array (feature map), performing a multiply-accumulate operation by the multiply circuit determining products of corresponding input feature map and convolution kernel weight values, and the add circuit accumulating (summing) the products determined by the multiply circuit in the storage)
wherein when the control information identifies that an average pooling operation is to be performed on the input tensor, one of the [plurality] of summation units is configured to receive a set tensels in [a column] and generate the sum of the set of tensels; (Holm [0091]: Accordingly, the combined convolution and pooling circuit performing an average pooling operation in an embodiment comprises, for each output value of an output data array (feature map), the add circuit accumulating (summing) input feature map data values in the storage, and the divisor circuit determining a divisor value to use to determine a mean of the input feature map data values accumulated (summed) in the storage by the add circuit).
Holm fails to teach a vertical pool engine, a plurality of multiplication units, a plurality of summation units, the plurality of summation units, a set tensels in a column, and wherein when the control information identifies that a depth-wise convolution operation is to be performed on the input tensor, at least two of the plurality of multiplication units are configured to receive a same set of tensels in a column and generate multiplication outputs based on a different set of weights, and at least two of the plurality of summation units are configured to generate a sum of the multiplication outputs for one of the at least two multiplication units.
However, Vantrease teaches a vertical pool engine (Vantrease [0077]: the PE may also receive a partial weighted sum from the preceding PE in the same column... The PE at the bottom row of each column may generate a weighted sum of input data elements received by all PEs in the column)
a plurality of multiplication units (Vantrease [0077]: Each PE may include a multiplier 623... the PE may also receive a partial weighted sum from the preceding PE in the same column... The PE at the bottom row of each column may generate a weighted sum of input data elements received by all PEs in the column)
a plurality of summation units (Vantrease [0077]: The PE at the bottom row of each column may generate a weighted sum of input data elements received by all PEs in the column)
the plurality of summation units (Vantrease [0077]: The PE at the bottom row of each column may generate a weighted sum of input data elements received by all PEs in the column)
a set tensels in a column (Vantrease [0077]: the PE may also receive a partial weighted sum from the preceding PE in the same column... The PE at the bottom row of each column may generate a weighted sum of input data elements received by all PEs in the column)
and wherein when the control information identifies that a depth-wise convolution operation is to be performed on the input tensor, at least two of the plurality of multiplication units are configured to receive a same set of tensels in a column and generate multiplication outputs based on a different set of weights, (Vantrease [0079]: In some implementations, each column of computing engine 600 may correspond to a processing node of a neural network layer, and may apply a different set of weights {w.sub.i} to generate a different weighted sum)
and at least two of the plurality of summation units are configured to generate a sum of the multiplication outputs for one of the at least two multiplication units (Vantrease [0077]: The PE at the bottom row of each column may generate a weighted sum of input data elements received by all PEs in the column).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Holm in view of Vantrease with the column tensels, the vertical pool engine, the depth-wise convolution, and the different weights as taught by Vantrease. One of ordinary skill in the art would be motivated to make this combination to reduce the size of the data used for the computation and improve the efficiency of the computation during inference as taught by Vantrease (Vantrease [0017]). Also, this would allow for the data to be processed in parallel, increasing efficiency.
With regards to claim 10, Holm in view of Vantrease teaches all of the limitations of claim 9 above. Holm further teaches wherein each set of weights corresponds to a [column] of a filter to be applied to a channel of the input tensor (Holm [0077]: A (discrete) convolution operation between an input data array (feature map) and a convolution (filter) kernel).
Holm fails to teach a column of a filter.
However, Vantrease teaches a column of a filter (Vantrease [0077]: Each PE may include a multiplier 623... the PE may also receive a partial weighted sum from the preceding PE in the same column... The PE at the bottom row of each column may generate a weighted sum of input data elements received by all PEs in the column).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Holm in view of Vantrease with the column weights as taught by Vantrease. One of ordinary skill in the art would be motivated to make this combination to reduce the size of the data used for the computation and improve the efficiency of the computation during inference as taught by Vantrease (Vantrease [0017]). Also, this would allow for the data to be processed in parallel, increasing efficiency.
With regards to claim 12, Holm in view of Vantrease teaches all of the limitations of claim 4 above. Holm further teaches wherein each pool engine further comprises a post calculation engine configurable to reformat an output of the reduction engine or the division engine (Holm [0205]: The combined convolution and pooling engine further comprises an output scale circuit 47 (output circuit). The output scale circuit 47 is configured to read data values in accumulators 46, scale the read values to a desired number of bits, and write out the result to an output feature map in the external memory).
With regards to claim 13, Holm in view of Vantrease teaches all of the limitations of claim 1 above. Holm further teaches and when the control information identifies that a [depth-wise] convolution operation is to be performed on the input tensor, the hardware accelerator is configured to fetch parameters for performing the [depth-wise] convolution operation and [store the fetched parameters in the parameter storage unit,] (Holm [0194]: the combined convolution and pooling engine comprises an input feature map read circuit 41 (input circuit) that is configured to read, from the external memory 8, data of an input feature map)
the parameters for performing the [depth-wise] convolution operation comprising a set of parameters for each channel of the at least one channel of the input tensor, the set of parameters for a channel comprising a set of weights (Holm [0079]: Accordingly, the combined convolution and pooling circuit performing a convolution operation in an embodiment comprises, for each output value of an output data array (feature map), performing a multiply-accumulate operation by the multiply circuit determining products of corresponding input feature map and convolution kernel weight values, and the add circuit accumulating (summing) the products determined by the multiply circuit in the storage).
Holm fails to teach comprising a parameter storage unit, a depth-wise convolution operation, store the fetched parameters in the parameter storage unit, the depth-wise convolution operation.
However, Vantrease teaches comprising a parameter storage unit, (Vantrease [0117]: the integer inputs may be stored in a storage device, such as a buffer or a volatile or non-volatile memory device)
a depth-wise convolution operation (Vantrease [0043]: First convolution layer 215 may perform convolutions on input image 210 using multiple filters to generate multiple output matrices (or feature maps) 220. The number of filters used may be referred to as the depth of the convolution layer)
store the fetched parameters in the parameter storage unit, (Vantrease [0117]: the integer inputs may be stored in a storage device, such as a buffer or a volatile or non-volatile memory device)
the depth-wise convolution operation (Vantrease [0043]: First convolution layer 215 may perform convolutions on input image 210 using multiple filters to generate multiple output matrices (or feature maps) 220. The number of filters used may be referred to as the depth of the convolution layer).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Holm in view of Vantrease with the depth-wise convolution and parameter storage as taught by Vantrease. One of ordinary skill in the art would be motivated to make this combination to reduce the size of the data used for the computation and improve the efficiency of the computation during inference as taught by Vantrease (Vantrease [0017]). Also, this would allow for the data to be stored on the chip, increasing the speed of the system.
With regards to claim 14, Holm in view of Vantrease teaches all of the limitations of claim 13 above. Holm fails to teach wherein the set of parameters for a channel further comprises a bias value.
However, Vantrease teaches wherein the set of parameters for a channel further comprises a bias value (Vantrease [0029]: In the example shown in FIG. 1, node 112 may be a bias node having a value of 1).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Holm in view of Vantrease with the bias as taught by Vantrease. One of ordinary skill in the art would be motivated to make this combination to reduce the size of the data used for the computation and improve the efficiency of the computation during inference as taught by Vantrease (Vantrease [0017]).
With regards to claim 16, Holm in view of Vantrease teaches all of the limitations of claim 1 above. Holm further teaches wherein the hardware accelerator is embodied on an integrated circuit (Holm [0161]: The ISP 2, CPU 3, GPU 4, NPU 5, interconnect 6 and memory controller 7, may be provided as part of a system-on-chip 9).
With regards to claim 17, Holm in view of Vantrease teaches all of the limitations of claim 1 above. Holm further teaches A neural network accelerator comprising the hardware accelerator as set forth in claim 1 (Holm [0158]: FIG. 1 shows a data processing system 10 which may be used to perform neural network processing. The data processing system comprises an image sensor 1 which may be operable to provide image data to an image signal processor (ISP) 2. The image signal processor (ISP) 2 may process the image data to provide data that is suitable for use as input data for neural network processing. The data processing system also comprises a central processing unit (CPU) 3, graphics processing unit (GPU) 4 and a neural network processing unit (accelerator) (NPU) 5).
With regards to claim 18, Holm in view of Vantrease teaches all of the limitations of claim 17 above. Holm further teaches further comprising a convolution processing unit configurable to perform one of a plurality of different convolution operations (Holm [0192]: FIG. 4 shows in more detail the improved neural network processing unit (NPU) 5 of the present embodiment which may be used in the system of FIG. 1. The NPU 5 comprises a fixed function hardware combined convolution and pooling engine (circuit) configured to perform both convolution and pooling operations).
Claim 20 is directed to a method that implements the same or similar features as the system of claim 1 and is therefore rejected for at least the same reasons therein.
Claims 11 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Holm in view of Vantrease further in view of Sriram et al. (US 20220044114 A1) hereinafter Sriram.
With regards to claim 11, Holm in view of Vantrease teaches all of the limitations of claim 7 above. Holm further teaches wherein the collector storage unit is a register, (Holm [0202]: The combined convolution and pooling engine further comprises accumulators (registers) 46 (storage) that can store data values being processed by the combined convolution and pooling engine).
Holm fails to teach and a set of pointers identify the appropriate column outputs in the register to generate a block output.
However, Vantrease teaches [and a set of pointers] identify the appropriate column outputs in the register to generate a block output (Vantrease [0077]: Each PE may include a multiplier 623... the PE may also receive a partial weighted sum from the preceding PE in the same column... The PE at the bottom row of each column may generate a weighted sum of input data elements received by all PEs in the column).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Holm in view of Vantrease with the column outputs as taught by Vantrease. One of ordinary skill in the art would be motivated to make this combination to reduce the size of the data used for the computation and improve the efficiency of the computation during inference as taught by Vantrease (Vantrease [0017]). Also, this would allow for the data to be processed in parallel, increasing efficiency.
Holm in view of Vantrease fails to teach and a set of pointers.
However, Sriram teaches and a set of pointers (Sriram [0292]: may store current register values to a designated region in memory (e.g., identified by a context pointer))
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Holm in view of Vantrease with the pointers as taught by Sriram. One of ordinary skill in the art would be motivated to make this combination because it would allow for the outputs to be stored in the registers, increasing the efficiency of the system.
With regards to claim 19, Holm in view of Vantrease teaches all of the limitations of claim 1 above. Holm further teaches A non-transitory computer readable storage medium having stored thereon a computer readable [dataset description of the hardware accelerator as set forth in claim 1 that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the hardware accelerator] (Holm [0156]: The technology described herein may accordingly suitably be embodied as a computer program product for use with a computer system. Such an implementation may comprise a series of computer readable instructions fixed on a tangible, non-transitory medium, such as a computer readable medium, for example, diskette, CD ROM, ROM, RAM, flash memory, or hard disk).
Holm fails to teach [A non-transitory computer readable storage medium having stored thereon a computer readable] dataset description of the hardware accelerator as set forth in claim 1 that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the hardware accelerator (Sriram [0177]: GPU(s) 1008 could be fabricated on Fin field-effect transistor (“FinFET”) circuitry).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Holm in view of Vantrease with the manufacture of the integrated circuit as taught by Sriram. One of ordinary skill in the art would be motivated to make this combination because it would allow for the circuits to be manufactured, increasing the efficiency of the system as multiple chips could work in parallel. Also, they may be power-optimized for best performance in automotive and embedded use cases as taught by Sriram (Sriram [0177]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Holm in view of Vantrease further in view of Desoli et al. (US 20230062910 A1) hereinafter Desoli further in view of Ha et al. (US 20210182594 A1) hereinafter Ha.
With regards to claim 15, Holm in view of Vantrease teaches all of the limitations of claim 13 above. Holm further teaches wherein, when the weights for a channel are in an [affine fixed point number format, the set of parameters for a channel further comprise a weight zero point,] (Holm [0079]: Accordingly, the combined convolution and pooling circuit performing a convolution operation in an embodiment comprises, for each output value of an output data array (feature map), performing a multiply-accumulate operation by the multiply circuit determining products of corresponding input feature map and convolution kernel weight values, and the add circuit accumulating (summing) the products determined by the multiply circuit in the storage).
Holm fails to teach [wherein, when the weights for a channel are in an] affine fixed point number format, the set of parameters for a channel further comprise a weight zero point.
However, Desoli teaches [wherein, when the weights for a channel are in an] affine fixed point number format, the set of parameters for a channel further comprise a weight zero point, (Desoli [0033]: Various quantization formats can be utilized for the input data 102. One possible quantization format is scale/offset format; (the offset being zero point)).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Holm in view of Vantrease with the affine fixed point with the weight zero point as taught by Desoli. One of ordinary skill in the art would be motivated to make this combination because in some cases, a layer, process, or unit of neural network may more efficiently process data if quantization factors such as scaling and offset are changed from a previous layer. In some cases, a layer, process, or unit of a neural network may more efficiently process data if an entirely different quantization format is utilized as taught by Desoli (Desoli [0004]).
Holm in view of Desoli fails to teach and the hardware accelerator is configured to remove the weight zero point from each weight associated with that channel prior to performing the depth-wise convolution operation.
However, Ha teaches and the hardware accelerator is configured to remove the weight zero point from each weight associated with that channel prior to performing the depth-wise convolution operation (Ha [0017]: remove offsets in the weight kernels).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Holm in view of Vantrease further in view of Desoli with removing the zero point as taught by Ha. One of ordinary skill in the art would be motivated to make this combination because low-power and high-performance systems, such as mobile or Internet of Things (IoT) devices, typically have limited resources, and thus typically require technologies that reduce energy consumption required to process a large amount of data as taught by Ha (Ha [0004]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jakob O Gudas whose telephone number is (571)272-0695. The examiner can normally be reached Monday-Thursday: 7:30AM-5:00PM Friday: 7:30AM-4:00PM.
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/J.O.G./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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