DETAILED ACTION
Claims 1-16 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-16 are rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter.
Claim 1 rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. As analyzed under the current 2019 Revised Patent Subject Matter Eligibility Guidance; first, the claim is directed to a proper statutory category. Second, under step 2A prong 1, the claim is directed to abstract ideas; specifically mathematical concepts such as mathematical matrix calculations and/or mental processes that could be performed by pen and paper. They are highlighted below (underlined, italicized):
1. An apparatus comprising a compute engine configured to perform self-attention computations by delaying performance of a division operation of a softmax computation, the performance of the self-attention computations comprising:
iteratively computing a first matrix multiplication of a given row vector of a first matrix and each column vector of a second matrix while determining a first scalar element representing a maximum value of the iterative first matrix multiplications;
iteratively subtracting a corresponding determined first scaler element from a result of each computed first matrix multiplication and computing an elementwise exponential function based on a result of the subtraction operation to generate a plurality of elements of a given row vector of a fourth matrix;
iteratively computing a second matrix multiplication of a given row vector of the fourth matrix and each column vector of a third matrix while summing the given row vectors of the fourth matrix to obtain a second scalar; and
computing a row vector of an output matrix based on results of the second matrix multiplications.
As currently recited, under the broadest reasonable interpretation, these highlighted limitations can be interpreted as mathematical concepts and/or mental processes such as mathematical matrix calculations and/or mental processes that could be performed by pen and paper.
Next, under step 2A prong 2, are there additional elements or combination of elements that apply or integrate the judicial exception into a practical application? The additional limitation of “apparatus comprising a compute engine” is recited at a high-level of generality (i.e., generic machine) such that it amounts no more than mere instructions to apply the exception using a generic computer component. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
Lastly, under step 2B are there limitations indicative of an inventive concept (i.e. significantly more)? No, the additional limitations do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements are no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. See MPEP 2106.05(f). The claim is not patent eligible.
5. Method claims 14 and 15 are rejected for similar reasons as presented above with reference to claim 1 as they recite the similar abstract ideas found in claim 1 above. Thus, the claims are directed to the same abstract ideas without reciting meaningful limitations that are sufficient to ensure that the claim amounts to significantly more than the abstract idea itself.
Dependent claims 2-13 and 16 are rejected under 35 U.S.C. 101 as non- statutory for at least the reason stated above, as they do not add any feature or subject matter that would solve the non-statutory deficiencies of the independent claims from which they depend. The claims depend from claim 1 and 15, but fail to include any additional elements sufficient to amount to significantly more than the judicial exception. The claims recite further limitations that abstract mathematical concepts and/or mental steps without reciting any additional limitations that make the claim any less abstract or that impose meaningful limits on practicing the abstract idea. Accordingly, the claims are not patent-eligible under 35 U.S.C. 101.
Claim Rejections - 35 USC § 102
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
7. Claim(s) 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Redfern et al (hereafter Redfern)(US Pub. 20180246855).
8. As to claim 14, Redfern discloses a method comprising:
pushing a given row vector of a first matrix ([0140]-[0145] row vector of matrix);
pushing a column vector of a second matrix on each of a plurality of clock cycles ([0140]-[0147] column vector); and
pushing a column vector of a third matrix on each of the plurality of clock cycles after a given delay ([0260] and p0278]-[0279]).
Allowable Subject Matter
9. Claims 1-13 and 15-16 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 101, set forth in this Office action.
10. The following is a statement of reasons for the indication of allowable subject matter:
The claims recite at least iteratively subtracting a corresponding determined first scaler element from a result of each computed first matrix multiplication and computing an elementwise exponential function based on a result of the subtraction operation to generate a plurality of elements of a given row vector of a fourth matrix;
iteratively computing a second matrix multiplication of a given row vector of the fourth matrix and each column vector of a third matrix while summing the given row vectors of the fourth matrix to obtain a second scalar; and
computing a row vector of an output matrix based on results of the second matrix multiplications.
The closest prior art of record US Pub. 20180246855 teaches hardware implementing matrix multiplication of the forms C=A*B and C=A*B+D wherein the data widths of the A-multiplier-matrix (AMM), B-multiplicand-matrix (BMM), C-product-matrix (CPM), and D-summation-matrix (DSM) may be dynamically reconfigured to interpret data contained within a fixed external memory data bus (EMB).
However, the prior art of record does not teach or suggest at least iteratively subtracting a corresponding determined first scaler element from a result of each computed first matrix multiplication and computing an elementwise exponential function based on a result of the subtraction operation to generate a plurality of elements of a given row vector of a fourth matrix;
iteratively computing a second matrix multiplication of a given row vector of the fourth matrix and each column vector of a third matrix while summing the given row vectors of the fourth matrix to obtain a second scalar; and
computing a row vector of an output matrix based on results of the second matrix multiplications.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Pub. 20220188075 – related to accelerating deep neural networks (DNNs).
US Pub. 20230008856 - related to performing fixed-point emulation of floating-point computation. In a multiplication operation on two floating-point matrices, the DNN accelerator determines an extreme exponent for a row in the first floating-point matrix and determines another extreme exponent for a column in the second floating-point matrix. The row and column can be converted to fixed-point vectors based on the extreme exponents. The two fixed-point vectors are fed into a PE array in the DNN accelerator. The PE array performs a multiplication operation on the two fixed-point vectors and generates a fixed-point inner product. The fixed-point inner product can be converted back to a floating-point inner product based on the extreme exponents. The floating-point inner product is an element in the matrix resulted from the multiplication operation on the two floating-point matrices. The matrix can be accumulated with another matrix resulted from a fixed-point emulation of a floating-point matrix multiplication.
US Pub. 20240028665 - related to omputing a matrix vector product of a given matrix, wherein the given matrix is represented by S submatrices, with S□1, with each submatrix representing a vertical slice of the given matrix, and with each submatrix approximated by the product of P further matrices, with P□1. Each further matrix is a sparse matrix and includes in each row a certain number of elements unequal to zero. The apparatus has S processing chains, wherein each processing chain is to receive an arbitrary vector and comprises P processing blocks. Each processing block is to multiply a block input vector and an associated further matrix by shifting the elements of the block input vector according to the values of the elements in the associated further matrix which are unequal to zero, and by combining the shifted elements of the block input vector to obtain respective elements of a block output vector.
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/MICHAEL D. YAARY/ Primary Examiner, Art Unit 2151
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