DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/22/2025 is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 11-14 and 16-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jenne et al. (US2019/0012263).
With respect claim 1, Jenne et al. teaches a volatile memory (see Fig. 1 and paragraph 30; volatile memory 134);
a persistent memory to store data persistently (see Fig. 1 and paragraph 30; non-volatile memory 136);
an energy backup device to provide energy to flush data from the volatile memory to the persistent memory in response to detection of a powerdown event (see Fig. 1 and paragraph 30, 39 and 88 and 39; backup power source 150; backup power source 150 represents a battery device that powers NVDIMM 130 and any other NVDIMM devices of information handling system 100, as needed or desired, in order to conduct the runtime save operation on the information handling system. Also in paragraph 28; during a save operation the module can store information from its volatile memory to maintain persistence of the information. The term “save operation” as used herein when used in the context of a memory module, such as NVDIMM 130, is intended to refer to the process of the memory module saving information from its volatile memory to its non-volatile memory at the request of a master device); and
platform hardware to execute a powerdown sequence in response to detection of the powerdown event (see paragraph 26 and 35; system service controller 180 can include an application specific device, such as a CPLD, to implement management functions not appropriate for handling by the CPLD, such as management functions that need to happen in a time critical manner… in response to determining a power failure condition, CPLD can notify the processing complex 120), to manage power usage during the powerdown sequence and manage the flush of data from the volatile memory to the persistent memory (see paragraph 35; in response to determining a power failure condition, CPLD can notify the processing complex 120. For example, according to an embodiment, the processing complex 120 can include a Platform Control Hub (PCH), as used with Intel-based processors, to which the CPLD sends a signal to trigger Asynchronous DRAM Refresh (ADR). In response, the PCH will notify the processing complex 110 to flush its caches, and other volatile information, to NVDIMM 130 in anticipation of losing power After processing complex 110 has finished flushing desired information to the NVDIMM 130, the processing complex 110, in conjunction with the memory controller 120, can place the NVDIMM 130 in self-refresh mode).
With respect claim 11, Jenne et al. teaches wherein the energy backup device comprises a supercapacitor (see Fig. 1 and paragraph 39; power source 150 represents one or more super-capacitors that are configured to provide power to NVDIMM 130 and other NVDIMM devices of information handling system 100, as needed), and wherein the platform hardware is to manage the power usage during the powerdown sequence with a policy specific to supercapacitor backup (see paragraph 88-89; if the back-up power system represents a capacitor, the available hold-up time may be given by E.sub.hold-up=C (V.sub.max−V.sub.min)/2 where C is a capacitance of energy storage device 116, V.sub.max equals a voltage of the energy storage device capacitor when fully charged, and V.sub.min equals the voltage of such capacitor at the end of the hold-up period when it is no longer able to provide energy (which, in some embodiments, may be equal to zero). If the available hold-up energy exceeds the energy E.sub.save needed to perform the save operation, there is sufficient energy to completed the save operation).
With respect claim 12, Jenne et al. teaches wherein the platform hardware is to trigger assert a MEMHOT alert (see paragraph 86; If the received temperature is greater than the threshold temperature, which can be the maximum temperature, the maximum temperature and a margin amount, or the like, a thermal failure condition is detected and the flow proceeds to step 1230, where it is noted that thermal failure has been detected to trigger memory bandwidth throttling (see paragraphs 86-89; in response to a determination that there is insufficient energy available, it is determined if the information handling system can be reconfigured to reduce the energy E.sub.save needed to perform save operations. Reconfiguration may include modifications to reduce cache flush times, including reduced throttling levels of information handling resources of information handling system precluding NVDIMMs from being used, staggering when saved operations of NVDIMMs occur).
With respect claim 13, Jenne et al. teaches a volatile memory (see Fig. 1 and paragraph 30; volatile memory 134);
a persistent memory to store data persistently (see Fig. 1 and paragraph 30; non-volatile memory 136);
an energy backup device to provide energy to flush data from the volatile memory to the persistent memory in response to detection of a powerdown event (see Fig. 1 and paragraph 30, 39 and 88 and 39; backup power source 150; backup power source 150 represents a battery device that powers NVDIMM 130 and any other NVDIMM devices of information handling system 100, as needed or desired, in order to conduct the runtime save operation on the information handling system. Also in paragraph 28; during a save operation the module can store information from its volatile memory to maintain persistence of the information. The term “save operation” as used herein when used in the context of a memory module, such as NVDIMM 130, is intended to refer to the process of the memory module saving information from its volatile memory to its non-volatile memory at the request of a master device);
a central processing unit (CPU) having multiple compute cores (see paragraph 98; system 1500 can include multiple processor cores) and an input/output (IO) control die (see Fig. 15 and paragraph 94; baseboard management controller (BMC) 1580, which can itself be part of a system service controller), the IO control die to receive an indication of the detection of the powerdown event (see paragraph 26 and 35; system service controller 180 can include an application specific device, such as a CPLD, to implement management functions not appropriate for handling by the CPLD, such as management functions that need to happen in a time critical manner… in response to determining a power failure condition, CPLD can notify the processing complex 120), trigger one of the compute cores to perform a flush of data from the volatile memory to the persistent memory, and execute a powerdown sequence specific to a type of the energy backup device (see paragraph 35; in response to determining a power failure condition, CPLD can notify the processing complex 120. For example, according to an embodiment, the processing complex 120 can include a Platform Control Hub (PCH), as used with Intel-based processors, to which the CPLD sends a signal to trigger Asynchronous DRAM Refresh (ADR). In response, the PCH will notify the processing complex 110 to flush its caches, and other volatile information, to NVDIMM 130 in anticipation of losing power After processing complex 110 has finished flushing desired information to the NVDIMM 130, the processing complex 110, in conjunction with the memory controller 120, can place the NVDIMM 130 in self-refresh mode).
With respect claim 14, Jenne et al. teaches wherein the powerdown sequence includes a configurable setting for system fans (see paragraph 80; in response to a power failure, the fan subsystem 1040 can be shutdown or powered by the back-up power source 1051, wherein the control circuitry 1020 of the power-down controller 1011 provides information to the fan controller 1012 indicating to the fan subsystem 1040 that a reduced fan speed should be implemented) and platform subsystems specific to the type of the energy backup device (see paragraph 88-89; if the back-up power system represents a capacitor, the available hold-up time may be given by E.sub.hold-up=C (V.sub.max−V.sub.min)/2 where C is a capacitance of energy storage device 116, V.sub.max equals a voltage of the energy storage device capacitor when fully charged, and V.sub.min equals the voltage of such capacitor at the end of the hold-up period when it is no longer able to provide energy (which, in some embodiments, may be equal to zero). If the available hold-up energy exceeds the energy E.sub.save needed to perform the save operation, there is sufficient energy to completed the save operation).
With respect claim 16, Jenne et al. teaches wherein the powerdown sequence includes a configurable setting for memory bandwidth specific to the type of the energy backup device (see paragraph 59-61; an energy and power characteristic of the system can be determined and NVDIMMs of system 100 are accessed based upon the energy/power characteristics... in response to closed-loop thermal throttling being enabled, a temperature indicator of a temperature sensor is read by a controller of the NVDIMM. At block 510, the temperature indicator is used by the NVDIMM controller to determine a transfer rate).
With respect claim 17, Jenne et al. teaches wherein the powerdown sequence includes a configurable setting for memory refresh (see claim 1; placing the memory module into a self-refresh mode that causes the memory module to refresh the volatile memory; monitoring a characteristic of the information handling system while the memory module is in the self-refresh mode to determine when to initiate a save operation of the memory module, wherein the save operation transfers information stored at the volatile memory to a nonvolatile memory of the memory module) and cache flush specific to the type of the energy backup device (see paragraph 88-89; if the back-up power system represents a capacitor, the available hold-up time may be given by E.sub.hold-up=C (V.sub.max−V.sub.min)/2 where C is a capacitance of energy storage device 116, V.sub.max equals a voltage of the energy storage device capacitor when fully charged, and V.sub.min equals the voltage of such capacitor at the end of the hold-up period when it is no longer able to provide energy (which, in some embodiments, may be equal to zero). If the available hold-up energy exceeds the energy E.sub.save needed to perform the save operation, there is sufficient energy to completed the save operation).
With respect claim 18, Jenne et al. teaches wherein the energy backup device comprises a battery or a supercapacitor (see Fig. 1 and paragraph 39; battery or supercapacitor)., and wherein the powerdown sequence is to manage power usage with a policy specific to battery backup or supercapacitor backup, respectively (see paragraph 88-89; if the back-up power system represents a capacitor, the available hold-up time may be given by E.sub.hold-up=C (V.sub.max−V.sub.min)/2 where C is a capacitance of energy storage device 116, V.sub.max equals a voltage of the energy storage device capacitor when fully charged, and V.sub.min equals the voltage of such capacitor at the end of the hold-up period when it is no longer able to provide energy (which, in some embodiments, may be equal to zero). If the available hold-up energy exceeds the energy E.sub.save needed to perform the save operation, there is sufficient energy to completed the save operation).
With respect claim 19, Jenne et al. teaches wherein the powerdown sequence includes asserting a MEMHOT alert (see paragraph 86; If the received temperature is greater than the threshold temperature, which can be the maximum temperature, the maximum temperature and a margin amount, or the like, a thermal failure condition is detected and the flow proceeds to step 1230, where it is noted that thermal failure has been detected) to trigger memory bandwidth throttling (see paragraphs 86-89; in response to a determination that there is insufficient energy available, it is determined if the information handling system can be reconfigured to reduce the energy E.sub.save needed to perform save operations. Reconfiguration may include modifications to reduce cache flush times, including reduced throttling levels of information handling resources of information handling system precluding NVDIMMs from being used, staggering when saved operations of NVDIMMs occur).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jenne et al. (US2019/0012263) in view of Horning (US5,414,861).
With respect claim 2, Jenne et al. does not teach wherein the platform hardware is to manage the power usage during the powerdown sequence based on user selectable configuration settings.
However, Horning teaches a user programmable power control sequence to selectively provide power to various components and to initiate the transfer of data into a non-volatile memory (see column 4, lines 52-55).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by Jenne et al. to include the above mentioned to efficiently manage the limited power available from a reserve power supply (see Horning, column 1, lines 9-13).
With respect claim 3, Jenne et al. teaches wherein the selectable configuration settings include platform settings to configure power usage for platform components, including system fans (see paragraph 80; in response to a power failure, the fan subsystem 1040 can be shutdown or powered by the back-up power source 1051, wherein the control circuitry 1020 of the power-down controller 1011 provides information to the fan controller 1012 indicating to the fan subsystem 1040 that a reduced fan speed should be implemented).
Claim(s) 4-8, 10 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jenne et al. (US2019/0012263) and Horning (US5,414,861) as applied to claims 1-2 above, and further in view of Ashmore et al. (US2006/0015683)
With respect claim 4, Jenne et al. and Horning do not explicitly teach wherein the selectable configuration settings include central processing unit (CPU) power configuration settings to configure power usage for the CPU
However, Ashmore et al. teaches RAID controller 100 also includes a memory controller 102, coupled to the disk interface 116, host interface 118, cache memory 104, and non-volatile memory 108. The memory controller 102 controls accesses by the disk interface 116, host interface 118, and CPU subsystem 112 to the cache memory 104 and non-volatile memory 108 (see paragraph 36). RAID controller 100 also includes a power regulator 134, coupled to receive power from both the capacitors 136 and the main power source. The power regulator 134 senses whether the main power source is supplying power, and if so, regulates the main power source to provide power to the various RAID controller 100 circuits… In the embodiment of FIG. 1, when main power is lost, the capacitors 136 supply power only to the cache memory 104, the non-volatile memory 108, the memory controller 102, and power manager 132, and other circuits required to keep those circuits operational (see paragraphs 38 and 40)
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by Jenne et al. and Horning to include the above mentioned to preserve write-cached data during the loss of main power (see Ashmore, paragraph 3).
With respect claim 5, Jenne et al. and Horning do not explicitly teach wherein the CPU power configuration settings comprise a setting to disable a CPU core for the powerdown sequence.
However, Ashmore et al. teaches wherein RAID controller 100 also includes a power regulator 134, coupled to receive power from both the capacitors 136 and the main power source. The power regulator 134 senses whether the main power source is supplying power, and if so, regulates the main power source to provide power to the various RAID controller 100 circuits… In the embodiment of FIG. 1, when main power is lost, the capacitors 136 supply power only to the cache memory 104, the non-volatile memory 108, the memory controller 102, and power manager 132 (i.e., CPU 112 subsystem not powered/ disabled) (see paragraphs 38 and 40).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by Jenne et al. and Horning to include the above mentioned to preserve write-cached data during the loss of main power (see Ashmore, paragraph 3).
With respect claim 6, Jenne et al. and Horning do not explicitly wherein the selectable configuration settings include memory settings to configure power usage for memory components.
However, Ashmore et al. teaches wherein RAID controller 100 also includes a power regulator 134, coupled to receive power from both the capacitors 136 and the main power source. The power regulator 134 senses whether the main power source is supplying power, and if so, regulates the main power source to provide power to the various RAID controller 100 circuits… In the embodiment of FIG. 1, when main power is lost, the capacitors 136 supply power only to the cache memory 104, the non-volatile memory 108, the memory controller 102, and power manager 132 (i.e., CPU 112 subsystem not powered/ disabled) (see paragraphs 38 and 40).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by Jenne et al. and Horning to include the above mentioned to preserve write-cached data during the loss of main power (see Ashmore, paragraph 3).
With respect claim 7, Jenne et al. teaches wherein the memory settings comprise a setting to place system memory in self-refresh prior to a cache flush and drop writes to volatile address ranges (see claim 1; placing the memory module into a self-refresh mode that causes the memory module to refresh the volatile memory; monitoring a characteristic of the information handling system while the memory module is in the self-refresh mode to determine when to initiate a save operation of the memory module, wherein the save operation transfers information stored at the volatile memory to a nonvolatile memory of the memory module).
With respect claim 8, Jenne et al. teaches wherein the memory settings comprise a setting to throttle memory bandwidth (see paragraph 59-61; an energy and power characteristic of the system can be determined and NVDIMMs of system 100 are accessed based upon the energy/power characteristics... in response to closed-loop thermal throttling being enabled, a temperature indicator of a temperature sensor is read by a controller of the NVDIMM. At block 510, the temperature indicator is used by the NVDIMM controller to determine a transfer rate)..
With respect claim 10, Jenne et al. teaches wherein the energy backup device comprises a battery (see Fig. 1 and paragraph 39; backup power source 150 represents a battery device that powers NVDIMM 130 and any other NVDIMM devices of information handling system 100).
Jenne et al. and Horning do not explicitly teach wherein the platform hardware is to manage the power usage during the powerdown sequence with a policy specific to battery backup.
However, Ashmore et al. teaches wherein the memory controller 102 performs the flush operation, such that the battery 826 does not supply power to the CPU subsystem 112 during the flush operation (see paragraph 100).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by Jenne et al. and Horning to include the above mentioned to preserve write-cached data during the loss of main power (see Ashmore, paragraph 3).
With respect claim 15, Jenne et al. teaches wherein the powerdown sequence includes a configurable setting for CPU core usage and system memory usage specific to the type of the energy backup device.
However, Ashmore et al. teaches wherein RAID controller 100 also includes a power regulator 134, coupled to receive power from both the capacitors 136 and the main power source. The power regulator 134 senses whether the main power source is supplying power, and if so, regulates the main power source to provide power to the various RAID controller 100 circuits… In the embodiment of FIG. 1, when main power is lost, the capacitors 136 supply power only to the cache memory 104, the non-volatile memory 108, the memory controller 102, and power manager 132 (i.e., CPU 112 subsystem not powered/ disabled) (see paragraphs 38 and 40).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Jenne et al. to include the above mentioned to preserve write-cached data during the loss of main power (see Ashmore, paragraph 3).
Allowable Subject Matter
Claims 9 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Benhase et al. (US 2006/0106990) teaches flushing modified cache data from a processor cache to nonvolatile memory in response to power loss.
Spears et al. (US6,304,981) teaches systems and related devices which store data in at least one of volatile and non-volatile memory, and more particularly to a system and method for controlling the shutdown of an information handling system.
Watson et al. (US9,223,664) teaches enabling one or more solid state drives to be powered by an energy storage device during a power failure to the primary power source.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARACELIS RUIZ whose telephone number is (571)270-1038. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G. Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ARACELIS RUIZ/Primary Examiner, Art Unit 2139