Prosecution Insights
Last updated: July 17, 2026
Application No. 18/092,605

MULTI-LAYER POWER TRANSFORMER WITH IMPROVED AC AND DC RESISTANCE

Final Rejection §102
Filed
Jan 03, 2023
Examiner
LIAN, MANG TIN BIK
Art Unit
2837
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Infineon Technologies AG
OA Round
2 (Final)
70%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 70% — above average
70%
Career Allowance Rate
933 granted / 1330 resolved
+2.2% vs TC avg
Strong +26% interview lift
Without
With
+26.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
68 currently pending
Career history
1401
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
91.7%
+51.7% vs TC avg
§102
6.4%
-33.6% vs TC avg
§112
1.2%
-38.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1330 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments with respect to claims 1-15 and 20-30 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The drawings replacement submitted on 05/06/2026 is acceptable. However, the drawings objection made in the Office action dated 02/06/2026 was not addressed in the reply filed on 05/06/2026. Accordingly, the drawings objection made in the Office action mailed on 02/06/2026 is maintained. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “circuit is directly coupled between a first node of the secondary winding and a second node of the secondary winding” as recited in claim 2, the different limitations of claim 4, the “a vertical capacitor and a vertical field effect transistor” of claim 6, the “the primary winding resides within a first plane; wherein the second winding resides within a second plane, the second plane substantially parallel to the first plane” as recited in claim 8, the “a reference voltage node disposed in a circuit layer in which the primary winding resides; and wherein the circuit is disposed between the reference voltage node and the secondary winding” as claimed in claim 14 and similar limitations in claim 15 and the “electrical coupling of the circuit between a first node of the secondary winding and a second node of the secondary winding” of claim 20 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-15 and 20-30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zeng et al. (U.S. PG. Pub. No. 2019/0199232 A1, hereinafter “Zeng”). With respect to claim 1, Zeng teaches a multi-layer transformer assembly (Figs. 16 and or 17) comprising: a primary winding 231 disposed in a first layer (top or bottom layer of the multilayer circuit board unit 23) of the multi-layer transformer assembly; a secondary winding 232 disposed in a second layer (layer in which winding 232 is disposed) of the multi-layer transformer assembly, the secondary winding magnetically coupled to the primary winding; an intermediary layer (layer between primary and secondary winding) disposed between the primary winding in the first layer and the secondary winding in the second layer; and a circuit (switch 233 and or “capacitor” para. [0074] and as seen in Fig. 17) disposed in the intermediary layer, the circuit disposed between the primary winding in the first layer and the secondary winding in the second layer, the circuit electrically coupled to the secondary winding (paras. [0071], [0072] and [0074]). PNG media_image1.png 207 428 media_image1.png Greyscale With respect to claim 2, Zeng teaches the multi-layer transformer assembly as in claim 1, wherein the circuit is directly coupled between a first node n1 (annotated Fig. 17) of the secondary winding and a second node n2 of the secondary winding (para. [0074]). PNG media_image2.png 243 293 media_image2.png Greyscale With respect to claim 3, Zeng teaches the multi-layer transformer assembly as in claim 1, wherein the circuit is operative to control a flow of current through the secondary winding (paras. [0071] and [0074]). With respect to claim 4, Zeng teaches the multi-layer transformer assembly as in claim 1, wherein the circuit includes a capacitor (“capacitor” para. [0074]) and a switch 233 disposed in series; wherein the capacitor is coupled between a first node Cn1 (annotated Fig. 17) of the circuit and a second node Cn2 of the circuit; wherein the switch is coupled between the second node Cn2 of the circuit and a third node Cn3 of the circuit; wherein the first node Cn1 of the circuit is directly coupled to a first node Sn1 of the secondary winding; and wherein the third node Cn3 of the circuit is directly coupled to a second node Sn2 of the secondary winding (para. [0074]). With respect to claim 5, Zeng teaches the multi-layer transformer assembly as in claim 4, wherein the circuit includes a first facing (lower face) and a second facing (upper face); wherein the first node of the circuit and the third node of the circuit are disposed on the first facing of the circuit; and wherein the second node of the circuit is disposed on the second facing of the circuit, the second facing opposite the first facing (paras. [0071] and [0074]). With respect to claim 6, Zeng teaches the multi-layer transformer assembly as in claim 1, wherein the circuit includes a vertical capacitor (“capacitor” para. [0074]) and a vertical field effect transistor (transistor as seen in Fig. 1) (paras. [0006] and [0074]). With respect to claim 7, Zeng teaches the multi-layer transformer assembly as in claim 6, wherein a first node Cn2 of the vertical capacitor is directly coupled to a first node (end of switch 233) of the switch via an electrically conductive path (line connection between capacitor and switch 233); wherein a second node Cn1 of the vertical capacitor is directly coupled to a first node Sn1 of the secondary winding; and wherein a second node Sn2 of the vertical switch is directly coupled to the second node of the secondary winding (paras. [0006] and [0074]). With respect to claim 8, Zeng teaches the multi-layer transformer assembly as in claim 7, wherein the primary winding resides within a first plane (a plane in which primary winding is disposed); wherein the second winding resides within a second plane (a plane in which secondary winding is disposed), the second plane substantially parallel to the first plane; wherein the intermediary layer resides between the first plane and the second plane (para. [0071], [0072] and [0074]). With respect to claim 9, Zeng teaches the multi-layer transformer assembly as in claim 1, wherein the circuit includes a capacitor (“capacitor” para. [0074]) and a switch 233; and wherein a combination of the secondary winding, the switch, and the capacitor are connected in series (para. [0074]). With respect to claim 10, Zeng teaches the multi-layer transformer assembly as in claim 9, wherein the combination of the secondary winding, the switch, and the capacitor form a series circuit loop (para. [0074]). With respect to claim 11, Zeng teaches the multi-layer transformer assembly as in claim 1, wherein the intermediary layer includes a substrate (the multilayer circuit board 23 has “no gaps,” so the intermediary layer would have “a substrate” as claimed); wherein the primary winding is affixed to a first surface (surface on which primary winding is fixed) of the substrate; and wherein the secondary winding is affixed to a second surface (surface on which secondary winding is fixed) of the substrate (para. [0071]). With respect to claim 12, Zeng teaches the multi-layer transformer assembly as in claim 1 further comprising: a core 221 of magnetic permeable material passing through the intermediary layer; wherein the primary winding is wrapped around the core; and wherein the secondary winding is wrapped around the core (para. [0071]). With respect to claim 13, Zeng teaches the multi-layer transformer assembly as in claim 1, wherein the intermediary layer includes a substrate (the multilayer circuit board 23 has “no gaps,” so the intermediary layer would have “a substrate” as claimed), the circuit disposed in an inlay of the substrate (para. [0071]). With respect to claim 14, Zeng teaches the multi-layer transformer assembly as in claim 1 further comprising: a reference voltage node disposed in a circuit layer in which the primary winding resides; and wherein the circuit is disposed between the reference voltage node and the secondary winding (para. [0074]). With respect to claim 15, Zeng teaches the multi-layer transformer assembly as in claim 1 further comprising: a reference voltage node disposed in a circuit layer in which the primary winding resides, the reference node not electrically connected to the primary winding; wherein the circuit includes a first circuit component, a first surface node of the first circuit component electrically coupled directly to the reference voltage node, a second surface node of the first circuit component electrically coupled directly to the secondary winding (paras. [0071] and [0074]). With respect to claim 20, Zeng teaches a method comprising: fabricating an intermediary layer (layer between primary 231 and secondary winding 232 of the multilayer circuit board 23) between a first layer (top or bottom layer of the multilayer circuit board unit 23) and a second layer (layer in which winding 232 is disposed) of a multi-layer transformer assembly (Fig. 16), the first layer fabricated to include a primary winding 231 of the multi-layer transformer assembly, the second layer fabricated to include a secondary winding 232 of the multi-layer transformer assembly, the secondary winding magnetically coupled to the primary winding, the intermediary layer fabricated to include a circuit (switch 233 and or “capacitor” para. [0074] and as seen in Fig. 17) disposed between the first layer and the second layer, the circuit operative to control flow of current through the secondary winding; and providing electrical coupling of the circuit between a first node Sn1 (annotated Fig. 17) of the secondary winding and a second node Sn2 of the secondary winding (paras. [0071], [0072] and [0074]). With respect to claim 21, Zeng teaches the multi-layer transformer assembly as in claim 1, wherein the circuit includes a switch 233 and a capacitor (“capacitor” para. [0074]) disposed in the intermediary layer; and wherein a combination of the secondary winding, the switch, and the capacitor form a series circuit loop (para. [0074]). With respect to claim 22, Zeng teaches the multi-layer transformer assembly as in claim 21, wherein the secondary winding extends between a first node Sn1 in the second layer and a second node Sn2 in the second layer; wherein the switch includes a first switch node Cn3 and a second switch node S2n; wherein the capacitor includes a first capacitor node Cn1 and a second capacitor node Cn2; and wherein the series circuit loop includes: i) a first direct connection between the first node in the second layer and the first switch node of the switch, ii) a second direct connection between the second switch node of the switch and a third node, iii) a third direction connection between the third node and the first capacitor node of the capacitor, and iv) a fourth direct connection between the second capacitor node of the capacitor and the second node in the second layer (para. [0074]). With respect to claim 23, Zeng teaches the multi-layer transformer assembly as in claim 22, wherein the third node is disposed in the second layer (para. [0074]). With respect to claim 24, Zeng teaches the multi-layer transformer assembly as in claim 23 further comprising: magnetically permeable material 221 disposed in the intermediary layer; and wherein the secondary winding extends in the second layer from the first node to the second node around the magnetically permeable material (para. 0071]). With respect to claim 25, Zeng teaches the multi-layer transformer assembly as in claim 24, wherein the switch is operative to control flow of current through the secondary winding; and wherein the controlled flow of current through the secondary winding is operative to produce an output voltage outputted from the second node of the secondary winding (para. [0071] and [0074]). With respect to claim 26, Zeng teaches the multi-layer transformer assembly as in claim 25, wherein the second node of the secondary winding is a center tap node of a transformer winding (para. [0074]). With respect to claim 27, Zeng teaches the multi-layer transformer assembly as in claim 1, wherein a combination of the circuit and the secondary winding are disposed in a closed series circuit loop (para. [0074]). With respect to claim 28, Zeng teaches the multi-layer transformer assembly as in claim 27, wherein the circuit includes a switch 233 and a capacitor (“capacitor” para. [0074]); wherein the secondary winding extends between a first node Sn1 in the second layer and a second node Sn2 in the second layer; wherein the switch includes a first switch node Cn3 and a second switch node Sn2; wherein the capacitor includes a first capacitor node Cn1 and a second capacitor node Cn2; and wherein the series circuit loop includes: i) a first direct connection between the first node in the second layer and the first switch node of the switch, ii) a second direct connection between the second switch node of the switch and a third node, iii) a third direction connection between the third node and the first capacitor node of the capacitor, and iv) a fourth direct connection between the second capacitor node of the capacitor and the second node in the second layer (para. [0074]). With respect to claim 29, Zeng teaches the multi-layer transformer assembly as in claim 28, wherein the switch is a field effect transistor; wherein the first switch node is a drain node of the field effect transistor; and wherein the second switch node is a source node of the field effect transistor (para. [0006]). With respect to claim 30, Zeng teaches the multi-layer transformer assembly as in claim 28 further comprising: magnetically permeable material 221 disposed in the intermediary layer; and wherein the secondary winding extends in the second layer from the first node to the second node around a first portion of the magnetically permeable material (para. [0071]). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MANGTIN LIAN whose telephone number is (571)270-5729. The examiner can normally be reached Monday-Friday 0800-1700. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Shawki S. Ismail can be reached at 571-272-3985. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MANG TIN BIK LIAN/ Primary Examiner, Art Unit 2837
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Prosecution Timeline

Jan 03, 2023
Application Filed
Feb 06, 2026
Non-Final Rejection mailed — §102
May 06, 2026
Response Filed
Jun 22, 2026
Final Rejection mailed — §102 (current)

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Prosecution Projections

3-4
Expected OA Rounds
70%
Grant Probability
97%
With Interview (+26.4%)
2y 7m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1330 resolved cases by this examiner. Grant probability derived from career allowance rate.

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